include/VBox/dis.h

	dis.h revision 0aa1ba1d1ea27baa7762e4fe891824df38697189
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @file
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DIS - The VirtualBox Disassembler.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * Copyright (C) 2006-2012 Oracle Corporation
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * available from http://www.virtualbox.org. This file is free software;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * you can redistribute it and/or modify it under the terms of the GNU
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * General Public License (GPL) as published by the Free Software
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * The contents of this file may alternatively be used under the terms
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * of the Common Development and Distribution License Version 1.0
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VirtualBox OSE distribution, in which case the provisions of the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * CDDL are applicable instead of those of the GPL.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * You may elect to license modified versions of this file under the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * terms and conditions of either the GPL or the CDDL or both.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
88350256a6c78b8631aba5aa5ce249d90a8514a2vboxsync#ifndef ___VBox_dis_h
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define ___VBox_dis_h
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/types.h>
943d182735b76ecae26ea011cb7b87e449aafea8vboxsync#include <VBox/disopcode.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/assert.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncRT_C_DECLS_BEGIN
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * CPU mode flags (DISCPUSTATE::mode).
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsynctypedef enum DISCPUMODE
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    DISCPUMODE_INVALID = 0,
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    DISCPUMODE_16BIT,
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    DISCPUMODE_32BIT,
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    DISCPUMODE_64BIT,
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    /** hack forcing the size of the enum to 32-bits. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync} DISCPUMODE;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Prefix byte flags (DISCPUSTATE::prefix_rex).
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_NONE                  UINT8_C(0x00)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** non-default address size. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_ADDRSIZE              UINT8_C(0x01)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** non-default operand size. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_OPSIZE                UINT8_C(0x02)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** lock prefix. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_LOCK                  UINT8_C(0x04)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** segment prefix. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_SEG                   UINT8_C(0x08)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** rep(e) prefix (not a prefix, but we'll treat is as one). */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REP                   UINT8_C(0x10)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** rep(e) prefix (not a prefix, but we'll treat is as one). */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REPNE                 UINT8_C(0x20)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** REX prefix (64 bits) */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX                   UINT8_C(0x40)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name 64 bits prefix byte flags (DISCPUSTATE::prefix_rex).
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Requires VBox/disopcode.h.
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISPREFIX_REX_OP_2_FLAGS(a)     (a - OP_PARM_REX_START)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS             DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_B           DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_X           DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_XB          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_R           DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_RB          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_RX          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_RXB         DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_W           DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WB          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WX          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WXB         DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WR          DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WRB         DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WRX         DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISPREFIX_REX_FLAGS_WRXB        DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Operand type.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_INVALID                  RT_BIT_32(0)
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync#define DISOPTYPE_HARMLESS                 RT_BIT_32(1)
b28fef07fef379ecc179e0bc0d5d1be753e482b5vboxsync#define DISOPTYPE_CONTROLFLOW              RT_BIT_32(2)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_POTENTIALLY_DANGEROUS    RT_BIT_32(3)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_DANGEROUS                RT_BIT_32(4)
257927abbaa6d9774427049fcbea552cda362281vboxsync#define DISOPTYPE_PORTIO                   RT_BIT_32(5)
257927abbaa6d9774427049fcbea552cda362281vboxsync#define DISOPTYPE_PRIVILEGED               RT_BIT_32(6)
257927abbaa6d9774427049fcbea552cda362281vboxsync#define DISOPTYPE_PRIVILEGED_NOTRAP        RT_BIT_32(7)
257927abbaa6d9774427049fcbea552cda362281vboxsync#define DISOPTYPE_UNCOND_CONTROLFLOW       RT_BIT_32(8)
24a8dd4360c4b4588fd2c340dd7687379a45e02evboxsync#define DISOPTYPE_RELATIVE_CONTROLFLOW     RT_BIT_32(9)
3c49234930c10a52368b992781dae0306a72b5f5vboxsync#define DISOPTYPE_COND_CONTROLFLOW         RT_BIT_32(10)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_INTERRUPT                RT_BIT_32(11)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_ILLEGAL                  RT_BIT_32(12)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_RRM_DANGEROUS            RT_BIT_32(14)  /**< Some additional dangerous ones when recompiling raw r0. */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISOPTYPE_RRM_DANGEROUS_16         RT_BIT_32(15)  /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
1d17a5f9688f3622ffe088b664588629b1e95801vboxsync#define DISOPTYPE_RRM_MASK                 (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISOPTYPE_INHIBIT_IRQS             RT_BIT_32(16)  /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_PORTIO_READ              RT_BIT_32(17)
81d1b221c2dfff6900e970e273dbb4e81ef6b5d9vboxsync#define DISOPTYPE_PORTIO_WRITE             RT_BIT_32(18)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_INVALID_64               RT_BIT_32(19)  /**< Invalid in 64 bits mode */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_ONLY_64                  RT_BIT_32(20)  /**< Only valid in 64 bits mode */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_DEFAULT_64_OP_SIZE       RT_BIT_32(21)  /**< Default 64 bits operand size */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_FORCED_64_OP_SIZE        RT_BIT_32(22)  /**< Forced 64 bits operand size; regardless of prefix bytes */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_REXB_EXTENDS_OPREG       RT_BIT_32(23)  /**< REX.B extends the register field in the opcode byte */
254365851c06fac7efeae0a0bf727ed6c6940611vboxsync#define DISOPTYPE_MOD_FIXED_11             RT_BIT_32(24)  /**< modrm.mod is always 11b */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_FORCED_32_OP_SIZE_X86    RT_BIT_32(25)  /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISOPTYPE_ALL                      UINT32_C(0xffffffff)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @}  */
254365851c06fac7efeae0a0bf727ed6c6940611vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Parameter usage flags.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
254365851c06fac7efeae0a0bf727ed6c6940611vboxsync#define DISUSE_BASE                        RT_BIT_64(0)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_INDEX                       RT_BIT_64(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_SCALE                       RT_BIT_64(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_GEN8                    RT_BIT_64(3)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DISUSE_REG_GEN16                   RT_BIT_64(4)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DISUSE_REG_GEN32                   RT_BIT_64(5)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DISUSE_REG_GEN64                   RT_BIT_64(6)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DISUSE_REG_FP                      RT_BIT_64(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_MMX                     RT_BIT_64(8)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_XMM                     RT_BIT_64(9)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_CR                      RT_BIT_64(10)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_DBG                     RT_BIT_64(11)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_SEG                     RT_BIT_64(12)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_REG_TEST                    RT_BIT_64(13)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_DISPLACEMENT8               RT_BIT_64(14)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_DISPLACEMENT16              RT_BIT_64(15)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_DISPLACEMENT32              RT_BIT_64(16)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_DISPLACEMENT64              RT_BIT_64(17)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_RIPDISPLACEMENT32           RT_BIT_64(18)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE8                  RT_BIT_64(19)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE8_REL              RT_BIT_64(20)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISUSE_IMMEDIATE16                 RT_BIT_64(21)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE16_REL             RT_BIT_64(22)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE32                 RT_BIT_64(23)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISUSE_IMMEDIATE32_REL             RT_BIT_64(24)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE64                 RT_BIT_64(25)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE64_REL             RT_BIT_64(26)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE_ADDR_0_32         RT_BIT_64(27)
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DISUSE_IMMEDIATE_ADDR_16_32        RT_BIT_64(28)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE_ADDR_0_16         RT_BIT_64(29)
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DISUSE_IMMEDIATE_ADDR_16_16        RT_BIT_64(30)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** DS:ESI */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DISUSE_POINTER_DS_BASED            RT_BIT_64(31)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** ES:EDI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_POINTER_ES_BASED            RT_BIT_64(32)
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DISUSE_IMMEDIATE16_SX8             RT_BIT_64(33)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISUSE_IMMEDIATE32_SX8             RT_BIT_64(34)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISUSE_IMMEDIATE64_SX8             RT_BIT_64(36)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync/** Mask of immediate use flags. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISUSE_IMMEDIATE                   ( DISUSE_IMMEDIATE8 \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE16 \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE32 \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE64 \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE8_REL \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE16_REL \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE32_REL \
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                                           | DISUSE_IMMEDIATE64_REL \
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync                                           | DISUSE_IMMEDIATE_ADDR_0_32 \
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync                                           | DISUSE_IMMEDIATE_ADDR_16_32 \
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync                                           | DISUSE_IMMEDIATE_ADDR_0_16 \
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync                                           | DISUSE_IMMEDIATE_ADDR_16_16 \
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync                                           | DISUSE_IMMEDIATE16_SX8 \
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync                                           | DISUSE_IMMEDIATE32_SX8 \
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync                                           | DISUSE_IMMEDIATE64_SX8)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync/** Check if the use flags indicates an effective address. */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!(  (a_fUseFlags) \
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync                                                  & (  DISUSE_BASE  \
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync                                                     | DISUSE_INDEX \
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync                                                     | DISUSE_DISPLACEMENT32 \
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync                                                     | DISUSE_DISPLACEMENT64 \
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync                                                     | DISUSE_DISPLACEMENT16 \
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync                                                     | DISUSE_DISPLACEMENT8 \
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync                                                     | DISUSE_RIPDISPLACEMENT32) ))
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/** @} */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/** @name 64-bit general register indexes.
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync * This matches the AMD64 register encoding.  It is found used in
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @note  Safe to assume same values as the 16-bit and 32-bit general registers.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RAX                     UINT8_C(0)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RCX                     UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RDX                     UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RBX                     UINT8_C(3)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RSP                     UINT8_C(4)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RBP                     UINT8_C(5)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RSI                     UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_RDI                     UINT8_C(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R8                      UINT8_C(8)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R9                      UINT8_C(9)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R10                     UINT8_C(10)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R11                     UINT8_C(11)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R12                     UINT8_C(12)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R13                     UINT8_C(13)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R14                     UINT8_C(14)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R15                     UINT8_C(15)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync/** @} */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name 32-bit general register indexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
f1acc1e99894e016bd1a6ee65c56b3fc064fa4ebvboxsync * @note  Safe to assume same values as the 16-bit and 64-bit general registers.
09ed5ee011f3a6cd9d4742216ad3bb7dbf855641vboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_EAX                     UINT8_C(0)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_ECX                     UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_EDX                     UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_EBX                     UINT8_C(3)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_ESP                     UINT8_C(4)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_EBP                     UINT8_C(5)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_ESI                     UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_EDI                     UINT8_C(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R8D                     UINT8_C(8)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R9D                     UINT8_C(9)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R10D                    UINT8_C(10)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R11D                    UINT8_C(11)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R12D                    UINT8_C(12)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R13D                    UINT8_C(13)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R14D                    UINT8_C(14)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R15D                    UINT8_C(15)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
45c2de093cddc990b8d1583aa49b9a40de7a3d97vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name 16-bit general register indexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @note  Safe to assume same values as the 32-bit and 64-bit general registers.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_AX                      UINT8_C(0)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_CX                      UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_DX                      UINT8_C(2)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync#define DISGREG_BX                      UINT8_C(3)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync#define DISGREG_SP                      UINT8_C(4)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync#define DISGREG_BP                      UINT8_C(5)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync#define DISGREG_SI                      UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_DI                      UINT8_C(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R8W                     UINT8_C(8)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISGREG_R9W                     UINT8_C(9)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R10W                    UINT8_C(10)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R11W                    UINT8_C(11)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R12W                    UINT8_C(12)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISGREG_R13W                    UINT8_C(13)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R14W                    UINT8_C(14)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R15W                    UINT8_C(15)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync/** @name 8-bit general register indexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This mostly (?) matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync */
47eb60db91f50291b3bd9b72b64d36341972a155vboxsync#define DISGREG_AL                      UINT8_C(0)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISGREG_CL                      UINT8_C(1)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISGREG_DL                      UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_BL                      UINT8_C(3)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync#define DISGREG_AH                      UINT8_C(4)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync#define DISGREG_CH                      UINT8_C(5)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_DH                      UINT8_C(6)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_BH                      UINT8_C(7)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_R8B                     UINT8_C(8)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_R9B                     UINT8_C(9)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_R10B                    UINT8_C(10)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_R11B                    UINT8_C(11)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R12B                    UINT8_C(12)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R13B                    UINT8_C(13)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R14B                    UINT8_C(14)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_R15B                    UINT8_C(15)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_SPL                     UINT8_C(16)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync#define DISGREG_BPL                     UINT8_C(17)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_SIL                     UINT8_C(18)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISGREG_DIL                     UINT8_C(19)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Segment registerindexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This matches the AMD64 register encoding.  It is found used in
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync * DISOPPARAM::base.reg_seg.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync */
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsynctypedef enum
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    DISSELREG_ES = 0,
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    DISSELREG_CS = 1,
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    DISSELREG_SS = 2,
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    DISSELREG_DS = 3,
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    DISSELREG_FS = 4,
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    DISSELREG_GS = 5,
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    /** The usual 32-bit paranoia. */
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    DIS_SEGREG_32BIT_HACK = 0x7fffffff
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync} DISSELREG;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @} */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync/** @name FPU register indexes.
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync * This matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_fp.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISFPREG_ST0                    UINT8_C(0)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISFPREG_ST1                    UINT8_C(1)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISFPREG_ST2                    UINT8_C(2)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISFPREG_ST3                    UINT8_C(3)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISFPREG_ST4                    UINT8_C(4)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISFPREG_ST5                    UINT8_C(5)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISFPREG_ST6                    UINT8_C(6)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISFPREG_ST7                    UINT8_C(7)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync/** @}  */
aca7a56d52c58d8b388343450503c22822fd6620vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync/** @name Control register indexes.
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * This matches the AMD64 register encoding.  It is found used in
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * DISOPPARAM::base.reg_ctrl.
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * @{
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync */
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISCREG_CR0                     UINT8_C(0)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISCREG_CR1                     UINT8_C(1)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISCREG_CR2                     UINT8_C(2)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync#define DISCREG_CR3                     UINT8_C(3)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISCREG_CR4                     UINT8_C(4)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISCREG_CR8                     UINT8_C(8)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/** @}  */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/** @name Debug register indexes.
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * This matches the AMD64 register encoding.  It is found used in
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * DISOPPARAM::base.reg_dbg.
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * @{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISDREG_DR0                     UINT8_C(0)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISDREG_DR1                     UINT8_C(1)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISDREG_DR2                     UINT8_C(2)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DISDREG_DR3                     UINT8_C(3)
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync#define DISDREG_DR4                     UINT8_C(4)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISDREG_DR5                     UINT8_C(5)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISDREG_DR6                     UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISDREG_DR7                     UINT8_C(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @}  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name MMX register indexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_mmx.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX0                    UINT8_C(0)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX1                    UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX2                    UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX3                    UINT8_C(3)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX4                    UINT8_C(4)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX5                    UINT8_C(5)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX6                    UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISMREG_MMX7                    UINT8_C(7)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync/** @}  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name SSE register indexes.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This matches the AMD64 register encoding.  It is found used in
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * DISOPPARAM::base.reg_xmm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM0                    UINT8_C(0)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISXREG_XMM1                    UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM2                    UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM3                    UINT8_C(3)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM4                    UINT8_C(4)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM5                    UINT8_C(5)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DISXREG_XMM6                    UINT8_C(6)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISXREG_XMM7                    UINT8_C(7)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @}  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISQPV_FLAG_8                   UINT8_C(0x01)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISQPV_FLAG_16                  UINT8_C(0x02)
47eb60db91f50291b3bd9b72b64d36341972a155vboxsync#define DISQPV_FLAG_32                  UINT8_C(0x04)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISQPV_FLAG_64                  UINT8_C(0x08)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DISQPV_FLAG_FARPTR16            UINT8_C(0x10)
4d5da2bfd5523ad009912e6e0cfb8bf480160e32vboxsync#define DISQPV_FLAG_FARPTR32            UINT8_C(0x20)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @}  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * @{ */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISQPV_TYPE_REGISTER            UINT8_C(1)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISQPV_TYPE_ADDRESS             UINT8_C(2)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DISQPV_TYPE_IMMEDIATE           UINT8_C(3)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @}  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsynctypedef struct
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    union
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        uint8_t     val8;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        uint16_t    val16;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        uint32_t    val32;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        uint64_t    val64;
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        struct
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            uint16_t sel;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            uint32_t offset;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        } farptr;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    } val;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    uint8_t         type;
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    uint8_t         size;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    uint8_t         flags;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync} DISQPVPARAMVAL;
/** Pointer to opcode parameter value. */
typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;

/** Indicates which parameter DISQueryParamVal should operate on. */
typedef enum DISQPVWHICH
{
    DISQPVWHICH_DST = 1,
    DISQPVWHICH_SRC,
    DISQPVWHAT_32_BIT_HACK = 0x7fffffff
} DISQPVWHICH;


/**
 * Operand Parameter.
 */
typedef struct DISOPPARAM
{
    uint64_t        parval;
    /** A combination of DISUSE_XXX. */
    uint64_t        fUse;
    union
    {
        int64_t     i64;
        int32_t     i32;
        int32_t     i16;
        int32_t     i8;
        uint64_t    u64;
        uint32_t    u32;
        uint32_t    u16;
        uint32_t    u8;
    } uDisp;
    int32_t         param;

    union
    {
        /** DISGREG_XXX. */
        uint8_t     reg_gen;
        /** DISFPREG_XXX */
        uint8_t     reg_fp;
        /** DISMREG_XXX. */
        uint8_t     reg_mmx;
        /** DISXREG_XXX. */
        uint8_t     reg_xmm;
        /** DISSELREG_XXX. */
        uint8_t     reg_seg;
        /** TR0-TR7  (no defines for these). */
        uint8_t     reg_test;
        /** DISCREG_XXX */
        uint8_t     reg_ctrl;
        /** DISDREG_XXX */
        uint8_t     reg_dbg;
    } base;
    union
    {
        /** DISGREG_XXX. */
        uint8_t     reg_gen;
    } index;

    /** 2, 4 or 8. */
    uint8_t         scale;
    /** Parameter size. */
    uint8_t         cb;
} DISOPPARAM;
AssertCompileSize(DISOPPARAM, 32);
/** Pointer to opcode parameter. */
typedef DISOPPARAM *PDISOPPARAM;
/** Pointer to opcode parameter. */
typedef const DISOPPARAM *PCOP_PARAMETER;


/** Pointer to const opcode. */
typedef const struct DISOPCODE *PCDISOPCODE;

/**
 * Callback for reading opcode bytes.
 *
 * @param   pDisState       Pointer to the CPU state.  The primary user argument
 *                          can be retrived from DISCPUSTATE::apvUserData[0]. If
 *                          more is required these can be passed in the
 *                          subsequent slots.
 * @param   pbDst           Pointer to output buffer.
 * @param   uSrcAddr        The address to start reading at.
 * @param   cbToRead        The number of bytes to read.
 */
typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
/** Pointer to a opcode byte reader. */
typedef FNDISREADBYTES *PFNDISREADBYTES;

/** Parser callback.
 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCDISOPCODE pOp, PDISOPPARAM pParam, PDISCPUSTATE pCpu);
typedef FNDISPARSE *PFNDISPARSE;
typedef PFNDISPARSE const *PCPFNDISPARSE;

typedef struct DISCPUSTATE
{
    /* Because of apvUserData[1] and apvUserData[2], put the less frequently
       used bits at the top for now.  (Might be better off in the middle?) */
    DISOPPARAM      param3;
    DISOPPARAM      param2;
    DISOPPARAM      param1;

    /* off: 0x060 (96) */
    /** ModRM fields. */
    union
    {
        /** Bitfield view */
        struct
        {
            unsigned        Rm  : 4;
            unsigned        Reg : 4;
            unsigned        Mod : 2;
        } Bits;
        /** unsigned view */
        unsigned            u;
    } ModRM;
    /** SIB fields. */
    union
    {
        /** Bitfield view */
        struct
        {
            unsigned        Base  : 4;
            unsigned        Index : 4;
            unsigned        Scale : 2;
        } Bits;
        /** unsigned view */
        unsigned            u;
    } SIB;
    int32_t         i32SibDisp;

    /* off: 0x06c (108) */
    /** The CPU mode (DISCPUMODE). */
    uint8_t         mode;
    /** The addressing mode (DISCPUMODE). */
    uint8_t         addrmode;
    /** The operand mode (DISCPUMODE). */
    uint8_t         opmode;
    /** Per instruction prefix settings. */
    uint8_t         prefix;
    /* off: 0x070 (112) */
    /** REX prefix value (64 bits only). */
    uint8_t         prefix_rex;
    /** Segment prefix value (DISSELREG). */
    uint8_t         idxSegPrefix;
    /** Last prefix byte (for SSE2 extension tables). */
    uint8_t         lastprefix;
    /** First opcode byte of instruction. */
    uint8_t         opcode;
    /* off: 0x074 (116) */
    /** The size of the prefix bytes. */
    uint8_t         cbPrefix;
    /** The instruction size. */
    uint8_t         opsize;
    uint8_t         abUnused[2];
    /* off: 0x078 (120) */
    /** Return code set by a worker function like the opcode bytes readers. */
    int32_t         rc;
    /** Internal: instruction filter */
    uint32_t        fFilter;
    /* off: 0x080 (128) */
    /** Internal: pointer to disassembly function table */
    PCPFNDISPARSE   pfnDisasmFnTable;
#if ARCH_BITS == 32
    uint32_t        uPtrPadding1;
#endif
    /** Pointer to the current instruction. */
    PCDISOPCODE     pCurInstr;
#if ARCH_BITS == 32
    uint32_t        uPtrPadding2;
#endif
    /* off: 0x090 (144) */
    /** The address of the instruction. */
    RTUINTPTR       uInstrAddr;
    /* off: 0x098 (152) */
    /** Optional read function */
    PFNDISREADBYTES pfnReadBytes;
#if ARCH_BITS == 32
    uint32_t        uPadding3;
#endif
    /* off: 0x0a0 (160) */
    /** The instruction bytes. */
    uint8_t         abInstr[16];
    /* off: 0x0b0 (176) */
    /** User data slots for the read callback.  The first entry is used for the
     *  pvUser argument, the rest are up for grabs.
     * @remarks This must come last so that we can memset everything before this. */
    void           *apvUserData[3];
#if ARCH_BITS == 32
    uint32_t        auPadding4[3];
#endif
} DISCPUSTATE;


/**
 * Opcode descriptor.
 */
typedef struct DISOPCODE
{
#ifndef DIS_CORE_ONLY
    const char  *pszOpcode;
#endif
    uint8_t     idxParse1;
    uint8_t     idxParse2;
    uint8_t     idxParse3;
    uint8_t     uUnused;
    uint16_t    opcode;
    uint16_t    param1;
    uint16_t    param2;
    uint16_t    param3;
    uint32_t    optype;
} DISOPCODE;


DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
                           PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
                                     PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
                             PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
                             PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);

DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr);
DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
                                PDISCPUSTATE pCpu, uint32_t *pcbInstr);
DISDECL(int) DISInstEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
                       PFNDISREADBYTES pfnReadBytes, void *pvUser,
                       PDISCPUSTATE pCpu, uint32_t *pcbInstr);

DISDECL(int)        DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
DISDECL(uint8_t)    DISQuerySegPrefixByte(PDISCPUSTATE pCpu);

DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize);

DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);


/**
 * Try resolve an address into a symbol name.
 *
 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
 *
 * @returns VBox status code.
 * @retval  VINF_SUCCESS on success, pszBuf contains the full symbol name.
 * @retval  VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
 *          content of pszBuf is truncated and zero terminated.
 * @retval  VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
 *
 * @param   pCpu        Pointer to the disassembler CPU state.
 * @param   u32Sel      The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
 *                      DIS_FMT_SEL_GET_REG to access this.
 * @param   uAddress    The segment address.
 * @param   pszBuf      Where to store the symbol name
 * @param   cchBuf      The size of the buffer.
 * @param   poff        If not a perfect match, then this is where the offset from the return
 *                      symbol to the specified address is returned.
 * @param   pvUser      The user argument.
 */
typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
/** Pointer to a FNDISGETSYMBOL(). */
typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;

/**
 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
 */
#define DIS_FMT_SEL_IS_REG(u32Sel)          ( !!((u32Sel) & RT_BIT(31)) )

/**
 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
 * @returns Selector value.
 */
#define DIS_FMT_SEL_GET_VALUE(u32Sel)       ( (RTSEL)(u32Sel) )

/**
 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
 */
#define DIS_FMT_SEL_GET_REG(u32Sel)         ( ((u32Sel) >> 16) & 0xf )

/** @internal */
#define DIS_FMT_SEL_FROM_REG(uReg)          ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
/** @internal */
#define DIS_FMT_SEL_FROM_VALUE(Sel)         ( (Sel) & 0xffff )


/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
 * @{
 */
/** Put the address to the right. */
#define DIS_FMT_FLAGS_ADDR_RIGHT            RT_BIT_32(0)
/** Put the address to the left. */
#define DIS_FMT_FLAGS_ADDR_LEFT             RT_BIT_32(1)
/** Put the address in comments.
 * For some assemblers this implies placing it to the right. */
#define DIS_FMT_FLAGS_ADDR_COMMENT          RT_BIT_32(2)
/** Put the instruction bytes to the right of the disassembly. */
#define DIS_FMT_FLAGS_BYTES_RIGHT           RT_BIT_32(3)
/** Put the instruction bytes to the left of the disassembly. */
#define DIS_FMT_FLAGS_BYTES_LEFT            RT_BIT_32(4)
/** Put the instruction bytes in comments.
 * For some assemblers this implies placing the bytes to the right. */
#define DIS_FMT_FLAGS_BYTES_COMMENT         RT_BIT_32(5)
/** Put the bytes in square brackets. */
#define DIS_FMT_FLAGS_BYTES_BRACKETS        RT_BIT_32(6)
/** Put spaces between the bytes. */
#define DIS_FMT_FLAGS_BYTES_SPACED          RT_BIT_32(7)
/** Display the relative +/- offset of branch instructions that uses relative addresses,
 * and put the target address in parenthesis. */
#define DIS_FMT_FLAGS_RELATIVE_BRANCH       RT_BIT_32(8)
/** Strict assembly. The assembly should, when ever possible, make the
 * assembler reproduce the exact same binary. (Refers to the yasm
 * strict keyword.) */
#define DIS_FMT_FLAGS_STRICT                RT_BIT_32(9)
/** Checks if the given flags are a valid combination. */
#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
    (   !((fFlags) & ~UINT32_C(0x000003ff)) \
     && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT  | DIS_FMT_FLAGS_ADDR_LEFT))  != (DIS_FMT_FLAGS_ADDR_RIGHT  | DIS_FMT_FLAGS_ADDR_LEFT) \
     && (   !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
         || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
     && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
     && (   !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
         || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
    )
/** @} */

DISDECL(size_t) DISFormatYasm(  PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
DISDECL(size_t) DISFormatMasm(  PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
DISDECL(size_t) DISFormatGas(   PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);

/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */

DISDECL(bool)   DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);


RT_C_DECLS_END

#endif