cpum.h revision db36ad422e2702475407b4adb86cd1b55f7ffbab
2N/A * CPUM - CPU Monitor(/ Manager). (VMM) 2N/A * Copyright (C) 2006-2007 Sun Microsystems, Inc. 2N/A * This file is part of VirtualBox Open Source Edition (OSE), as 2N/A * you can redistribute it and/or modify it under the terms of the GNU 2N/A * General Public License (GPL) as published by the Free Software 2N/A * Foundation, in version 2 as it comes in the "COPYING" file of the 2N/A * VirtualBox OSE distribution. VirtualBox OSE is distributed in the 2N/A * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. 2N/A * The contents of this file may alternatively be used under the terms 2N/A * of the Common Development and Distribution License Version 1.0 2N/A * (CDDL) only, as it comes in the "COPYING.CDDL" file of the 2N/A * VirtualBox OSE distribution, in which case the provisions of the 2N/A * CDDL are applicable instead of those of the GPL. 2N/A * You may elect to license modified versions of this file under the 2N/A * terms and conditions of either the GPL or the CDDL or both. 2N/A * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa 2N/A * additional information or have any questions. 2N/A/** @defgroup grp_cpum The CPU Monitor / Manager API * Selector hidden registers. * - Unused in long mode for CS, DS, ES, SS * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address * - 64 bits for TR & LDTR * This is the high 32-bit word of the descriptor entry. * Only the flags, dpl and type are used. */ * The sysenter register set. * This value + 8 is the Ring 0 ss. * This value + 16 is the Ring 3 cs. * This value + 24 is the Ring 3 ss. /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */ RTSEL csPadding[
3];
/* 3 words to force 8 byte alignment for the remainder */ /** Hidden selector registers. /** FPU state. (16-byte alignment) * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the * actual format or convert it (waste of time). */ /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */ RTSEL csPadding[
3];
/* 3 words to force 8 byte alignment for the remainder */ /** Hidden selector registers. * @remarks DR4 and DR5 should not be used since they are aliases for * DR6 and DR7 respectively on both AMD and Intel CPUs. * @remarks DR8-15 are currently not supported by AMD or Intel, so /** Global Descriptor Table register. */ /** Interrupt Descriptor Table register. */ * Only the guest context uses all the members. */ * Only the guest context uses all the members. */ /** The sysenter msr registers. * This member is not used by the hypervisor context. */ /** Hidden selector registers. /*& Padding to align the size on a 64 byte boundrary. */ * Gets the CPUMCTXCORE part of a CPUMCTX. * Selector hidden registers, for version 1.6 saved state. * This is the high 32-bit word of the descriptor entry. * Only the flags, dpl and type are used. */ * CPU context, for version 1.6 saved state. * @remarks PATM uses this, which is why it has to be here. /** FPU state. (16-byte alignment) * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the * actual format or convert it (waste of time). */ /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */ /* Note: no overlap with esp here. */ RTSEL csPadding[
3];
/* 3 words to force 8 byte alignment for the remainder */ /** Hidden selector registers. /* DR8-15 are currently not supported */ /** Global Descriptor Table register. */ /** Interrupt Descriptor Table register. */ * Only the guest context uses all the members. */ * Only the guest context uses all the members. */ /** The sysenter msr registers. * This member is not used by the hypervisor context. */ /** Hidden selector registers. /* padding to get 32byte aligned size */ /** Pointer to the guest MSR state. */ /** Pointer to the const guest MSR state. */ * The register set returned by a CPUID operation. /** Pointer to a CPUID leaf. */ /** Pointer to a const CPUID leaf. */ * CPUID feature to set or clear. /** The APIC feature bit. (Std+Ext) */ /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */ /** The PAE feature bit. (Std+Ext) */ /** The NXE feature bit. (Ext) */ /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */ /** The LONG MODE feature bit. (Ext) */ /** The PAT feature bit. (Std+Ext) */ /** The x2APIC feature bit. (Std) */ /** The RDTSCP feature bit. (Ext) */ /** 32bit hackishness. */ /** 32bit hackishness. */ /** @name Guest Register Getters. /** @name Guest Register Setters. /** @name Misc Guest Predicate Functions. * Tests if the guest is running in real mode or not. * @returns true if in real mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in real mode or not. * @returns true if in real mode, otherwise false. * @param pCtx Current CPU context * Tests if the guest is running in protected or not. * @returns true if in protected mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in paged protected or not. * @returns true if in paged protected mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in paged protected or not. * @returns true if in paged protected mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in long mode or not. * @returns true if in long mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in long mode or not. * @returns true if in long mode, otherwise false. * @param pCtx Current CPU context * Tests if the guest is running in 64 bits mode or not. * @returns true if in 64 bits protected mode, otherwise false. * @param pVM The VM handle. * @param pCtx Current CPU context * Tests if the guest is running in 64 bits mode or not. * @returns true if in 64 bits protected mode, otherwise false. * @param pVM The VM handle. * @param pCtx Current CPU context * Tests if the guest is running in PAE mode or not. * @returns true if in PAE mode, otherwise false. * @param pVM The VM handle. * Tests if the guest is running in PAE mode or not. * @returns true if in PAE mode, otherwise false. * @param pCtx Current CPU context /** @name Hypervisor Register Getters. #
if 0
/* these are not correct. *//** This register is only saved on fatal traps. */ /** This register is only saved on fatal traps. */ /** This register is only saved on fatal traps. */ /** @name Hypervisor Register Setters. * These flags are used to keep track of which important register that * have been changed since last they were reset. The only one allowed /** The usual invalid zero entry. */ /** Protected mode (32-bit). */ /** Long mode (64-bit). */ /** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API /** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API * Assumes a trap stack frame has already been setup on the guest's stack! * @param selCS Code selector of handler * @param pHandler GC virtual address of handler * @param eflags Callee's EFLAGS * @param selSS Stack selector for handler * @param pEsp Stack address for handler * This function does not return! /** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API