0N/A/* BEGIN CSTYLED */
0N/A
1356N/A/*
0N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
1356N/A */
0N/A
0N/A/*
919N/A * Copyright (c) 2007-2008, 2013, Intel Corporation
919N/A * Jesse Barnes <jesse.barnes@intel.com>
919N/A *
919N/A * Permission is hereby granted, free of charge, to any person obtaining a
919N/A * copy of this software and associated documentation files (the "Software"),
919N/A * to deal in the Software without restriction, including without limitation
919N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
919N/A * and/or sell copies of the Software, and to permit persons to whom the
919N/A * Software is furnished to do so, subject to the following conditions:
919N/A *
919N/A * The above copyright notice and this permission notice shall be included in
919N/A * all copies or substantial portions of the Software.
919N/A *
919N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
919N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
919N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
919N/A * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0N/A * OTHER DEALINGS IN THE SOFTWARE.
156N/A */
493N/A#ifndef __DRM_EDID_H__
0N/A#define __DRM_EDID_H__
1356N/A
1356N/A#include "drm.h"
1356N/A#include "drmP.h"
970N/A#define EDID_LENGTH 128
970N/A#define DDC_ADDR 0x50
970N/A
970N/A#define CEA_EXT 0x02
970N/A#define VTB_EXT 0x10
970N/A#define DI_EXT 0x40
970N/A#define LS_EXT 0x50
970N/A#define MI_EXT 0x60
970N/A
970N/A#pragma pack(1)
970N/Astruct est_timings {
970N/A u8 t1;
970N/A u8 t2;
970N/A u8 mfg_rsvd;
970N/A} __attribute__((packed));
970N/A#pragma pack()
970N/A
970N/A/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
970N/A#define EDID_TIMING_ASPECT_SHIFT 6
970N/A#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
970N/A
970N/A/* need to add 60 */
970N/A#define EDID_TIMING_VFREQ_SHIFT 0
970N/A#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
1356N/A
970N/A#pragma pack(1)
0N/Astruct std_timing {
950N/A u8 hsize; /* need to multiply by 8 then add 248 */
0N/A u8 vfreq_aspect;
911N/A} __attribute__((packed));
950N/A#pragma pack()
950N/A
911N/A#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
0N/A#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
493N/A#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
493N/A#define DRM_EDID_PT_STEREO (1 << 5)
0N/A#define DRM_EDID_PT_INTERLACED (1 << 7)
0N/A
156N/A/* If detailed data is pixel timing */
156N/A#pragma pack(1)
0N/Astruct detailed_pixel_timing {
0N/A u8 hactive_lo;
950N/A u8 hblank_lo;
950N/A u8 hactive_hblank_hi;
950N/A u8 vactive_lo;
950N/A u8 vblank_lo;
950N/A u8 vactive_vblank_hi;
950N/A u8 hsync_offset_lo;
1102N/A u8 hsync_pulse_width_lo;
1160N/A u8 vsync_offset_pulse_width_lo;
1160N/A u8 hsync_vsync_offset_pulse_width_hi;
364N/A u8 width_mm_lo;
156N/A u8 height_mm_lo;
156N/A u8 width_height_mm_hi;
0N/A u8 hborder;
591N/A u8 vborder;
947N/A u8 misc;
947N/A} __attribute__((packed));
591N/A#pragma pack()
591N/A
591N/A/* If it's not pixel timing, it'll be one of the below */
947N/A#pragma pack(1)
947N/Astruct detailed_data_string {
947N/A u8 str[13];
947N/A} __attribute__((packed));
947N/A#pragma pack()
947N/A
947N/A#pragma pack(1)
947N/Astruct detailed_data_monitor_range {
947N/A u8 min_vfreq;
947N/A u8 max_vfreq;
947N/A u8 min_hfreq_khz;
947N/A u8 max_hfreq_khz;
947N/A u8 pixel_clock_mhz; /* need to multiply by 10 */
947N/A u8 flags;
947N/A union {
947N/A struct {
0N/A u8 reserved;
1418N/A u8 hfreq_start_khz; /* need to multiply by 2 */
1418N/A u8 c; /* need to divide by 2 */
156N/A __u16 m;
493N/A u8 k;
493N/A u8 j; /* need to divide by 2 */
837N/A } __attribute__((packed)) gtf2;
837N/A struct {
846N/A u8 version;
493N/A u8 data1; /* high 6 bits: extra clock resolution */
156N/A u8 data2; /* plus low 2 of above: max hactive */
493N/A u8 supported_aspects;
493N/A u8 flags; /* preferred aspect and blanking support */
493N/A u8 supported_scalings;
364N/A u8 preferred_refresh;
0N/A } __attribute__((packed)) cvt;
493N/A } formula;
493N/A} __attribute__((packed));
156N/A#pragma pack()
493N/A
493N/A#pragma pack(1)
0N/Astruct detailed_data_wpindex {
1196N/A u8 white_yx_lo; /* Lower 2 bits each */
1196N/A u8 white_x_hi;
1196N/A u8 white_y_hi;
1196N/A u8 gamma; /* need to divide by 100 then add 1 */
1196N/A} __attribute__((packed));
967N/A#pragma pack()
967N/A
967N/A#pragma pack(1)
970N/Astruct detailed_data_color_point {
980N/A u8 windex1;
0N/A u8 wpindex1[3];
980N/A u8 windex2;
339N/A u8 wpindex2[3];
970N/A} __attribute__((packed));
970N/A#pragma pack()
970N/A
970N/A#pragma pack(1)
0N/Astruct cvt_timing {
837N/A u8 code[3];
837N/A} __attribute__((packed));
838N/A#pragma pack()
837N/A
837N/A#pragma pack(1)
967N/Astruct detailed_non_pixel {
967N/A u8 pad1;
967N/A u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
779N/A fb=color point data, fa=standard timing data,
970N/A f9=undefined, f8=mfg. reserved */
838N/A u8 pad2;
591N/A union {
967N/A struct detailed_data_string str;
0N/A struct detailed_data_monitor_range range;
0N/A struct detailed_data_wpindex color;
0N/A struct std_timing timings[5];
0N/A struct cvt_timing cvt[4];
591N/A } data;
0N/A} __attribute__((packed));
339N/A#pragma pack()
339N/A
591N/A#define EDID_DETAIL_EST_TIMINGS 0xf7
493N/A#define EDID_DETAIL_CVT_3BYTE 0xf8
970N/A#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
970N/A#define EDID_DETAIL_STD_MODES 0xfa
970N/A#define EDID_DETAIL_MONITOR_CPDATA 0xfb
970N/A#define EDID_DETAIL_MONITOR_NAME 0xfc
970N/A#define EDID_DETAIL_MONITOR_RANGE 0xfd
970N/A#define EDID_DETAIL_MONITOR_STRING 0xfe
970N/A#define EDID_DETAIL_MONITOR_SERIAL 0xff
970N/A
837N/A#pragma pack(1)
837N/Astruct detailed_timing {
967N/A __u16 pixel_clock; /* need to multiply by 10 KHz */
967N/A union {
967N/A struct detailed_pixel_timing pixel_data;
779N/A struct detailed_non_pixel other_data;
156N/A } data;
156N/A} __attribute__((packed));
967N/A#pragma pack()
591N/A
1183N/A#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
591N/A#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
591N/A#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
591N/A#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
935N/A#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
967N/A#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
967N/A#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
967N/A#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
0N/A#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
#define DRM_EDID_DIGITAL_TYPE_DVI (1)
#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
#define DRM_EDID_DIGITAL_TYPE_DP (5)
#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
/* If digital */
#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
#define DRM_EDID_FEATURE_RGB (0 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
#pragma pack(1)
struct edid {
u8 header[8];
/* Vendor & product info */
u8 mfg_id[2];
u8 prod_code[2];
__u32 serial; /* FIXME: byte order */
u8 mfg_week;
u8 mfg_year;
/* EDID version */
u8 version;
u8 revision;
/* Display info: */
u8 input;
u8 width_cm;
u8 height_cm;
u8 gamma;
u8 features;
/* Color characteristics */
u8 red_green_lo;
u8 black_white_lo;
u8 red_x;
u8 red_y;
u8 green_x;
u8 green_y;
u8 blue_x;
u8 blue_y;
u8 white_x;
u8 white_y;
/* Est. timings and mfg rsvd timings*/
struct est_timings established_timings;
/* Standard timings 1-8*/
struct std_timing standard_timings[8];
/* Detailing timings 1-4 */
struct detailed_timing detailed_timings[4];
/* Number of 128 byte ext. blocks */
u8 extensions;
/* Checksum */
u8 checksum;
} __attribute__((packed));
#pragma pack()
#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
/* define the number of Extension EDID block */
#define DRM_MAX_EDID_EXT_NUM 4
/* Short Audio Descriptor */
struct cea_sad {
u8 format;
u8 channels; /* max number of channels - 1 */
u8 freq;
u8 byte2; /* meaning depends on format */
};
struct drm_encoder;
struct drm_connector;
struct drm_display_mode;
void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
int drm_av_sync_delay(struct drm_connector *connector,
struct drm_display_mode *mode);
struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
#endif /* __DRM_EDID_H__ */