1494N/A/*
1494N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
1494N/A */
1494N/A
1494N/A/*
1494N/A *
1494N/A * Copyright © 1997-2003 by The XFree86 Project, Inc.
1494N/A * Copyright © 2007 Dave Airlie
1494N/A * Copyright (c) 2007-2008, 2013, Intel Corporation
1494N/A * Jesse Barnes <jesse.barnes@intel.com>
1494N/A * Copyright 2005-2006 Luc Verhaegen
1494N/A * Copyright (c) 2001, Andy Ritger aritger@nvidia.com
1494N/A *
1494N/A * Permission is hereby granted, free of charge, to any person obtaining a
1494N/A * copy of this software and associated documentation files (the "Software"),
1494N/A * to deal in the Software without restriction, including without limitation
1494N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1494N/A * and/or sell copies of the Software, and to permit persons to whom the
1494N/A * Software is furnished to do so, subject to the following conditions:
1494N/A *
1494N/A * The above copyright notice and this permission notice shall be included in
1494N/A * all copies or substantial portions of the Software.
1494N/A *
1494N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1494N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1494N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1494N/A * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1494N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1494N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1494N/A * OTHER DEALINGS IN THE SOFTWARE.
1494N/A *
1494N/A * Except as contained in this notice, the name of the copyright holder(s)
1494N/A * and author(s) shall not be used in advertising or otherwise to promote
1494N/A * the sale, use or other dealings in this Software without prior written
1494N/A * authorization from the copyright holder(s) and author(s).
1494N/A */
1494N/A
1494N/A#include "drmP.h"
1494N/A#include "drm.h"
1494N/A#include "drm_crtc.h"
1494N/A#include "drm_linux_list.h"
1494N/A/**
1494N/A * drm_mode_debug_printmodeline - debug print a mode
1494N/A * @dev: DRM device
1494N/A * @mode: mode to print
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Describe @mode using DRM_DEBUG.
1494N/A */
1494N/Avoid drm_mode_debug_printmodeline(const struct drm_display_mode *mode)
1494N/A{
1494N/A DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d "
1494N/A "0x%x 0x%x\n",
1494N/A mode->base.id, mode->name, mode->vrefresh, mode->clock,
1494N/A mode->hdisplay, mode->hsync_start,
1494N/A mode->hsync_end, mode->htotal,
1494N/A mode->vdisplay, mode->vsync_start,
1494N/A mode->vsync_end, mode->vtotal, mode->type, mode->flags);
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_cvt_mode -create a modeline based on CVT algorithm
1494N/A * @dev: DRM device
1494N/A * @hdisplay: hdisplay size
1494N/A * @vdisplay: vdisplay size
1494N/A * @vrefresh : vrefresh rate
1494N/A * @reduced : Whether the GTF calculation is simplified
1494N/A * @interlaced:Whether the interlace is supported
1494N/A *
1494N/A * LOCKING:
1494N/A * none.
1494N/A *
1494N/A * return the modeline based on CVT algorithm
1494N/A *
1494N/A * This function is called to generate the modeline based on CVT algorithm
1494N/A * according to the hdisplay, vdisplay, vrefresh.
1494N/A * It is based from the VESA(TM) Coordinated Video Timing Generator by
1494N/A * Graham Loveridge April 9, 2003 available at
1494N/A * http://www.vesa.org/public/CVT/CVTd6r1.xls
1494N/A *
1494N/A * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
1494N/A * What I have done is to translate it by using integer calculation.
1494N/A */
1494N/A#define HV_FACTOR 1000
1494N/Astruct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
1494N/A int vdisplay, int vrefresh,
1494N/A bool reduced, bool interlaced, bool margins)
1494N/A{
1494N/A /* 1) top/bottom margin size (% of height) - default: 1.8, */
1494N/A#define CVT_MARGIN_PERCENTAGE 18
1494N/A /* 2) character cell horizontal granularity (pixels) - default 8 */
1494N/A#define CVT_H_GRANULARITY 8
1494N/A /* 3) Minimum vertical porch (lines) - default 3 */
1494N/A#define CVT_MIN_V_PORCH 3
1494N/A /* 4) Minimum number of vertical back porch lines - default 6 */
1494N/A#define CVT_MIN_V_BPORCH 6
1494N/A /* Pixel Clock step (kHz) */
1494N/A#define CVT_CLOCK_STEP 250
1494N/A struct drm_display_mode *drm_mode;
1494N/A unsigned int vfieldrate, hperiod;
1494N/A int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
1494N/A int interlace;
1494N/A
1494N/A /* allocate the drm_display_mode structure. If failure, we will
1494N/A * return directly
1494N/A */
1494N/A drm_mode = drm_mode_create(dev);
1494N/A if (!drm_mode)
1494N/A return NULL;
1494N/A
1494N/A /* the CVT default refresh rate is 60Hz */
1494N/A if (!vrefresh)
1494N/A vrefresh = 60;
1494N/A
1494N/A /* the required field fresh rate */
1494N/A if (interlaced)
1494N/A vfieldrate = vrefresh * 2;
1494N/A else
1494N/A vfieldrate = vrefresh;
1494N/A
1494N/A /* horizontal pixels */
1494N/A hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
1494N/A
1494N/A /* determine the left&right borders */
1494N/A hmargin = 0;
1494N/A if (margins) {
1494N/A hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
1494N/A hmargin -= hmargin % CVT_H_GRANULARITY;
1494N/A }
1494N/A /* find the total active pixels */
1494N/A drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
1494N/A
1494N/A /* find the number of lines per field */
1494N/A if (interlaced)
1494N/A vdisplay_rnd = vdisplay / 2;
1494N/A else
1494N/A vdisplay_rnd = vdisplay;
1494N/A
1494N/A /* find the top & bottom borders */
1494N/A vmargin = 0;
1494N/A if (margins)
1494N/A vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
1494N/A
1494N/A drm_mode->vdisplay = vdisplay + 2 * vmargin;
1494N/A
1494N/A /* Interlaced */
1494N/A if (interlaced)
1494N/A interlace = 1;
1494N/A else
1494N/A interlace = 0;
1494N/A
1494N/A /* Determine VSync Width from aspect ratio */
1494N/A if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
1494N/A vsync = 4;
1494N/A else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
1494N/A vsync = 5;
1494N/A else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
1494N/A vsync = 6;
1494N/A else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
1494N/A vsync = 7;
1494N/A else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
1494N/A vsync = 7;
1494N/A else /* custom */
1494N/A vsync = 10;
1494N/A
1494N/A if (!reduced) {
1494N/A /* simplify the GTF calculation */
1494N/A /* 4) Minimum time of vertical sync + back porch interval (µs)
1494N/A * default 550.0
1494N/A */
1494N/A int tmp1, tmp2;
1494N/A#define CVT_MIN_VSYNC_BP 550
1494N/A /* 3) Nominal HSync width (% of line period) - default 8 */
1494N/A#define CVT_HSYNC_PERCENTAGE 8
1494N/A unsigned int hblank_percentage;
1494N/A /* LINTED */
1494N/A int vsyncandback_porch, vback_porch, hblank;
1494N/A
1494N/A /* estimated the horizontal period */
1494N/A tmp1 = HV_FACTOR * 1000000 -
1494N/A CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
1494N/A tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
1494N/A interlace;
1494N/A hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
1494N/A
1494N/A tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
1494N/A /* 9. Find number of lines in sync + backporch */
1494N/A if (tmp1 < (vsync + CVT_MIN_V_PORCH))
1494N/A vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
1494N/A else
1494N/A vsyncandback_porch = tmp1;
1494N/A /* 10. Find number of lines in back porch */
1494N/A vback_porch = vsyncandback_porch - vsync;
1494N/A drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
1494N/A vsyncandback_porch + CVT_MIN_V_PORCH;
1494N/A /* 5) Definition of Horizontal blanking time limitation */
1494N/A /* Gradient (%/kHz) - default 600 */
1494N/A#define CVT_M_FACTOR 600
1494N/A /* Offset (%) - default 40 */
1494N/A#define CVT_C_FACTOR 40
1494N/A /* Blanking time scaling factor - default 128 */
1494N/A#define CVT_K_FACTOR 128
1494N/A /* Scaling factor weighting - default 20 */
1494N/A#define CVT_J_FACTOR 20
1494N/A#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256)
1494N/A#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
1494N/A CVT_J_FACTOR)
1494N/A /* 12. Find ideal blanking duty cycle from formula */
1494N/A hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
1494N/A hperiod / 1000;
1494N/A /* 13. Blanking time */
1494N/A if (hblank_percentage < 20 * HV_FACTOR)
1494N/A hblank_percentage = 20 * HV_FACTOR;
1494N/A hblank = drm_mode->hdisplay * hblank_percentage /
1494N/A (100 * HV_FACTOR - hblank_percentage);
1494N/A hblank -= hblank % (2 * CVT_H_GRANULARITY);
1494N/A /* 14. find the total pixes per line */
1494N/A drm_mode->htotal = drm_mode->hdisplay + hblank;
1494N/A drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
1494N/A drm_mode->hsync_start = drm_mode->hsync_end -
1494N/A (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
1494N/A drm_mode->hsync_start += CVT_H_GRANULARITY -
1494N/A drm_mode->hsync_start % CVT_H_GRANULARITY;
1494N/A /* fill the Vsync values */
1494N/A drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
1494N/A drm_mode->vsync_end = drm_mode->vsync_start + vsync;
1494N/A } else {
1494N/A /* Reduced blanking */
1494N/A /* Minimum vertical blanking interval time (µs)- default 460 */
1494N/A#define CVT_RB_MIN_VBLANK 460
1494N/A /* Fixed number of clocks for horizontal sync */
1494N/A#define CVT_RB_H_SYNC 32
1494N/A /* Fixed number of clocks for horizontal blanking */
1494N/A#define CVT_RB_H_BLANK 160
1494N/A /* Fixed number of lines for vertical front porch - default 3*/
1494N/A#define CVT_RB_VFPORCH 3
1494N/A int vbilines;
1494N/A int tmp1, tmp2;
1494N/A /* 8. Estimate Horizontal period. */
1494N/A tmp1 = HV_FACTOR * 1000000 -
1494N/A CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
1494N/A tmp2 = vdisplay_rnd + 2 * vmargin;
1494N/A hperiod = tmp1 / (tmp2 * vfieldrate);
1494N/A /* 9. Find number of lines in vertical blanking */
1494N/A vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
1494N/A /* 10. Check if vertical blanking is sufficient */
1494N/A if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
1494N/A vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
1494N/A /* 11. Find total number of lines in vertical field */
1494N/A drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
1494N/A /* 12. Find total number of pixels in a line */
1494N/A drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
1494N/A /* Fill in HSync values */
1494N/A drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
1494N/A drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
1494N/A /* Fill in VSync values */
1494N/A drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH;
1494N/A drm_mode->vsync_end = drm_mode->vsync_start + vsync;
1494N/A }
1494N/A /* 15/13. Find pixel clock frequency (kHz for xf86) */
1494N/A drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
1494N/A drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
1494N/A /* 18/16. Find actual vertical frame frequency */
1494N/A /* ignore - just set the mode flag for interlaced */
1494N/A if (interlaced) {
1494N/A drm_mode->vtotal *= 2;
1494N/A drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
1494N/A }
1494N/A /* Fill the mode line name */
1494N/A drm_mode_set_name(drm_mode);
1494N/A if (reduced)
1494N/A drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
1494N/A DRM_MODE_FLAG_NVSYNC);
1494N/A else
1494N/A drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
1494N/A DRM_MODE_FLAG_NHSYNC);
1494N/A
1494N/A return drm_mode;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_gtf_mode - create the modeline based on GTF algorithm
1494N/A *
1494N/A * @dev :drm device
1494N/A * @hdisplay :hdisplay size
1494N/A * @vdisplay :vdisplay size
1494N/A * @vrefresh :vrefresh rate.
1494N/A * @interlaced :whether the interlace is supported
1494N/A * @margins :whether the margin is supported
1494N/A * @GTF_[MCKJ] :extended GTF formula parameters
1494N/A *
1494N/A * LOCKING.
1494N/A * none.
1494N/A *
1494N/A * return the modeline based on GTF algorithm
1494N/A *
1494N/A * GTF feature blocks specify C and J in multiples of 0.5, so we pass them
1494N/A * in here multiplied by two. For a C of 40, pass in 80.
1494N/A */
1494N/Astruct drm_display_mode *
1494N/Adrm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
1494N/A int vrefresh, bool interlaced, int margins,
1494N/A int GTF_M, int GTF_2C, int GTF_K, int GTF_2J)
1494N/A{ /* 1) top/bottom margin size (% of height) - default: 1.8, */
1494N/A#define GTF_MARGIN_PERCENTAGE 18
1494N/A /* 2) character cell horizontal granularity (pixels) - default 8 */
1494N/A#define GTF_CELL_GRAN 8
1494N/A /* 3) Minimum vertical porch (lines) - default 3 */
1494N/A#define GTF_MIN_V_PORCH 1
1494N/A /* width of vsync in lines */
1494N/A#define V_SYNC_RQD 3
1494N/A /* width of hsync as % of total line */
1494N/A#define H_SYNC_PERCENT 8
1494N/A /* min time of vsync + back porch (microsec) */
1494N/A#define MIN_VSYNC_PLUS_BP 550
1494N/A /* C' and M' are part of the Blanking Duty Cycle computation */
1494N/A#define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2)
1494N/A#define GTF_M_PRIME (GTF_K * GTF_M / 256)
1494N/A struct drm_display_mode *drm_mode;
1494N/A unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd;
1494N/A int top_margin, bottom_margin;
1494N/A int interlace;
1494N/A unsigned int hfreq_est;
1494N/A /* LINTED */
1494N/A int vsync_plus_bp, vback_porch;
1494N/A /* LINTED */
1494N/A unsigned int vtotal_lines, vfieldrate_est, hperiod;
1494N/A /* LINTED */
1494N/A unsigned int vfield_rate, vframe_rate;
1494N/A int left_margin, right_margin;
1494N/A unsigned int total_active_pixels, ideal_duty_cycle;
1494N/A unsigned int hblank, total_pixels, pixel_freq;
1494N/A int hsync, hfront_porch, vodd_front_porch_lines;
1494N/A unsigned int tmp1, tmp2;
1494N/A
1494N/A drm_mode = drm_mode_create(dev);
1494N/A if (!drm_mode)
1494N/A return NULL;
1494N/A
1494N/A /* 1. In order to give correct results, the number of horizontal
1494N/A * pixels requested is first processed to ensure that it is divisible
1494N/A * by the character size, by rounding it to the nearest character
1494N/A * cell boundary:
1494N/A */
1494N/A hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
1494N/A hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN;
1494N/A
1494N/A /* 2. If interlace is requested, the number of vertical lines assumed
1494N/A * by the calculation must be halved, as the computation calculates
1494N/A * the number of vertical lines per field.
1494N/A */
1494N/A if (interlaced)
1494N/A vdisplay_rnd = vdisplay / 2;
1494N/A else
1494N/A vdisplay_rnd = vdisplay;
1494N/A
1494N/A /* 3. Find the frame rate required: */
1494N/A if (interlaced)
1494N/A vfieldrate_rqd = vrefresh * 2;
1494N/A else
1494N/A vfieldrate_rqd = vrefresh;
1494N/A
1494N/A /* 4. Find number of lines in Top margin: */
1494N/A top_margin = 0;
1494N/A if (margins)
1494N/A top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
1494N/A 1000;
1494N/A /* 5. Find number of lines in bottom margin: */
1494N/A bottom_margin = top_margin;
1494N/A
1494N/A /* 6. If interlace is required, then set variable interlace: */
1494N/A if (interlaced)
1494N/A interlace = 1;
1494N/A else
1494N/A interlace = 0;
1494N/A
1494N/A /* 7. Estimate the Horizontal frequency */
1494N/A {
1494N/A tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500;
1494N/A tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) *
1494N/A 2 + interlace;
1494N/A hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1;
1494N/A }
1494N/A
1494N/A /* 8. Find the number of lines in V sync + back porch */
1494N/A /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */
1494N/A vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000;
1494N/A vsync_plus_bp = (vsync_plus_bp + 500) / 1000;
1494N/A /* 9. Find the number of lines in V back porch alone: */
1494N/A vback_porch = vsync_plus_bp - V_SYNC_RQD;
1494N/A /* 10. Find the total number of lines in Vertical field period: */
1494N/A vtotal_lines = vdisplay_rnd + top_margin + bottom_margin +
1494N/A vsync_plus_bp + GTF_MIN_V_PORCH;
1494N/A /* 11. Estimate the Vertical field frequency: */
1494N/A vfieldrate_est = hfreq_est / vtotal_lines;
1494N/A /* 12. Find the actual horizontal period: */
1494N/A hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines);
1494N/A
1494N/A /* 13. Find the actual Vertical field frequency: */
1494N/A vfield_rate = hfreq_est / vtotal_lines;
1494N/A /* 14. Find the Vertical frame frequency: */
1494N/A if (interlaced)
1494N/A vframe_rate = vfield_rate / 2;
1494N/A else
1494N/A vframe_rate = vfield_rate;
1494N/A /* 15. Find number of pixels in left margin: */
1494N/A if (margins)
1494N/A left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
1494N/A 1000;
1494N/A else
1494N/A left_margin = 0;
1494N/A
1494N/A /* 16.Find number of pixels in right margin: */
1494N/A right_margin = left_margin;
1494N/A /* 17.Find total number of active pixels in image and left and right */
1494N/A total_active_pixels = hdisplay_rnd + left_margin + right_margin;
1494N/A /* 18.Find the ideal blanking duty cycle from blanking duty cycle */
1494N/A ideal_duty_cycle = GTF_C_PRIME * 1000 -
1494N/A (GTF_M_PRIME * 1000000 / hfreq_est);
1494N/A /* 19.Find the number of pixels in the blanking time to the nearest
1494N/A * double character cell: */
1494N/A hblank = total_active_pixels * ideal_duty_cycle /
1494N/A (100000 - ideal_duty_cycle);
1494N/A hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN);
1494N/A hblank = hblank * 2 * GTF_CELL_GRAN;
1494N/A /* 20.Find total number of pixels: */
1494N/A total_pixels = total_active_pixels + hblank;
1494N/A /* 21.Find pixel clock frequency: */
1494N/A pixel_freq = total_pixels * hfreq_est / 1000;
1494N/A /* Stage 1 computations are now complete; I should really pass
1494N/A * the results to another function and do the Stage 2 computations,
1494N/A * but I only need a few more values so I'll just append the
1494N/A * computations here for now */
1494N/A /* 17. Find the number of pixels in the horizontal sync period: */
1494N/A hsync = H_SYNC_PERCENT * total_pixels / 100;
1494N/A hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
1494N/A hsync = hsync * GTF_CELL_GRAN;
1494N/A /* 18. Find the number of pixels in horizontal front porch period */
1494N/A hfront_porch = hblank / 2 - hsync;
1494N/A /* 36. Find the number of lines in the odd front porch period: */
1494N/A vodd_front_porch_lines = GTF_MIN_V_PORCH ;
1494N/A
1494N/A /* finally, pack the results in the mode struct */
1494N/A drm_mode->hdisplay = hdisplay_rnd;
1494N/A drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
1494N/A drm_mode->hsync_end = drm_mode->hsync_start + hsync;
1494N/A drm_mode->htotal = total_pixels;
1494N/A drm_mode->vdisplay = vdisplay_rnd;
1494N/A drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
1494N/A drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
1494N/A drm_mode->vtotal = vtotal_lines;
1494N/A
1494N/A drm_mode->clock = pixel_freq;
1494N/A
1494N/A if (interlaced) {
1494N/A drm_mode->vtotal *= 2;
1494N/A drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
1494N/A }
1494N/A
1494N/A drm_mode_set_name(drm_mode);
1494N/A if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40)
1494N/A drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC;
1494N/A else
1494N/A drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC;
1494N/A
1494N/A return drm_mode;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_gtf_mode - create the modeline based on GTF algorithm
1494N/A *
1494N/A * @dev :drm device
1494N/A * @hdisplay :hdisplay size
1494N/A * @vdisplay :vdisplay size
1494N/A * @vrefresh :vrefresh rate.
1494N/A * @interlaced :whether the interlace is supported
1494N/A * @margins :whether the margin is supported
1494N/A *
1494N/A * LOCKING.
1494N/A * none.
1494N/A *
1494N/A * return the modeline based on GTF algorithm
1494N/A *
1494N/A * This function is to create the modeline based on the GTF algorithm.
1494N/A * Generalized Timing Formula is derived from:
1494N/A * GTF Spreadsheet by Andy Morrish (1/5/97)
1494N/A * available at http://www.vesa.org
1494N/A *
1494N/A * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c.
1494N/A * What I have done is to translate it by using integer calculation.
1494N/A * I also refer to the function of fb_get_mode in the file of
1494N/A * drivers/video/fbmon.c
1494N/A *
1494N/A * Standard GTF parameters:
1494N/A * M = 600
1494N/A * C = 40
1494N/A * K = 128
1494N/A * J = 20
1494N/A */
1494N/Astruct drm_display_mode *
1494N/Adrm_gtf_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh,
1494N/A bool lace, int margins)
1494N/A{
1494N/A return drm_gtf_mode_complex(dev, hdisplay, vdisplay, vrefresh, lace,
1494N/A margins, 600, 40 * 2, 128, 20 * 2);
1494N/A}
1494N/A
1494N/A#ifdef CONFIG_VIDEOMODE_HELPERS
1494N/Aint drm_display_mode_from_videomode(const struct videomode *vm,
1494N/A struct drm_display_mode *dmode)
1494N/A{
1494N/A dmode->hdisplay = vm->hactive;
1494N/A dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
1494N/A dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
1494N/A dmode->htotal = dmode->hsync_end + vm->hback_porch;
1494N/A
1494N/A dmode->vdisplay = vm->vactive;
1494N/A dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
1494N/A dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
1494N/A dmode->vtotal = dmode->vsync_end + vm->vback_porch;
1494N/A
1494N/A dmode->clock = vm->pixelclock / 1000;
1494N/A
1494N/A dmode->flags = 0;
1494N/A if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
1494N/A dmode->flags |= DRM_MODE_FLAG_PHSYNC;
1494N/A else if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
1494N/A dmode->flags |= DRM_MODE_FLAG_NHSYNC;
1494N/A if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
1494N/A dmode->flags |= DRM_MODE_FLAG_PVSYNC;
1494N/A else if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
1494N/A dmode->flags |= DRM_MODE_FLAG_NVSYNC;
1494N/A if (vm->flags & DISPLAY_FLAGS_INTERLACED)
1494N/A dmode->flags |= DRM_MODE_FLAG_INTERLACE;
1494N/A if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
1494N/A dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
1494N/A if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
1494N/A dmode->flags |= DRM_MODE_FLAG_DBLCLK;
1494N/A drm_mode_set_name(dmode);
1494N/A
1494N/A return 0;
1494N/A}
1494N/A
1494N/A#ifdef CONFIG_OF
1494N/A/**
1494N/A * of_get_drm_display_mode - get a drm_display_mode from devicetree
1494N/A * @np: device_node with the timing specification
1494N/A * @dmode: will be set to the return value
1494N/A * @index: index into the list of display timings in devicetree
1494N/A *
1494N/A * This function is expensive and should only be used, if only one mode is to be
1494N/A * read from DT. To get multiple modes start with of_get_display_timings and
1494N/A * work with that instead.
1494N/A */
1494N/Aint of_get_drm_display_mode(struct device_node *np,
1494N/A struct drm_display_mode *dmode, int index)
1494N/A{
1494N/A struct videomode vm;
1494N/A int ret;
1494N/A
1494N/A ret = of_get_videomode(np, &vm, index);
1494N/A if (ret)
1494N/A return ret;
1494N/A
1494N/A drm_display_mode_from_videomode(&vm, dmode);
1494N/A
1494N/A pr_debug("%s: got %dx%d display mode from %s\n",
1494N/A of_node_full_name(np), vm.hactive, vm.vactive, np->name);
1494N/A drm_mode_debug_printmodeline(dmode);
1494N/A
1494N/A return 0;
1494N/A}
1494N/A#endif /* CONFIG_OF */
1494N/A#endif /* CONFIG_VIDEOMODE_HELPERS */
1494N/A
1494N/A/**
1494N/A * drm_mode_set_name - set the name on a mode
1494N/A * @mode: name will be set in this mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Set the name of @mode to a standard format.
1494N/A */
1494N/Avoid drm_mode_set_name(struct drm_display_mode *mode)
1494N/A{
1494N/A bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1494N/A
1494N/A (void) snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s",
1494N/A mode->hdisplay, mode->vdisplay,
1494N/A interlaced ? "i" : "");
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_list_concat - move modes from one list to another
1494N/A * @head: source list
1494N/A * @new: dst list
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must ensure both lists are locked.
1494N/A *
1494N/A * Move all the modes from @head to @new.
1494N/A */
1494N/Avoid drm_mode_list_concat(struct list_head *head, struct list_head *new)
1494N/A{
1494N/A
1494N/A struct list_head *entry, *tmp;
1494N/A
1494N/A list_for_each_safe(entry, tmp, head) {
1494N/A list_move_tail(entry, new, (caddr_t)entry);
1494N/A }
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_width - get the width of a mode
1494N/A * @mode: mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Return @mode's width (hdisplay) value.
1494N/A *
1494N/A * FIXME: is this needed?
1494N/A *
1494N/A * RETURNS:
1494N/A * @mode->hdisplay
1494N/A */
1494N/Aint drm_mode_width(const struct drm_display_mode *mode)
1494N/A{
1494N/A return mode->hdisplay;
1494N/A
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_height - get the height of a mode
1494N/A * @mode: mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Return @mode's height (vdisplay) value.
1494N/A *
1494N/A * FIXME: is this needed?
1494N/A *
1494N/A * RETURNS:
1494N/A * @mode->vdisplay
1494N/A */
1494N/Aint drm_mode_height(const struct drm_display_mode *mode)
1494N/A{
1494N/A return mode->vdisplay;
1494N/A}
1494N/A
1494N/A/** drm_mode_hsync - get the hsync of a mode
1494N/A * @mode: mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Return @modes's hsync rate in kHz, rounded to the nearest int.
1494N/A */
1494N/Aint drm_mode_hsync(const struct drm_display_mode *mode)
1494N/A{
1494N/A unsigned int calc_val;
1494N/A
1494N/A if (mode->hsync)
1494N/A return mode->hsync;
1494N/A
1494N/A if (mode->htotal < 0)
1494N/A return 0;
1494N/A
1494N/A calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
1494N/A calc_val += 500; /* round to 1000Hz */
1494N/A calc_val /= 1000; /* truncate to kHz */
1494N/A
1494N/A return calc_val;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_vrefresh - get the vrefresh of a mode
1494N/A * @mode: mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Return @mode's vrefresh rate in Hz or calculate it if necessary.
1494N/A *
1494N/A * FIXME: why is this needed? shouldn't vrefresh be set already?
1494N/A *
1494N/A * RETURNS:
1494N/A * Vertical refresh rate. It will be the result of actual value plus 0.5.
1494N/A * If it is 70.288, it will return 70Hz.
1494N/A * If it is 59.6, it will return 60Hz.
1494N/A */
1494N/Aint drm_mode_vrefresh(const struct drm_display_mode *mode)
1494N/A{
1494N/A int refresh = 0;
1494N/A unsigned int calc_val;
1494N/A
1494N/A if (mode->vrefresh > 0)
1494N/A refresh = mode->vrefresh;
1494N/A else if (mode->htotal > 0 && mode->vtotal > 0) {
1494N/A int vtotal;
1494N/A vtotal = mode->vtotal;
1494N/A /* work out vrefresh the value will be x1000 */
1494N/A calc_val = (mode->clock * 1000);
1494N/A calc_val /= mode->htotal;
1494N/A refresh = (calc_val + vtotal / 2) / vtotal;
1494N/A
1494N/A if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1494N/A refresh *= 2;
1494N/A if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1494N/A refresh /= 2;
1494N/A if (mode->vscan > 1)
1494N/A refresh /= mode->vscan;
1494N/A }
1494N/A return refresh;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_set_crtcinfo - set CRTC modesetting parameters
1494N/A * @p: mode
1494N/A * @adjust_flags: unused? (FIXME)
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Setup the CRTC modesetting parameters for @p, adjusting if necessary.
1494N/A */
1494N/Avoid drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
1494N/A{
1494N/A if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
1494N/A return;
1494N/A
1494N/A p->crtc_hdisplay = p->hdisplay;
1494N/A p->crtc_hsync_start = p->hsync_start;
1494N/A p->crtc_hsync_end = p->hsync_end;
1494N/A p->crtc_htotal = p->htotal;
1494N/A p->crtc_hskew = p->hskew;
1494N/A p->crtc_vdisplay = p->vdisplay;
1494N/A p->crtc_vsync_start = p->vsync_start;
1494N/A p->crtc_vsync_end = p->vsync_end;
1494N/A p->crtc_vtotal = p->vtotal;
1494N/A
1494N/A if (p->flags & DRM_MODE_FLAG_INTERLACE) {
1494N/A if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
1494N/A p->crtc_vdisplay /= 2;
1494N/A p->crtc_vsync_start /= 2;
1494N/A p->crtc_vsync_end /= 2;
1494N/A p->crtc_vtotal /= 2;
1494N/A }
1494N/A }
1494N/A
1494N/A if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
1494N/A p->crtc_vdisplay *= 2;
1494N/A p->crtc_vsync_start *= 2;
1494N/A p->crtc_vsync_end *= 2;
1494N/A p->crtc_vtotal *= 2;
1494N/A }
1494N/A
1494N/A if (p->vscan > 1) {
1494N/A p->crtc_vdisplay *= p->vscan;
1494N/A p->crtc_vsync_start *= p->vscan;
1494N/A p->crtc_vsync_end *= p->vscan;
1494N/A p->crtc_vtotal *= p->vscan;
1494N/A }
1494N/A
1494N/A p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
1494N/A p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
1494N/A p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
1494N/A p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
1494N/A}
1494N/A
1494N/A
1494N/A/**
1494N/A * drm_mode_copy - copy the mode
1494N/A * @dst: mode to overwrite
1494N/A * @src: mode to copy
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Copy an existing mode into another mode, preserving the object id
1494N/A * of the destination mode.
1494N/A */
1494N/Avoid drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src)
1494N/A{
1494N/A int id = dst->base.id;
1494N/A struct list_head head = dst->head;
1494N/A
1494N/A *dst = *src;
1494N/A dst->base.id = id;
1494N/A dst->head = head;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_duplicate - allocate and duplicate an existing mode
1494N/A * @m: mode to duplicate
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Just allocate a new mode, copy the existing mode into it, and return
1494N/A * a pointer to it. Used to create new instances of established modes.
1494N/A */
1494N/Astruct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
1494N/A const struct drm_display_mode *mode)
1494N/A{
1494N/A struct drm_display_mode *nmode;
1494N/A
1494N/A nmode = drm_mode_create(dev);
1494N/A if (!nmode)
1494N/A return NULL;
1494N/A
1494N/A drm_mode_copy(nmode, mode);
1494N/A
1494N/A return nmode;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_equal - test modes for equality
1494N/A * @mode1: first mode
1494N/A * @mode2: second mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Check to see if @mode1 and @mode2 are equivalent.
1494N/A *
1494N/A * RETURNS:
1494N/A * True if the modes are equal, false otherwise.
1494N/A */
1494N/Abool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
1494N/A{
1494N/A /* do clock check convert to PICOS so fb modes get matched
1494N/A * the same */
1494N/A if (mode1->clock && mode2->clock) {
1494N/A if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock))
1494N/A return false;
1494N/A } else if (mode1->clock != mode2->clock)
1494N/A return false;
1494N/A
1494N/A return drm_mode_equal_no_clocks(mode1, mode2);
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_equal_no_clocks - test modes for equality
1494N/A * @mode1: first mode
1494N/A * @mode2: second mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Check to see if @mode1 and @mode2 are equivalent, but
1494N/A * don't check the pixel clocks.
1494N/A *
1494N/A * RETURNS:
1494N/A * True if the modes are equal, false otherwise.
1494N/A */
1494N/Abool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
1494N/A{
1494N/A if (mode1->hdisplay == mode2->hdisplay &&
1494N/A mode1->hsync_start == mode2->hsync_start &&
1494N/A mode1->hsync_end == mode2->hsync_end &&
1494N/A mode1->htotal == mode2->htotal &&
1494N/A mode1->hskew == mode2->hskew &&
1494N/A mode1->vdisplay == mode2->vdisplay &&
1494N/A mode1->vsync_start == mode2->vsync_start &&
1494N/A mode1->vsync_end == mode2->vsync_end &&
1494N/A mode1->vtotal == mode2->vtotal &&
1494N/A mode1->vscan == mode2->vscan &&
1494N/A mode1->flags == mode2->flags)
1494N/A return true;
1494N/A
1494N/A return false;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_validate_size - make sure modes adhere to size constraints
1494N/A * @dev: DRM device
1494N/A * @mode_list: list of modes to check
1494N/A * @maxX: maximum width
1494N/A * @maxY: maximum height
1494N/A * @maxPitch: max pitch
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must hold a lock protecting @mode_list.
1494N/A *
1494N/A * The DRM device (@dev) has size and pitch limits. Here we validate the
1494N/A * modes we probed for @dev against those limits and set their status as
1494N/A * necessary.
1494N/A */
1494N/A/* LINTED */
1494N/Avoid drm_mode_validate_size(struct drm_device *dev,
1494N/A struct list_head *mode_list,
1494N/A int maxX, int maxY, int maxPitch)
1494N/A{
1494N/A struct drm_display_mode *mode;
1494N/A
1494N/A list_for_each_entry(mode, struct drm_display_mode, mode_list, head) {
1494N/A if (maxPitch > 0 && mode->hdisplay > maxPitch)
1494N/A mode->status = MODE_BAD_WIDTH;
1494N/A
1494N/A if (maxX > 0 && mode->hdisplay > maxX)
1494N/A mode->status = MODE_VIRTUAL_X;
1494N/A
1494N/A if (maxY > 0 && mode->vdisplay > maxY)
1494N/A mode->status = MODE_VIRTUAL_Y;
1494N/A }
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_validate_clocks - validate modes against clock limits
1494N/A * @dev: DRM device
1494N/A * @mode_list: list of modes to check
1494N/A * @min: minimum clock rate array
1494N/A * @max: maximum clock rate array
1494N/A * @n_ranges: number of clock ranges (size of arrays)
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must hold a lock protecting @mode_list.
1494N/A *
1494N/A * Some code may need to check a mode list against the clock limits of the
1494N/A * device in question. This function walks the mode list, testing to make
1494N/A * sure each mode falls within a given range (defined by @min and @max
1494N/A * arrays) and sets @mode->status as needed.
1494N/A */
1494N/A/* LINTED */
1494N/Avoid drm_mode_validate_clocks(struct drm_device *dev,
1494N/A struct list_head *mode_list,
1494N/A int *min, int *max, int n_ranges)
1494N/A{
1494N/A struct drm_display_mode *mode;
1494N/A int i;
1494N/A
1494N/A list_for_each_entry(mode, struct drm_display_mode, mode_list, head) {
1494N/A bool good = false;
1494N/A for (i = 0; i < n_ranges; i++) {
1494N/A if (mode->clock >= min[i] && mode->clock <= max[i]) {
1494N/A good = true;
1494N/A break;
1494N/A }
1494N/A }
1494N/A if (!good)
1494N/A mode->status = MODE_CLOCK_RANGE;
1494N/A }
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_prune_invalid - remove invalid modes from mode list
1494N/A * @dev: DRM device
1494N/A * @mode_list: list of modes to check
1494N/A * @verbose: be verbose about it
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must hold a lock protecting @mode_list.
1494N/A *
1494N/A * Once mode list generation is complete, a caller can use this routine to
1494N/A * remove invalid modes from a mode list. If any of the modes have a
1494N/A * status other than %MODE_OK, they are removed from @mode_list and freed.
1494N/A */
1494N/Avoid drm_mode_prune_invalid(struct drm_device *dev,
1494N/A struct list_head *mode_list, bool verbose)
1494N/A{
1494N/A struct drm_display_mode *mode, *t;
1494N/A
1494N/A list_for_each_entry_safe(mode, t, struct drm_display_mode, mode_list, head) {
1494N/A if (mode->status != MODE_OK) {
1494N/A list_del(&mode->head);
1494N/A if (verbose) {
1494N/A drm_mode_debug_printmodeline(mode);
1494N/A DRM_DEBUG_KMS("Not using %s mode %d\n",
1494N/A mode->name, mode->status);
1494N/A }
1494N/A drm_mode_destroy(dev, mode);
1494N/A }
1494N/A }
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_compare - compare modes for favorability
1494N/A * @lh_a: list_head for first mode
1494N/A * @lh_b: list_head for second mode
1494N/A *
1494N/A * LOCKING:
1494N/A * None.
1494N/A *
1494N/A * Compare two modes, given by @lh_a and @lh_b, returning a value indicating
1494N/A * which is better.
1494N/A *
1494N/A * RETURNS:
1494N/A * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
1494N/A * positive if @lh_b is better than @lh_a.
1494N/A */
1494N/Astatic int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
1494N/A{
1494N/A struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
1494N/A struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
1494N/A int diff;
1494N/A
1494N/A diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) -
1494N/A ((a->type & DRM_MODE_TYPE_PREFERRED) != 0);
1494N/A if (diff)
1494N/A return diff;
1494N/A diff = b->hdisplay * b->vdisplay - a->hdisplay * a->vdisplay;
1494N/A if (diff)
1494N/A return diff;
1494N/A
1494N/A diff = b->vrefresh - a->vrefresh;
1494N/A if (diff)
1494N/A return diff;
1494N/A
1494N/A diff = b->clock - a->clock;
1494N/A return diff;
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_sort - sort mode list
1494N/A * @mode_list: list to sort
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must hold a lock protecting @mode_list.
1494N/A *
1494N/A * Sort @mode_list by favorability, putting good modes first.
1494N/A */
1494N/Avoid drm_mode_sort(struct list_head *mode_list)
1494N/A{
1494N/A struct list_head *cur, *end;
1494N/A struct list_head *list, *temp;
1494N/A int ordered = 1;
1494N/A
1494N/A if (list_empty(mode_list))
1494N/A return;
1494N/A
1494N/A /* Pre-check the mode order
1494N/A * In most cases, the modes is ordered.
1494N/A */
1494N/A for (list = mode_list->next, temp = list->next;
1494N/A temp != mode_list;
1494N/A list = temp, temp = temp->next) {
1494N/A if (drm_mode_compare(list, temp) > 0){
1494N/A ordered = 0;
1494N/A break;
1494N/A }
1494N/A }
1494N/A
1494N/A if (ordered)
1494N/A return;
1494N/A
1494N/A end = mode_list->next;
1494N/A cur = end->next;
1494N/A while (cur != mode_list) {
1494N/A list_for_each_safe(list, temp, mode_list){
1494N/A if (drm_mode_compare(list, cur) > 0) {
1494N/A //insert
1494N/A struct list_head *p_node = list->prev;
1494N/A list_del(cur);
1494N/A p_node->next = cur;
1494N/A list->prev = cur;
1494N/A cur->next = list;
1494N/A cur->prev = p_node;
1494N/A
1494N/A cur = end->next;
1494N/A break;
1494N/A }
1494N/A if (list == end) {
1494N/A end = cur;
1494N/A cur = end->next;
1494N/A break;
1494N/A }
1494N/A }
1494N/A }
1494N/A}
1494N/A
1494N/A/**
1494N/A * drm_mode_connector_list_update - update the mode list for the connector
1494N/A * @connector: the connector to update
1494N/A *
1494N/A * LOCKING:
1494N/A * Caller must hold a lock protecting @mode_list.
1494N/A *
1494N/A * This moves the modes from the @connector probed_modes list
1494N/A * to the actual mode list. It compares the probed mode against the current
1494N/A * list and only adds different modes. All modes unverified after this point
1494N/A * will be removed by the prune invalid modes.
1494N/A */
1494N/Avoid drm_mode_connector_list_update(struct drm_connector *connector)
1494N/A{
1494N/A struct drm_display_mode *mode;
1494N/A struct drm_display_mode *pmode, *pt;
1494N/A int found_it;
1494N/A
1494N/A list_for_each_entry_safe(pmode, pt, struct drm_display_mode,
1494N/A &connector->probed_modes,
1494N/A head) {
1494N/A found_it = 0;
1494N/A /* go through current modes checking for the new probed mode */
1494N/A list_for_each_entry(mode, struct drm_display_mode, &connector->modes, head) {
1494N/A if (drm_mode_equal(pmode, mode)) {
1494N/A found_it = 1;
1494N/A /* if equal delete the probed mode */
1494N/A mode->status = pmode->status;
1494N/A /* Merge type bits together */
1494N/A mode->type |= pmode->type;
1494N/A list_del(&pmode->head);
1494N/A drm_mode_destroy(connector->dev, pmode);
1494N/A break;
1494N/A }
1494N/A }
1494N/A
1494N/A if (!found_it) {
1494N/A list_move_tail(&pmode->head, &connector->modes, (caddr_t)pmode);
1494N/A }
1494N/A }
1494N/A}
1494N/Astruct drm_display_mode *
1494N/Adrm_mode_create_from_cmdline_mode(struct drm_device *dev,
1494N/A struct drm_cmdline_mode *cmd)
1494N/A{
1494N/A struct drm_display_mode *mode;
1494N/A
1494N/A if (cmd->cvt)
1494N/A mode = drm_cvt_mode(dev,
1494N/A cmd->xres, cmd->yres,
1494N/A cmd->refresh_specified ? cmd->refresh : 60,
1494N/A cmd->rb, cmd->interlace,
1494N/A cmd->margins);
1494N/A else
1494N/A mode = drm_gtf_mode(dev,
1494N/A cmd->xres, cmd->yres,
1494N/A cmd->refresh_specified ? cmd->refresh : 60,
1494N/A cmd->interlace,
1494N/A cmd->margins);
1494N/A if (!mode)
1494N/A return NULL;
1494N/A
1494N/A drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
1494N/A return mode;
1494N/A}