1494N/A/*
1494N/A * Copyright (c) 2013 Intel Corporation. All rights reserved.
1494N/A */
1494N/A
1494N/A/*
1494N/A * Copyright © 2009 Keith Packard
1494N/A *
1494N/A * Permission to use, copy, modify, distribute, and sell this software and its
1494N/A * documentation for any purpose is hereby granted without fee, provided that
1494N/A * the above copyright notice appear in all copies and that both that copyright
1494N/A * notice and this permission notice appear in supporting documentation, and
1494N/A * that the name of the copyright holders not be used in advertising or
1494N/A * publicity pertaining to distribution of the software without specific,
1494N/A * written prior permission. The copyright holders make no representations
1494N/A * about the suitability of this software for any purpose. It is provided "as
1494N/A * is" without express or implied warranty.
1494N/A *
1494N/A * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1494N/A * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1494N/A * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1494N/A * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1494N/A * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1494N/A * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
1494N/A * OF THIS SOFTWARE.
1494N/A */
1494N/A
1494N/A#include "drm_dp_helper.h"
1494N/A#include "drmP.h"
1494N/A
1494N/A
1494N/A/* Helpers for DP link training */
1494N/Astatic u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
1494N/A{
1494N/A return link_status[r - DP_LANE0_1_STATUS];
1494N/A}
1494N/A
1494N/Astatic u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
1494N/A int lane)
1494N/A{
1494N/A int i = DP_LANE0_1_STATUS + (lane >> 1);
1494N/A int s = (lane & 1) * 4;
1494N/A u8 l = dp_link_status(link_status, i);
1494N/A return (l >> s) & 0xf;
1494N/A}
1494N/A
1494N/Abool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
1494N/A int lane_count)
1494N/A{
1494N/A u8 lane_align;
1494N/A u8 lane_status;
1494N/A int lane;
1494N/A
1494N/A lane_align = dp_link_status(link_status,
1494N/A DP_LANE_ALIGN_STATUS_UPDATED);
1494N/A if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1494N/A return false;
1494N/A for (lane = 0; lane < lane_count; lane++) {
1494N/A lane_status = dp_get_lane_status(link_status, lane);
1494N/A if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
1494N/A return false;
1494N/A }
1494N/A return true;
1494N/A}
1494N/A
1494N/Abool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
1494N/A int lane_count)
1494N/A{
1494N/A int lane;
1494N/A u8 lane_status;
1494N/A
1494N/A for (lane = 0; lane < lane_count; lane++) {
1494N/A lane_status = dp_get_lane_status(link_status, lane);
1494N/A if ((lane_status & DP_LANE_CR_DONE) == 0)
1494N/A return false;
1494N/A }
1494N/A return true;
1494N/A}
1494N/A
1494N/Au8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
1494N/A int lane)
1494N/A{
1494N/A int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1494N/A int s = ((lane & 1) ?
1494N/A DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1494N/A DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1494N/A u8 l = dp_link_status(link_status, i);
1494N/A
1494N/A return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1494N/A}
1494N/A
1494N/Au8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
1494N/A int lane)
1494N/A{
1494N/A int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1494N/A int s = ((lane & 1) ?
1494N/A DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1494N/A DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1494N/A u8 l = dp_link_status(link_status, i);
1494N/A
1494N/A return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1494N/A}
1494N/A
1494N/Avoid drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
1494N/A if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
1494N/A udelay(100);
1494N/A else
1494N/A mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
1494N/A}
1494N/A
1494N/Avoid drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
1494N/A if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
1494N/A udelay(400);
1494N/A else
1494N/A mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
1494N/A}
1494N/A
1494N/Au8 drm_dp_link_rate_to_bw_code(int link_rate)
1494N/A{
1494N/A switch (link_rate) {
1494N/A case 162000:
1494N/A default:
1494N/A return DP_LINK_BW_1_62;
1494N/A case 270000:
1494N/A return DP_LINK_BW_2_7;
1494N/A case 540000:
1494N/A return DP_LINK_BW_5_4;
1494N/A }
1494N/A}
1494N/A
1494N/Aint drm_dp_bw_code_to_link_rate(u8 link_bw)
1494N/A{
1494N/A switch (link_bw) {
1494N/A case DP_LINK_BW_1_62:
1494N/A default:
1494N/A return 162000;
1494N/A case DP_LINK_BW_2_7:
1494N/A return 270000;
1494N/A case DP_LINK_BW_5_4:
1494N/A return 540000;
1494N/A }
1494N/A}
1494N/A
1494N/Aint
1494N/Adrm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
1494N/A{
1494N/A return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1494N/A}