1450N/A/*
1450N/A * Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright (c) 2007-2008, 2013, Intel Corporation
1450N/A * Jesse Barnes <jesse.barnes@intel.com>
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice shall be included in
1450N/A * all copies or substantial portions of the Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1450N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1450N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1450N/A * OTHER DEALINGS IN THE SOFTWARE.
1450N/A */
1450N/A#ifndef __DRM_EDID_H__
1450N/A#define __DRM_EDID_H__
1450N/A
1450N/A#include "drm.h"
1450N/A#include "drmP.h"
1450N/A#define EDID_LENGTH 128
1450N/A#define DDC_ADDR 0x50
1450N/A
1450N/A#define CEA_EXT 0x02
1450N/A#define VTB_EXT 0x10
1450N/A#define DI_EXT 0x40
1450N/A#define LS_EXT 0x50
1450N/A#define MI_EXT 0x60
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct est_timings {
1450N/A u8 t1;
1450N/A u8 t2;
1450N/A u8 mfg_rsvd;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
1450N/A#define EDID_TIMING_ASPECT_SHIFT 6
1450N/A#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
1450N/A
1450N/A/* need to add 60 */
1450N/A#define EDID_TIMING_VFREQ_SHIFT 0
1450N/A#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct std_timing {
1450N/A u8 hsize; /* need to multiply by 8 then add 248 */
1450N/A u8 vfreq_aspect;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
1450N/A#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
1450N/A#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
1450N/A#define DRM_EDID_PT_STEREO (1 << 5)
1450N/A#define DRM_EDID_PT_INTERLACED (1 << 7)
1450N/A
1450N/A/* If detailed data is pixel timing */
1450N/A#pragma pack(1)
1450N/Astruct detailed_pixel_timing {
1450N/A u8 hactive_lo;
1450N/A u8 hblank_lo;
1450N/A u8 hactive_hblank_hi;
1450N/A u8 vactive_lo;
1450N/A u8 vblank_lo;
1450N/A u8 vactive_vblank_hi;
1450N/A u8 hsync_offset_lo;
1450N/A u8 hsync_pulse_width_lo;
1450N/A u8 vsync_offset_pulse_width_lo;
1450N/A u8 hsync_vsync_offset_pulse_width_hi;
1450N/A u8 width_mm_lo;
1450N/A u8 height_mm_lo;
1450N/A u8 width_height_mm_hi;
1450N/A u8 hborder;
1450N/A u8 vborder;
1450N/A u8 misc;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A/* If it's not pixel timing, it'll be one of the below */
1450N/A#pragma pack(1)
1450N/Astruct detailed_data_string {
1450N/A u8 str[13];
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct detailed_data_monitor_range {
1450N/A u8 min_vfreq;
1450N/A u8 max_vfreq;
1450N/A u8 min_hfreq_khz;
1450N/A u8 max_hfreq_khz;
1450N/A u8 pixel_clock_mhz; /* need to multiply by 10 */
1450N/A u8 flags;
1450N/A union {
1450N/A struct {
1450N/A u8 reserved;
1450N/A u8 hfreq_start_khz; /* need to multiply by 2 */
1450N/A u8 c; /* need to divide by 2 */
1450N/A __u16 m;
1450N/A u8 k;
1450N/A u8 j; /* need to divide by 2 */
1450N/A } __attribute__((packed)) gtf2;
1450N/A struct {
1450N/A u8 version;
1450N/A u8 data1; /* high 6 bits: extra clock resolution */
1450N/A u8 data2; /* plus low 2 of above: max hactive */
1450N/A u8 supported_aspects;
1450N/A u8 flags; /* preferred aspect and blanking support */
1450N/A u8 supported_scalings;
1450N/A u8 preferred_refresh;
1450N/A } __attribute__((packed)) cvt;
1450N/A } formula;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct detailed_data_wpindex {
1450N/A u8 white_yx_lo; /* Lower 2 bits each */
1450N/A u8 white_x_hi;
1450N/A u8 white_y_hi;
1450N/A u8 gamma; /* need to divide by 100 then add 1 */
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct detailed_data_color_point {
1450N/A u8 windex1;
1450N/A u8 wpindex1[3];
1450N/A u8 windex2;
1450N/A u8 wpindex2[3];
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct cvt_timing {
1450N/A u8 code[3];
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct detailed_non_pixel {
1450N/A u8 pad1;
1450N/A u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
1450N/A fb=color point data, fa=standard timing data,
1450N/A f9=undefined, f8=mfg. reserved */
1450N/A u8 pad2;
1450N/A union {
1450N/A struct detailed_data_string str;
1450N/A struct detailed_data_monitor_range range;
1450N/A struct detailed_data_wpindex color;
1450N/A struct std_timing timings[5];
1450N/A struct cvt_timing cvt[4];
1450N/A } data;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#define EDID_DETAIL_EST_TIMINGS 0xf7
1450N/A#define EDID_DETAIL_CVT_3BYTE 0xf8
1450N/A#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
1450N/A#define EDID_DETAIL_STD_MODES 0xfa
1450N/A#define EDID_DETAIL_MONITOR_CPDATA 0xfb
1450N/A#define EDID_DETAIL_MONITOR_NAME 0xfc
1450N/A#define EDID_DETAIL_MONITOR_RANGE 0xfd
1450N/A#define EDID_DETAIL_MONITOR_STRING 0xfe
1450N/A#define EDID_DETAIL_MONITOR_SERIAL 0xff
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct detailed_timing {
1450N/A __u16 pixel_clock; /* need to multiply by 10 KHz */
1450N/A union {
1450N/A struct detailed_pixel_timing pixel_data;
1450N/A struct detailed_non_pixel other_data;
1450N/A } data;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
1450N/A#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
1450N/A#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
1450N/A#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
1450N/A#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
1450N/A#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
1450N/A#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
1450N/A#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
1450N/A#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
1450N/A#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
1450N/A#define DRM_EDID_DIGITAL_TYPE_DVI (1)
1450N/A#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
1450N/A#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
1450N/A#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
1450N/A#define DRM_EDID_DIGITAL_TYPE_DP (5)
1450N/A
1450N/A#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
1450N/A#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
1450N/A#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
1450N/A#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
1450N/A/* If digital */
1450N/A#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
1450N/A#define DRM_EDID_FEATURE_RGB (0 << 3)
1450N/A#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
1450N/A#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
1450N/A#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
1450N/A
1450N/A#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
1450N/A#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
1450N/A#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
1450N/A
1450N/A#pragma pack(1)
1450N/Astruct edid {
1450N/A u8 header[8];
1450N/A /* Vendor & product info */
1450N/A u8 mfg_id[2];
1450N/A u8 prod_code[2];
1450N/A __u32 serial; /* FIXME: byte order */
1450N/A u8 mfg_week;
1450N/A u8 mfg_year;
1450N/A /* EDID version */
1450N/A u8 version;
1450N/A u8 revision;
1450N/A /* Display info: */
1450N/A u8 input;
1450N/A u8 width_cm;
1450N/A u8 height_cm;
1450N/A u8 gamma;
1450N/A u8 features;
1450N/A /* Color characteristics */
1450N/A u8 red_green_lo;
1450N/A u8 black_white_lo;
1450N/A u8 red_x;
1450N/A u8 red_y;
1450N/A u8 green_x;
1450N/A u8 green_y;
1450N/A u8 blue_x;
1450N/A u8 blue_y;
1450N/A u8 white_x;
1450N/A u8 white_y;
1450N/A /* Est. timings and mfg rsvd timings*/
1450N/A struct est_timings established_timings;
1450N/A /* Standard timings 1-8*/
1450N/A struct std_timing standard_timings[8];
1450N/A /* Detailing timings 1-4 */
1450N/A struct detailed_timing detailed_timings[4];
1450N/A /* Number of 128 byte ext. blocks */
1450N/A u8 extensions;
1450N/A /* Checksum */
1450N/A u8 checksum;
1450N/A} __attribute__((packed));
1450N/A#pragma pack()
1450N/A
1450N/A#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
1450N/A
1450N/A/* define the number of Extension EDID block */
1450N/A#define DRM_MAX_EDID_EXT_NUM 4
1450N/A
1450N/A/* Short Audio Descriptor */
1450N/Astruct cea_sad {
1450N/A u8 format;
1450N/A u8 channels; /* max number of channels - 1 */
1450N/A u8 freq;
1450N/A u8 byte2; /* meaning depends on format */
1450N/A};
1450N/A
1450N/Astruct drm_encoder;
1450N/Astruct drm_connector;
1450N/Astruct drm_display_mode;
1450N/Avoid drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
1450N/Aint drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
1450N/Aint drm_av_sync_delay(struct drm_connector *connector,
1450N/A struct drm_display_mode *mode);
1450N/Astruct drm_connector *drm_select_eld(struct drm_encoder *encoder,
1450N/A struct drm_display_mode *mode);
1450N/A
1450N/A#endif /* __DRM_EDID_H__ */