intel_sdvo_regs.h revision 1450
* Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2006-2007, 2013, Intel Corporation * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * Eric Anholt <eric@anholt.net> * @file SDVO command definitions and structures. /* Note: SDVO detailed timing flags match EDID misc flags. */ /** This matches the EDID DTD structure, more or less */ u16 clock;
/**< pixel clock, in 10kHz units */ u8 h_high;
/**< upper 4 bits each h_active, h_blank */ u8 v_high;
/**< upper 4 bits each v_active, v_blank */ /** lower 4 bits each vsync offset, vsync width */ * 2 high bits of hsync offset, 2 high bits of hsync width, * bits 4-5 of vsync offset, and 2 high bits of vsync width. /** bits 6-7 of vsync offset at bits 6-7 */ u16 min;
/**< pixel clock, in 10kHz units */ u16 max;
/**< pixel clock, in 10kHz units */ /* I2C registers for SDVO */ /** Returns a struct intel_sdvo_caps */ * Reports which inputs are trained (managed to sync). * Devices must have trained within 2 vsyncs of a mode change. /** Returns a struct intel_sdvo_output_flags of active outputs. */ * Sets the current set of active outputs. * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP * on multi-output devices. * Returns the current mapping of SDVO inputs to outputs on the device. * Returns two struct intel_sdvo_output_flags structures. * Sets the current mapping of SDVO inputs to outputs on the device. * Takes two struct i380_sdvo_output_flags structures. * Returns a struct intel_sdvo_output_flags of attached displays. * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. * Takes a struct intel_sdvo_output_flags. * Returns a struct intel_sdvo_output_flags of displays with hot plug * Selects which input is affected by future input commands. * Commands affected include SET_INPUT_TIMINGS_PART[12], * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. * Takes a struct intel_sdvo_output_flags of which outputs are targetted by * future output commands. * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. * Generates a DTD based on the given width, height, and flags. * This will be supported by any device supporting scaling or interlaced /** Returns a struct intel_sdvo_pixel_clock_range */ /** Returns a struct intel_sdvo_pixel_clock_range */ /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ /** 5 bytes of bit flags for TV formats shared by all TV format functions */ /** Returns the resolutiosn that can be used with the given TV format */ /* Get supported resolution with squire pixel aspect ratio that can be scaled for the requested HDTV format */ /* Get supported power state returns info for encoder and monitor, rely on last SetTargetInput and SetTargetOutput calls */ /* Get power state returns info for encoder and monitor, rely on last SetTargetInput and SetTargetOutput calls */ * The panel power sequencing parameters are in units of milliseconds. * The high fields are bits 8:9 of the 10-bit values. /* Set display power state */ /* Picture enhancement limits below are dependent on the current TV format, * and thus need to be queried and set after it. #
endif /* _INTEL_SDVO_REGS_H */