intel_ringbuffer.h revision 1450
824N/A * Copyright (c) 2012, 2013, Oracle and/or its affiliates. All rights reserved. 824N/A * Copyright (c) 2008-2010, 2013, Intel Corporation 824N/A * Permission is hereby granted, free of charge, to any person obtaining a 919N/A * copy of this software and associated documentation files (the "Software"), 919N/A * to deal in the Software without restriction, including without limitation 919N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 919N/A * and/or sell copies of the Software, and to permit persons to whom the 919N/A * Software is furnished to do so, subject to the following conditions: 919N/A * The above copyright notice and this permission notice (including the next 919N/A * paragraph) shall be included in all copies or substantial portions of the 919N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 919N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 919N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 919N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 919N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 919N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 824N/A * Eric Anholt <eric@anholt.net> 824N/A * Zou Nan hai <nanhai.zou@intel.com> 824N/A * Xiang Hai hao<haihao.xiang@intel.com> 824N/A * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" 824N/A * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" 824N/A * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" 824N/A * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same 824N/A * cacheline, the Head Pointer must not be greater than the Tail /** We track the position of the requests in the ring buffer, and * when each is retired we increment last_retired_head as the GPU * must have finished processing the request and so we know we * can advance the ringbuffer up to that position. * last_retired_head is set to -1 after the value is consumed so * we can detect new retirements. u32 gt;
/* protected by dev_priv->irq_lock */ u32 pm;
/* protected by dev_priv->rps.lock (sucks) */ /* Some chipsets are not quite as coherent as advertised and need * an expensive kick to force a true read of the up-to-date seqno. * However, the up-to-date seqno is not always required and the last * seen value is good enough. Note that the seqno will always be * monotonic, even if not coherent. /* our mbox written by others */ /* mboxes this ring signals to */ * List of objects currently involved in rendering from the * Includes buffers having the contents of their GPU caches * flushed, not necessarily primitives. last_rendering_seqno * represents when the rendering involved will be completed. * A reference is held on the buffer while on this list. * List of breadcrumbs associated with GPU requests currently * Do we have some not yet emitted requests outstanding? * Do an explicit TLB flush before MI_SET_CONTEXT * vcs -> 0 = bcs, 1 = cs, * bcs -> 0 = cs, 1 = vcs. * Reads a dword out of the status page, which is written to from the command * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or * The following dwords have a reserved meaning: * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. * 0x04: ring 0 head pointer * 0x05: ring 1 head pointer (915-class) * 0x06: ring 2 head pointer (915-class) * 0x10-0x1b: Context status DWords (GM45) * 0x1f: Last written status offset. (GM45) * The area from dword 0x20 to 0x3ff is available for driver usage. #
endif /* _INTEL_RINGBUFFER_H_ */