intel_display.c revision 1450
749N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 749N/A * Copyright (c) 2006-2007, 2013, Intel Corporation 919N/A * Permission is hereby granted, free of charge, to any person obtaining a 919N/A * copy of this software and associated documentation files (the "Software"), 919N/A * to deal in the Software without restriction, including without limitation 919N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense, 919N/A * and/or sell copies of the Software, and to permit persons to whom the 919N/A * Software is furnished to do so, subject to the following conditions: 919N/A * The above copyright notice and this permission notice (including the next 919N/A * paragraph) shall be included in all copies or substantial portions of the 919N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 919N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 919N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 919N/A * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 919N/A * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 919N/A * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 749N/A * DEALINGS IN THE SOFTWARE. 1097N/A * Eric Anholt <eric@anholt.net> 749N/Astatic inline u32 /* units of 100MHz */ .m = { .
min =
96, .
max =
140 },
.p = { .
min =
4, .
max =
128 },
.m = { .
min =
96, .
max =
140 },
.p = { .
min =
4, .
max =
128 },
.m = { .
min =
70, .
max =
120 },
.m = { .
min =
70, .
max =
120 },
.m = { .
min =
104, .
max =
138 },
.p = { .
min =
10, .
max =
30 },
/* n.min 1->2 fix high resolution issue */ .m = { .
min =
104, .
max =
138 },
.m = { .
min =
104, .
max =
138 },
.p = { .
min =
28, .
max =
112 },
.m = { .
min =
104, .
max =
138 },
.p = { .
min =
14, .
max =
42 },
/* Pineview's Ncounter is a ring counter */ .m = { .
min =
2, .
max =
256 },
/* Pineview only has one combined m divider, which we treat as m2. */ .m = { .
min =
2, .
max =
256 },
.p = { .
min =
7, .
max =
112 },
/* Ironlake / Sandybridge * We calculate clock using (register_value + 2) for N/M1/M2, so here * the range value for them is (actual_value - 2). /* n.min 1->2 fix high resolution issue */ .m = { .
min =
79, .
max =
127 },
.m = { .
min =
79, .
max =
118 },
.p = { .
min =
28, .
max =
112 },
.m = { .
min =
79, .
max =
127 },
.p = { .
min =
14, .
max =
56 },
/* LVDS 100mhz refclk limits. */ .m = { .
min =
79, .
max =
126 },
.p = { .
min =
28, .
max =
112 },
.m = { .
min =
79, .
max =
126 },
.p = { .
min =
14, .
max =
42 },
.m = { .
min =
22, .
max =
450 },
/* guess */ .p = { .
min =
10, .
max =
30 },
.m = { .
min =
60, .
max =
300 },
/* guess */ .p = { .
min =
10, .
max =
30 },
.m = { .
min =
22, .
max =
450 },
.p = { .
min =
10, .
max =
30 },
}
else /* The option is for other outputs *//* m1 is reserved as 0 in Pineview, n is a ring counter */ * Returns whether any output on the specified pipe is of the specified type * Returns whether the given set of divisors are valid for a given refclk with /* XXX: We may need to be checking "Dot clock" depending on the multiplier, * connector, etc., rather than just a single range. * For LVDS just rely on its current settings for dual-channel. * We haven't figured out how to reliably set up different * For LVDS just rely on its current settings for dual-channel. * We haven't figured out how to reliably set up different /* approximately equals target * 0.00585 */ /* based on hardware requirement prefer smaller n to precision */ /* based on hardware requirement prefer larger m1,m2 */ /* based on hardware requirement, prefer smaller n to precision */ /* based on hardware requirement, prefer bigger m1,m2 values */ * intel_wait_for_vblank - wait for vblank on a given pipe * @pipe: pipe to wait for * Wait for vblank to occur on a given pipe. Needed for various bits of /* Clear existing vblank status. Note this will clear any other * sticky status fields as well. * This races with i915_driver_irq_handler() with the result * that either function could miss a vblank event. Here it is not * fatal, as we will either wait upon the next vblank interrupt or * timeout. Generally speaking intel_wait_for_vblank() is only * called during modeset at which time the GPU should be idle and * should *not* be performing page flips and thus not waiting on * Currently, the result of us stealing a vblank from the irq * handler is that a single frame will be skipped during swapbuffers. /* Wait for vblank interrupt bit to set */ * intel_wait_for_pipe_off - wait for pipe to turn off * @pipe: pipe to wait for * After disabling a pipe, we can't wait for vblank in the usual way, * spinning on the vblank interrupt status bit, since we won't actually * see an interrupt when the pipe is disabled. * wait for the pipe register state bit to turn off * wait for the display line value to settle (it usually * ends up stopping at the start of the next frame). /* Wait for the Pipe State to go off */ /* Wait for the display line to settle */ * ibx_digital_port_connected - is the specified port connected? * @dev_priv: i915 private structure * @port: the port to test * Returns true if @port is connected, false otherwise. /* Only for pre-ILK configs */ DRM_ERROR(
"PLL state assertion failure (expected %s, current %s)",
/* On Haswell, DDI is used instead of FDI_TX_CTL */ DRM_ERROR(
"FDI TX state assertion failure (expected %s, current %s)\n",
DRM_ERROR(
"FDI RX state assertion failure (expected %s, current %s)\n",
/* ILK FDI PLL is always enabled */ /* On Haswell, DDI ports are responsible for the FDI PLL setup */ DRM_ERROR(
"FDI TX PLL assertion failure, should be active but is disabled\n");
DRM_ERROR(
"FDI RX PLL assertion failure, should be active but is disabled\n");
DRM_ERROR(
"panel assertion failure, pipe %c regs locked\n",
/* if we need the pipe A quirk it must be always on */ DRM_ERROR(
"pipe %c assertion failure (expected %s, current %s)\n",
DRM_ERROR(
"plane %c assertion failure, should be active but is disabled\n",
/* Planes are fixed to pipes on ILK+ */ DRM_ERROR(
"plane %c assertion failure, should be disabled but not\n",
/* Need to check both planes against the pipe */ DRM_ERROR(
"plane %c assertion failure, should be off on pipe %c but is still active\n",
DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
DRM_ERROR(
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
DRM_ERROR(
"PCH refclk assertion failure, should be active but is disabled\n");
DRM_ERROR(
"transcoder assertion failed, should be off on pipe %c but is still active\n",
DRM_ERROR(
"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
DRM_ERROR(
"IBX PCH dp port still using transcoder B\n");
DRM_ERROR(
"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
DRM_ERROR(
"IBX PCH hdmi port still using transcoder B\n");
DRM_ERROR(
"PCH VGA enabled on transcoder %c, should be disabled\n",
DRM_ERROR(
"PCH LVDS enabled on transcoder %c, should be disabled\n",
* intel_enable_pll - enable a PLL * @dev_priv: i915 private structure * @pipe: pipe PLL to enable * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to * make sure the PLL reg is writable first though, since the panel write * protect mechanism may be enabled. * Note! This is for pre-ILK only. * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. /* No really, not for ILK+ */ /* PLL is protected by panel, make sure we can write it */ /* We do this three times for luck */ udelay(
150);
/* wait for warmup */ udelay(
150);
/* wait for warmup */ udelay(
150);
/* wait for warmup */ * intel_disable_pll - disable a PLL * @dev_priv: i915 private structure * @pipe: pipe PLL to disable * Disable the PLL for @pipe, making sure the pipe is off first. * Note! This is for pre-ILK only. /* Don't disable pipe A or pipe A PLLs if needed */ /* Make sure the pipe isn't still relying on us */ DRM_ERROR(
"timed out waiting for port %c ready: 0x%08x\n",
* ironlake_enable_pch_pll - enable PCH PLL * @dev_priv: i915 private structure * @pipe: pipe PLL to enable * The PCH PLL needs to be enabled before the PCH transcoder, since it * drives the transcoder clock. /* PCH PLLs only available on ILK, SNB and IVB */ /* PCH only available on ILK+ */ /* PCH only available on ILK+ */ /* Make sure PCH DPLL is enabled */ /* FDI must be feeding us bits for PCH ports */ /* Workaround: Set the timing override bit before enabling the * make the BPC in transcoder be consistent with /* PCH only available on ILK+ */ /* FDI must be feeding us bits for PCH ports */ /* Workaround: set timing override bit. */ DRM_ERROR(
"Failed to enable PCH transcoder\n");
/* FDI relies on the transcoder */ /* Ports must be off as well */ /* wait for PCH transcoder off, transcoder state */ /* Workaround: Clear the timing override chicken bit again. */ /* wait for PCH transcoder off, transcoder state */ DRM_ERROR(
"Failed to disable PCH transcoder\n");
/* Workaround: clear timing override bit. */ * intel_enable_pipe - enable a pipe, asserting requirements * @dev_priv: i915 private structure * @pch_port: on ILK+, is this pipe driving a PCH port or not * Enable @pipe, making sure that various hardware specific requirements * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. * @pipe should be %PIPE_A or %PIPE_B. * Will wait until the pipe is actually running (i.e. first vblank) before * A pipe without a PLL won't actually be able to drive bits from * a plane. On ILK+ the pipe PLLs are integrated, so we don't /* if driving the PCH, we need FDI enabled */ /* FIXME: assert CPU port conditions for SNB+ */ * intel_disable_pipe - disable a pipe, asserting requirements * @dev_priv: i915 private structure * Disable @pipe, making sure that various hardware specific requirements * are met, if applicable, e.g. plane disabled, panel fitter off, etc. * @pipe should be %PIPE_A or %PIPE_B. * Will wait until the pipe has shut down before returning. * Make sure planes won't keep trying to pump pixels to us, * or we might hang the display. /* Don't disable pipe A or pipe A PLLs if needed */ * Plane regs are double buffered, going from enabled->disabled needs a * trigger in order to latch. The display address reg provides this. * intel_enable_plane - enable a display plane on a given pipe * @dev_priv: i915 private structure * @plane: plane to enable * Enable @plane on @pipe, making sure that @pipe is running first. /* If the pipe isn't enabled, we can't pump pixels and may hang */ * intel_disable_plane - disable a display plane * @dev_priv: i915 private structure * @plane: plane to disable * @pipe: pipe consuming the data * Disable @plane; should be an independent operation. /* pin() will align the object as required by fence */ /* Despite that we check this in framebuffer_init userspace can * screw us over and change the tiling after the fact. Only * pinned buffers can't change their tiling. */ /* Note that the w/a also requires 64 PTE of padding following the * bo. We currently fill all unused PTE with the shadow page and so * we should always have valid PTE following the scanout preventing /* Install a fence for tiled scan-out. Pre-i965 always needs a * fence, whereas 965+ only requires a fence if using * framebuffer compression. For simplicity, we always install * a fence as the cost is not that onerous. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel * is assumed to be a power-of-two. */ /* Mask out pixel format bits in case we change it */ /* Mask out pixel format bits in case we change it */ /* Assume fb object is pinned & idle & fenced and just update base pointers */ * Flips in the rings have been nuked by the reset, * so complete all pending flips so that user space * will get its events and not get stuck. * Also update the base address of all primary * planes to the the last fb to make sure we're * showing the correct fb after a reset. * Need to make two loops over the crtcs so that we * don't try to grab a crtc mutex before the * pending_flip_queue really got woken up. /* Big Hammer, we also need to ensure that any pending * MI_WAIT_FOR_EVENT inside a user batch buffer on the * current scanout is retired before unpinning the old * This should only fail upon a hung GPU, in which case we DRM_ERROR(
"no plane for crtc: plane %c, num_pipes %d\n",
DRM_ERROR(
"failed to update base address\n");
/* enable normal train */ /* wait one idle pattern time */ /* IVB wants error correction enabled */ * When everything is off disable fdi C so that we could enable fdi B * with all lanes. Note that we don't care about enabled pipes without * an enabled pch encoder. /* The FDI link training functions for ILK/Ibexpeak. */ /* FDI needs bits from pipe & plane first */ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit /* enable CPU FDI TX and PCH FDI RX */ /* Ironlake workaround, enable clock pointer after FDI enable*/ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit /* enable CPU FDI TX and PCH FDI RX */ for (i = 0; i <
4; i++ ) {
for (i = 0; i <
4; i++ ) {
/* Manual link training for Ivy Bridge A0 parts */ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit /* enable CPU FDI TX and PCH FDI RX */ for (i = 0; i <
4; i++ ) {
for (i = 0; i <
4; i++ ) {
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */ /* Switch from Rawclk to PCDclk */ /* Enable CPU FDI TX PLL, always on for Ironlake */ /* Switch from PCDclk to Rawclk */ /* Disable CPU FDI TX PLL */ /* Wait for the clocks to turn off. */ /* disable CPU FDI tx and PCH FDI rx */ /* Ironlake workaround, disable clock pointer after downing FDI */ /* still set train pattern 1 */ /* BPC in FDI rx is consistent with that in PIPECONF */ /* Program iCLKIP clock to the desired frequency */ /* It is necessary to ungate the pixclk gate prior to programming * the divisors, and gate it back when it is done. /* 20MHz is a corner case which is out of range for the 7-bit divisor */ /* The iCLK virtual clock root frequency is in MHz, * but the crtc->mode.clock in in KHz. To get the divisors, * it is necessary to divide one by another, so we * convert the virtual clock precision to KHz here for higher /* This should not happen with any sane values */ DRM_DEBUG_KMS(
"iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
/* Program SSCDIVINTPHASE6 */ /* Enable modulator and associated divider */ /* Wait for initialization time */ * Enable PCH resources required for PCH ports: * - update transcoder timings /* Write the TU size bits before fdi link training, so that error /* For PCH output, training FDI link */ /* XXX: pch pll's can be enabled any time before we enable the PCH * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. * Note that enable_pch_pll tries to do the right thing, but get_pch_pll * unconditionally resets the pll - we need that to have the right LVDS /* set transcoder timing */ /* For PCH DP, enable TRANS_DP_CTL */ temp |=
bpc <<
9;
/* same format but at 11:9 */ /* Set transcoder timing. */ DRM_ERROR(
"PCH PLL refcount is 0, but it's still active");
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ /* Only want to check enabled timings first */ DRM_DEBUG_KMS(
"CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
/* Ok no matching timings, maybe there's a free one? */ /* Wait for the clocks to stabilize before rewriting the regs */ /* Force use of hard-coded filter coefficients * as some pre-programmed values are broken, /* Note: FDI PLL enabling _must_ be done before we enable the * cpu pipes, hence this is separate from all the other fdi/pch * On ILK+ LUT must be loaded before the pipe is running but with * There seems to be a race in PCH platform hw (at least on some * outputs) where an enabled pipe still completes any pageflip right * away (as if the pipe is off) instead of waiting for vblank. As soon * as the first vblank happend, everything works as expected. Hence just * wait for one vblank before returning to avoid strange things /* IPS only exists on ULT machines and is tied to pipe A. */ /* We can only enable IPS after we enable a plane and wait for a vblank. * We guarantee that the plane is enabled by calling intel_enable_ips * only after intel_enable_plane. And intel_enable_plane already waits * for a vblank, so all we need to do here is to enable the IPS bit. */ /* We need to wait for a vblank before we can disable the plane. */ * On ILK+ LUT must be loaded before the pipe is running but with * There seems to be a race in PCH platform hw (at least on some * outputs) where an enabled pipe still completes any pageflip right * away (as if the pipe is off) instead of waiting for vblank. As soon * as the first vblank happend, everything works as expected. Hence just * wait for one vblank before returning to avoid strange things /* To avoid upsetting the power well on haswell only disable the pfit if * it's in use. The hw state code will make sure we get this right. */ /* disable TRANS_DP_CTL */ /* FBC must be disabled before disabling the plane on HSW. */ /* Let userspace switch the overlay on again. In most cases userspace * has to recompute where to put it anyway. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware * cursor plane briefly if not already running after enabling the display * This workaround avoids occasional blank screens when self refresh is * The panel fitter should only be adjusted whilst the pipe is disabled, * according to register description and PRM. /* Border color in case we don't scale up to the full screen. Black by * default, change to something else for debugging. */ /* VLV wants encoder enabling _before_ the pipe is up. */ /* The fixup needs to happen before cursor is enabled */ /* Give the overlay scaler a chance to enable if it's on this pipe */ /* Give the overlay scaler a chance to disable if it's on this pipe */ * Sets the power management mode of the pipe and plane. /* crtc should still be enabled when we disable it. */ /* Update computed state. */ /* Simple dpms helper for encodres with just one connector, no cloning and only * one kind of off state. It clamps all !ON modes to fully OFF and changes the * state of the entire output pipe. */ /* Cross check the actual hw state with our own modeset state tracking (and it's * internal consistency). */ DRM_ERROR(
"active connector not linked to encoder\n");
DRM_ERROR(
"encoder->connectors_active not set\n");
DRM_ERROR(
"encoder active on the wrong pipe\n");
/* Even simpler default implementation, if there's really no special case to /* All the simple cases only support two dpms states. */ /* Only need to change hw state when actually enabled */ /* Simple connector->get_hw_state implementation for encoders that support only * one connector and no cloning and hence the encoder state determines the state /* Ivybridge 3 pipe is really complicated */ DRM_DEBUG_KMS(
"invalid shared fdi lane config on pipe %c: %i lanes\n",
DRM_DEBUG_KMS(
"invalid shared fdi lane config on pipe %c: %i lanes\n",
DRM_DEBUG_KMS(
"fdi link B uses too many lanes to enable link C\n");
/* FDI is a binary signal running at ~2.7GHz, encoding * each output octet as 10 bits. The actual frequency * is stored as a divider into a 100MHz clock, and the * mode pixel clock is stored in units of 1KHz. * Hence the bw of each lane in terms of the mode signal DRM_DEBUG_KMS(
"fdi link bw constraint, reducing pipe bpp to %i\n",
/* FDI link clock is fixed at 2.7G */ /* All interlaced capable intel hw wants timings in frames. Note though * that intel_lvds_mode_fixup does some funny tricks with the crtc * timings, so we need to be careful not to clobber these.*/ /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. /* only a 8bpc pipe, with 6bpc dither through the panel fitter /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old * clock survives for now. */ return 400000;
/* FIXME */ /* Assume that the hardware is in the high speed state. This static void compute_m_n(
unsigned int m,
unsigned int n,
int refclk =
27000;
/* for DP & HDMI */ return 100000;
/* only one validated so far */ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. /* See eDP HDMI DPIO driver vbios notes doc */ /* PLL B needs special handling */ /* Set up Tx target for periodic Rcomp update */ /* Disable target IRef on PLL */ /* Set idtafcrecal before PLL is enabled */ * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, * but we don't support that). * Note: don't use the DAC post divider as it seems unstable. /* Set HBR and RBR LPF coefficients */ }
else {
/* HDMI or VGA */ /* Enable DPIO clock input */ /* compute bitmask from p1 value */ /* Wait for the clocks to stabilize. */ /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. /* Wait for the clocks to stabilize. */ /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. /* We need to be careful not to changed the adjusted mode, for otherwise * the hw state checker will get angry at the mismatch. */ /* the chip adds 2 halflines automatically */ /* Workaround: when the EDP input selection is B, the VTOTAL_B must be * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is * documented on the DDI_FUNC_CTL register description, EDP Input Select /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. /* Enable pixel doubling when the dot clock is > 90% of the (display) * XXX: No double-wide on 915GM pipe B. Is that the only reason for the /* only g4x and later have fancy bpc/dither controls */ /* Bspec claims that we can't use dithering for 30bpp pipes. */ /* Case prevented by intel_choose_pipe_bpp_dither. */ * Returns a set of divisors for the desired target clock with the given * refclk, or FALSE. The returned values represent the clock equation: * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. DRM_ERROR(
"Couldn't find PLL settings for mode!\n");
/* Ensure that the cursor is valid for the new mode before changing... */ * Ensure we match the reduced clock's P to the target clock. * If the clocks don't match, we can't switch the display clock * by using the FP0/FP1. In such case we will disable the LVDS /* Compat-code for transition, will disappear. */ /* Set up the display plane register */ /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. /* Check whether the pfit is attached to our pipe. */ /* Note that on i915G/GM the pixel multiplier is in the sdvo * port and will be fixed up in the encoder->get_config /* We need to take the global config into account */ /* Ironlake: try to setup display ref clock before DPLL * enabling. This is only under driver's control after * PCH B stepping, previous chipset stepping should be /* As we must carefully and slowly disable/enable each source in turn, * compute the final state we want first and check if we need to * make any changes at all. /* Always enable nonspread source */ /* SSC must be turned on before enabling the CPU output */ /* Get SSC going before enabling the outputs */ /* Enable CPU source on CPU attached eDP */ /* Turn off CPU output */ /* Turn off the SSC source */ /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ /* XXX: Rip out SDV support once Haswell ships for real. */ DRM_ERROR(
"FDI mPHY reset assert timeout\n");
DRM_ERROR(
"FDI mPHY reset de-assert timeout\n");
tmp |= (
0x3F <<
24) | (
0xF <<
20) | (
0xF <<
16);
tmp |= (
0x3F <<
24) | (
0xF <<
20) | (
0xF <<
16);
tmp |= (
1 <<
24) | (
1 <<
21) | (
1 <<
18);
tmp |= (
1 <<
24) | (
1 <<
21) | (
1 <<
18);
/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ * Initialize reference clocks when the driver loads /* Case prevented by intel_choose_pipe_bpp_dither. */ * Set up the pipe CSC unit. * Currently only full range RGB to limited range RGB conversion * is supported, but eventually this should handle various * RGB<->YCbCr scenarios as well. * TODO: Check what kind of values actually come out of the pipe * with these coeff/postoff values and adjust to get the best * accuracy. Perhaps we even need to take the bpc value into coeff = ((
235 -
16) * (
1 <<
12) /
255) &
0xff8;
/* 0.xxx... */ * GY/GU and RY/RU should be the other way around according * to BSpec, but reality doesn't agree. Just set them up in * a way that results in the correct picture. postoff = (
16 * (
1 <<
13) /
255) &
0x1fff;
* Returns a set of divisors for the desired target clock with the given * refclk, or FALSE. The returned values represent the clock equation: * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. * Ensure we match the reduced clock's P to the target clock. * If the clocks don't match, we can't switch the display clock * by using the FP0/FP1. In such case we will disable the LVDS * Account for spread spectrum to avoid * oversubscribing the link. Max center spread * is 2.5%; use 5% for safety's sake. /* Enable autotuning of the PLL clock (if permissible) */ /* compute bitmask from p1 value */ DRM_ERROR(
"Couldn't find PLL settings for mode!\n");
/* Compat-code for transition, will disappear. */ /* Ensure that the cursor is valid for the new mode before changing... */ /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ * We previously verified the shared_dpll in the eDP case, * so pll should not be NULL from above call. /* Wait for the clocks to stabilize. */ /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. /* Set up the display plane register */ /* We currently do not free assignements of panel fitters on * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ /* XXX: Can't properly read out the pch dpll pixel multiplier * since we don't have state tracking for pch clocks yet. */ /* Ensure that the cursor is valid for the new mode before changing... */ /* Set up the display plane register */ DRM_ERROR(
"unknown pipe linked to edp transcoder\n");
* Haswell has only FDI/PCH transcoder A. It is which is connected to * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. for (i = 0; i <
eld[
2]; i++)
len = (i >>
9) &
0x1f;
/* ELD buffer size */ for (i = 0; i <
len; i++)
/* Audio output enable */ /* Wait for 1 vertical blank */ /* Set ELD valid state */ /* clear N_programing_enable and N_value_index */ eld[
5] |= (
1 <<
2);
/* Conn_Type, 0x1 = DisplayPort */ len =
min(
eld[
2],
21);
/* 84 bytes of hw ELD buffer */ for (i = 0; i <
len; i++)
/* operate blindly on all ports */ eld[
5] |= (
1 <<
2);
/* Conn_Type, 0x1 = DisplayPort */ len =
min(
eld[
2],
21);
/* 84 bytes of hw ELD buffer */ for (i = 0; i <
len; i++)
/** Loads the palette/gamma unit for the CRTC with the prepared values */ /* The clocks have to be on to load the palette. */ /* use legacy palette for Ironlake */ /* Workaround : Do not read or write the pipe palette/gamma data while * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. for (i = 0; i <
256; i++) {
/* On these chipsets we can only modify the base whilst * the cursor is disabled. /* XXX width must be 64, stride 256 => 0x00 << 28 */ cntl |=
pipe <<
28;
/* Connect to correct pipe */ /* and commit changes on next vblank */ /* and commit changes on next vblank */ /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ /* if we want to turn off the cursor ignore width and height */ /* Currently we only support 64x64 cursors */ DRM_ERROR(
"we currently only support 64x64 cursors\n");
/* we only need to pin inside GTT if cursor is non-phy */ /* Note that the w/a also requires 2 PTE of padding following * the bo. We currently fill all unused PTE with the shadow * page and so we should always have valid PTE following the * cursor preventing the VT-d warning. DRM_ERROR(
"failed to move cursor bo into the GTT\n");
DRM_ERROR(
"failed to release fence for cursor");
/** Sets the color ramps on behalf of RandR */ /* VESA 640x480x72Hz mode to set on the pipe */ * Algorithm gets a little messy: * - if the connector already has an assigned crtc, use it (but make * - try to find the first unused crtc that can drive this connector, * and use that if we find one /* See if we already have a CRTC for this connector */ /* Make sure the crtc and connector are running */ /* Make sure the crtc and connector are running */ /* Find an unused one (if possible) */ * If we didn't find an unused CRTC, don't use any. /* We need a framebuffer large enough to accommodate all accesses * that the plane may generate whilst we perform load detection. * We can not rely on the fbcon either being present (we get called * during its initialisation to detect all boot displays, or it may * not even exist) or that it is large enough to satisfy the DRM_DEBUG_KMS(
"failed to allocate framebuffer for load-detection\n");
/* let the connector get through one full cycle before testing */ /* Switch crtc and encoder back off if necessary */ /* Returns the clock of the currently programmed mode of the given pipe. */ /* XXX: might not be 66MHz */ /* XXX: It would be nice to validate the clocks, but we can't reuse * i830PllIsValid() because it relies on the xf86_config connector * configuration being accurate, which it isn't necessarily. /** Returns the currently programmed mode of the given pipe. */ * Since this is called by a timer, we should never get here in /* Ignore early vblank irqs */ /* NB: An MMIO update of the plane base pointer will also * generate a page-flip completion irq, i.e. every modeset * is also accompanied by a spurious intel_prepare_page_flip(). /* Ensure that the work item is consistent when activating it ... */ /* and that it is marked active as soon as the irq could fire. */ /* Can't queue multiple flips, so wait for the previous * one to finish before executing the next. /* i965+ uses the linear or tiled offsets from the * Display Registers (which do not change across a page-flip) * so we need only reprogram the base address. /* XXX Enabling the panel-fitter across page-flip is so far * untested on non-native modes, so ignore it for now. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; /* Contrary to the suggestions in the documentation, * "Enable Panel Fitter" does not seem to be required when page * flipping with a non-native mode, and worse causes a normal * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; * On gen7 we currently use the blit ring because (in early silicon at least) * the render ring doesn't give us interrpts for page flip completion, which * means clients will hang after the first flip is queued. Fortunately the * blit ring generates interrupts properly, so use it instead. DRM_ERROR(
"unknown plane in flip command\n");
/* Can't change pixel format via MI display flips. */ * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. /* We borrow the event spin lock for protecting unpin_work */ /* Reference the objects for the scheduled work. */ * intel_modeset_update_staged_output_state * Updates the staged output configuration state, e.g. after we've read out the * intel_modeset_commit_output_state * This function copies the stage display pipe configuration to the real one. DRM_DEBUG_KMS(
"[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
/* Don't use an invalid EDID bpc value */ DRM_DEBUG_KMS(
"clamping display bpp (was %d) to EDID reported max of %d\n",
/* Clamp bpp to 8 on screens without EDID 1.4 */ DRM_DEBUG_KMS(
"clamping display bpp (was %d) to default limit of 24\n",
bpp =
8*
3;
/* since we go through a colormap */ /* checked in intel_framebuffer_init already */ bpp =
6*
3;
/* min is 18bpp */ /* checked in intel_framebuffer_init already */ /* checked in intel_framebuffer_init already */ /* TODO: gen4+ supports 16 bpc floating point, too. */ /* Clamp display bpp to EDID value */ DRM_DEBUG_KMS(
"fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
DRM_DEBUG_KMS(
"gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
/* Compute a starting value for pipe_config->pipe_bpp taking the source * plane pixel format and any sink constraints into account. Returns the * source plane bpp so that dithering can be selected on mismatches * after encoders and crtc also have had their say. */ /* Ensure the port clock defaults are reset when retrying. */ /* Pass our mode to the connectors and the CRTC to give them a chance to * adjust it according to limitations or connector properties, and also * a chance to reject the mode entirely. /* Set default port clock if not overwritten by the encoder. Needs to be * done afterwards in case the encoder adjusts the mode. */ DRM_ERROR(
"loop in pipe configuration computation");
/* Computes which crtcs are affected and sets the relevant bits in the mask. For * simplicity we use the crtc's pipe number (because it's easier to obtain). */ /* Check which crtcs have changed outputs connected to them, these need * to be part of the prepare_pipes mask. We don't (yet) support global * modeset across multiple crtcs, so modeset_pipes will only have one /* Check for any pipes that will be fully disabled ... */ /* Don't try to disable disabled crtcs. */ /* set_mode is also used to update properties on life display pipes. */ * For simplicity do a full modeset on any pipe where the output routing * changed. We could be more clever, but that would require us to be * more careful with calling the relevant encoder->mode_set functions. /* ... and mask these out. */ * HACK: We don't (yet) fully support global modesets. intel_set_config * obies this rule, but the modeset restore mode of * intel_modeset_setup_hw_state does not. DRM_DEBUG_KMS(
"set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
/* Update computed state. */ "(expected 0x%08x, found 0x%08x)\n", \
"(expected %i, found %i)\n", \
"(expected %i, found %i)\n", \
/* pfit ratios are autocomputed by the hw on gen4+ */ * ->get_hw_state callbacks. */ DRM_ERROR(
"connector's staged encoder doesn't match current encoder\n");
DRM_ERROR(
"encoder's stage crtc doesn't match current crtc\n");
DRM_ERROR(
"encoder's active_connectors set, but no crtc\n");
DRM_ERROR(
"encoder's enabled state mismatch " "(expected %i, found %i)\n",
DRM_ERROR(
"encoder's computed active state doesn't match tracked active state " DRM_ERROR(
"encoder's hw state doesn't match sw tracking " "(expected %i, found %i)\n",
DRM_ERROR(
"active encoder's pipe doesn't match" "(expected %i, found %i)\n",
DRM_ERROR(
"active crtc, but not enabled in sw tracking\n");
DRM_ERROR(
"crtc's computed active state doesn't match tracked active state " DRM_ERROR(
"crtc's computed enabled state doesn't match tracked enabled state " /* hw state is inconsistent with the pipe A quirk */ DRM_ERROR(
"crtc active state doesn't match with hw state " DRM_DEBUG_KMS(
"more active pll users than references: %i vs %i\n",
DRM_DEBUG_KMS(
"pll active crtcs mismatch (expected %i, found %i)\n",
DRM_DEBUG_KMS(
"pll enabled crtcs mismatch (expected %i, found %i)\n",
/* Hack: Because we don't (yet) support global modeset on multiple * crtcs, we don't keep track of the new mode for more than one crtc. * Hence simply check whether any bit is set in modeset_pipes in all the * pieces of code that are not yet converted to deal with mutliple crtcs * changing their mode at the same time. */ /* crtc->mode is already used by the ->mode_set callbacks, hence we need * to set it here already despite that we pass it down the callchain. /* Only after disabling all output pipelines that will be changed can we * update the the output configuration. */ /* Set up the DPLL and any encoders state that needs to adjust or depend /* Now enable the clocks, plane, pipe, and connectors that we set up. */ /* Store real post-adjustment hardware mode. */ /* Calculate and store various constants which * are later needed by vblank and swap-completion * timestamping. They are derived from true hwmode. /* FIXME: add subpixel order */ /* Copy data. Note that driver private data is not affected. * Should anything bad happen only the expected state is * restored, not the drivers personal bookkeeping. /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ /* If we have no fb then treat it as a full mode set */ /* The upper layers ensure that we either disabl a crtc or have a list * of connectors. For paranoia, double-check this. */ /* Otherwise traverse passed in connector list and get encoders /* If we disable the crtc, disable all its connectors. Also, if * the connector is on the changing crtc but not on the new * connector list, disable it. */ /* connector->new_encoder is now updated for all connectors. */ /* Update crtc of enabled connectors. */ /* Make sure the new CRTC will work with the encoder */ /* Check for any encoders that needs to be disabled. */ /* Only now check for crtc changes so we don't miss encoders * that will be disabled. */ /* Now we've also updated encoder->new_crtc for all encoders. */ /* Enforce sane interface api - has been abused by the fb helper. */ DRM_DEBUG_KMS(
"[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
/* Compute whether we need a full modeset, only an fb base update or no * change at all. In the future we might also check whether only the * mode changed, e.g. for LVDS where we only change the panel fitter in /* Try to restore the config */ DRM_ERROR(
"failed to restore config after modeset failure\n");
/* PCH refclock must be enabled first */ /* Make sure no transcoder isn't still depending on us. */ for (i = 0; i <
256; i++) {
/* Swap pipes & planes for FBC on pre-965 */ /* Intel hw has only one MUX where enocoders could be cloned. */ /* Haswell uses DDI functions to detect digital outputs */ /* DDI A only supports eDP */ /* DDI B, C and D detection is indicated by the SFUSE_STRAP /* PCH SDVOB multiplex with HDMIB */ /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ /* Before G4X SDVOC doesn't have its own detect register */ DRM_DEBUG(
"hardware does not support tiling Y\n");
DRM_DEBUG(
"pitch (%d) must be at least 64 byte aligned\n",
/* XXX DSPC is limited to 4k tiled */ DRM_DEBUG(
"%s pitch (%d) must be at less than %d\n",
DRM_DEBUG(
"pitch (%d) must match tiling stride (%d)\n",
/* Reject formats not supported by any plane early. */ /* Set up chip specific display functions */ /* Returns the core display clock speed */ /* FIXME: detect B0+ stepping and use auto training */ /* Default just returns -ENODEV to indicate unsupported */ * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, * resume, or other times. This quirk makes sure that's the case for DRM_INFO(
"applying pipe a force quirk\n");
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason DRM_INFO(
"applying lvds SSC disable quirk\n");
* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight DRM_INFO(
"applying inverted panel brightness quirk\n");
* Some machines (Dell XPS13) suffer broken backlight controls if * BLM_PCH_PWM_ENABLE is set. DRM_INFO(
"applying no-PCH_PWM_ENABLE quirk\n");
DRM_INFO(
"Backlight polarity reversed on %s\n",
id->
ident);
.
ident =
"NCR Corporation",
{ }
/* terminating entry */ /* HP Mini needs pipe A force quirk (LP: #322104) */ /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ /* 830/845 need to leave pipe A & dpll A up */ /* Lenovo U160 cannot use SSC on LVDS */ /* Sony Vaio Y cannot use SSC on LVDS */ /* Acer Aspire 5734Z must invert backlight brightness */ /* Dell XPS13 HD Sandy Bridge */ /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ /* Disable the VGA plane that we never use */ /* OSOL_I915 intel_init_quirks(dev); */ /* Just disable it once at startup */ /* Just in case the BIOS is doing something questionable. */ /* We can't just switch on the pipe A, we need to set things up with a * proper mode and output configuration. As a gross hack, enable pipe A * by enabling the load detect pipe once. */ /* Clear any frame start delays used for debugging left by the BIOS */ /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. Note * that gen4+ has a fixed plane -> pipe mapping. */ /* Pipe has the wrong plane attached and the plane is active. * Temporarily change the plane mapping and disable everything /* ... and break all links. */ /* BIOS forgot to enable pipe A, this mostly happens after * resume. Force-enable the pipe to fix this, the update_dpms * call below we restore the pipe to the right state, but leave * the required bits on. */ /* Adjust the state of the output pipe according to whether we /* This can happen either due to bugs in the get_hw_state * functions or because the pipe is force-enabled due to the /* Because we only establish the connector -> encoder -> * crtc links if something is active, this means the * crtc is now deactivated. Break the links. connector * -> encoder links are only establish when things are * actually up, hence no need to break them. */ /* We need to check both for a crtc link (meaning that the * encoder is active and trying to read from a pipe) and the * pipe itself being active. */ DRM_DEBUG_KMS(
"[ENCODER:%d:%s] has active connectors but no active pipe!\n",
/* Connector is active, but has no active pipe. This is * fallout from our resume register restoring. Disable * the encoder manually again. */ * a bug in one of the get_hw_state functions. Or someplace else * in our code, like the register restore mess on resume. Clamp * things to off as a safer default. */ /* Enabled encoders without active connectors will be fixed in /* FIXME: Smash this into the new shared dpll infrastructure. */ /* Scan out the current hw modeset state, sanitizes it and maps it into the drm * and i915 state tracking structures. */ /* HW state is read out, now we need to sanitize this mess. */ * We need to use raw interfaces for restoring state to avoid * checking (bogus) intermediate states. * Interrupts and polling as the first thing to avoid creating havoc. * Too much stuff here (turning of rps, connectors, ...) would * experience fancy races otherwise. /* OSOL_I915 cancel_work_sync(&dev_priv->hotplug_work); */ * Due to the hpd irq storm handling the hotplug work can re-arm the * poll handlers. Hence disable polling after hpd handling is shut down. /* Skip inactive CRTCs */ /* flush any delayed tasks or pending work */ /* OSOL_I915 flush_scheduled_work(); */ /* destroy backlight, if any, before the connectors */ /* current intel driver doesn't take advantage of encoders always give back the encoder for the connector * set vga decode state - true == enable VGA decode /* In the code above we read the registers without checking if the power * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to * prevent the next I915_WRITE from detecting it and printing an error