i915_irq.c revision 1450
98N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 98N/A * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 98N/A * Copyright (c) 2009, 2012, Intel Corporation. 98N/A * All Rights Reserved. 98N/A * Permission is hereby granted, free of charge, to any person obtaining a 98N/A * copy of this software and associated documentation files (the 98N/A * "Software"), to deal in the Software without restriction, including 98N/A * without limitation the rights to use, copy, modify, merge, publish, 98N/A * distribute, sub license, and/or sell copies of the Software, and to 98N/A * permit persons to whom the Software is furnished to do so, subject to 98N/A * the following conditions: 98N/A * The above copyright notice and this permission notice (including the 98N/A * next paragraph) shall be included in all copies or substantial portions 98N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 98N/A * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 98N/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 98N/A * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 98N/A * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 98N/A * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 98N/A * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 98N/A/* For display hotplug interrupt */ * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages * @enable: true if we want to report FIFO underrun errors, false otherwise * This function makes us disable or enable CPU fifo underruns for a specific * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun * reporting for one pipe may also disable all the other CPU error interruts for * the other pipes, due to the fact that there's just one interrupt mask/enable * Returns the previous state of underrun reporting. * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) * @enable: true if we want to report FIFO underrun errors, false otherwise * This function makes us disable or enable PCH fifo underruns for a specific * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO * underrun reporting for one transcoder may also disable all the other PCH * error interruts for the other transcoders, due to the fact that there's just * one interrupt mask/enable bit for all the transcoders. * Returns the previous state of underrun reporting. DRM_ERROR(
"PCH FIFO underrun, but no CRTC using the PCH found\n");
/* Enable the interrupt, clear any pending status */ * i915_pipe_enabled - check if a pipe is enabled * Reading certain registers when the pipe is disabled can hang the chip. * Use this routine to make sure the PLL is running and the pipe is active * before reading such registers if unsure. /* Locking is horribly broken here, but whatever. */ /* Called from drm generic code, passed a 'crtc', which * High & low register fields aren't synchronized, so make sure * we get a low value that's stable across two reads of the high /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. /* Decode into vertical scanout position. Don't have * horizontal scanout position. /* Have access to pixelcount since start of frame. * We can split this into vertical and horizontal /* Test position against vblank region. */ /* Inside "upper part" of vblank area? Apply corrective offset: */ /* Get drm_crtc to timestamp: */ /* Helper routine in DRM core does all the work: */ DRM_DEBUG_KMS(
"[CONNECTOR:%d:%s] status updated from %d to %d\n",
* Handle hotplug events outside the interrupt handler proper. /* HPD irq before everything is fully set up. */ DRM_INFO(
"HPD interrupt storm detected on connector %s: " "switching from hotplug detection to polling\n",
/* if there were no outputs to poll, poll was disabled, * therefore make sure it's enabled when disabling HPD on /* Handle RCS change request from hw */ * For better performance, jump directly * to RPe if we're below it. /* sysfs frequency interfaces may have snuck in while servicing the * ivybridge_parity_work - Workqueue called when a parity error interrupt * @work: workqueue struct * Doesn't actually do anything except notify userspace. As a consequence of * this event, userspace should try to remap the bad rows since statistically * it is likely the same row is more likely to go bad again. /* We must turn off DOP level clock gating to access the L3 registers. * In order to prevent a get/put style interface, acquire struct mutex * any time we access those registers. DRM_DEBUG(
"Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
* IIR bits should never already be set because IMR should * prevent an interrupt from being shown in IIR. The warning * displays a case where we've unsafely cleared * dev_priv->rps.pm_iir. Although missing an interrupt of the same * type is not a problem, it displays a problem in the logic. * The mask bit in IMR is cleared by dev_priv->rps.work. /* Unlike gen6_queue_rps_work() from which this function is originally derived, * we must be able to deal with other PM interrupts. This is complicated because * of the way in which we use the masks to defer the RPS work (which for * posterity is necessary because of forcewake). /* never want to mask useful interrupts. (also posting read) */ /* TODO: if queue_work is slow, move it out of the spinlock */ * Clear the PIPE*STAT regs before the IIR /* Consume port. Then clear IIR or we'll miss events */ /* We get interrupts on unclaimed registers, so check for this before we * do any I915_{READ,WRITE}. */ DRM_ERROR(
"Unclaimed register before interrupt\n");
/* disable master interrupt before clearing iir */ /* Disable south interrupts. We'll only write to SDEIIR once, so further * interrupts will will be stored on its back queue, and then we'll be * able to process them after we restore SDEIER (as soon as we restore * it, we'll get an interrupt if SDEIIR still has something to process * due to its back queue). */ /* On Haswell, also mask ERR_INT because we don't want to risk * generating "unclaimed register" interrupts from inside the interrupt for (i = 0; i <
3; i++) {
/* check event from PCH */ /* clear PCH hotplug event before clear CPU irq */ /* disable master interrupt before clearing iir */ /* Disable south interrupts. We'll only write to SDEIIR once, so further * interrupts will will be stored on its back queue, and then we'll be * able to process them after we restore SDEIER (as soon as we restore * it, we'll get an interrupt if SDEIIR still has something to process * due to its back queue). */ /* check event from PCH */ /* should clear PCH hotplug event before clear CPU irq */ * i915_error_work_func - do process context error handling work * Fire an error uevent so userspace can see that a hang or error /* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */ * Note that there's only one work item which does gpu resets, so we * need not worry about concurrent gpu resets potentially incrementing * error->reset_counter twice. We only need to take care of another * racing irq/hangcheck declaring the gpu dead for a second time. A * quick check for that is good enough: schedule_work ensures the * correct ordering between hang detection and this work item, and since * the reset in-progress bit is only ever set by code outside of this * work we don't need to worry about any other races. /* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */ * After all the gem state is reset, increment the reset * counter and wake up everyone waiting for the reset to * Since unlock operations are a one-sided barrier only, * we need to insert a barrier here to order any seqno /* NB: please notice the memset */ /* Simply ignore tiling or any overlapping fence. * It's part of the error state, and this hopefully * captures what the GPU read. /* We need to copy these to an anonymous buffer as the simplest * method to avoid being overwritten by userspace. /* Currently render ring is the only HW context user */ * i915_capture_error_state - capture an error record for later analysis * Should be called when an error is detected (either a hang or an error * interrupt) to capture error state from the time of the error. Fills * out a structure which becomes available in debugfs for user level tools /* Account for pipe specific data like PIPE*STAT */ DRM_INFO(
"capturing error event; look for more information in " /* Record buffers on the active and pinned lists. */ /* pipestat has already been acked */ * some errors might have become stuck, * i915_handle_error - handle an error interrupt * Do some basic checking of regsiter state at error interrupt time and * dump it to the syslog. Also call i915_capture_error_state() to make * sure we get a record and make it available in debugfs. Fire a uevent * so userspace knows something bad happened (should trigger collection * Wakeup waiting processes so they don't hang /* Ignore early vblank irqs */ /* Either the pending flip IRQ arrived, or we're too early. Don't check */ /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ /* Called from drm generic code, passed 'crtc' which /* maintain vblank delivery even in deep C-states */ /* Called from drm generic code, passed 'crtc' which if ((
ipehr & ~(
0x3 <<
16)) !=
/* ACTHD is likely pointing to the dword after the actual command, * so scan backwards until we find the MBOX. /* cursory check for an unkickable deadlock */ /* Is the chip hanging on a WAIT_FOR_EVENT? * If so we can simply poke the RB_WAIT bit * and break the hang. This should work on * all but the second generation chipsets. * This is called when the chip hasn't reported back with completed * batchbuffers in a long time. The first time this is called we simply record * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses * Further, acthd is inspected to see if the ring is stuck. On stuck case * we kick the ring. If we see no progress on three subsequent calls * again, we assume the chip is wedged and try to fix it. /* Issue a wake-up to catch stuck h/w. */ DRM_ERROR(
"Hangcheck timer elapsed... %s idle\n",
/* We always increment the hangcheck score * if the ring is busy and still processing * the same request, so that no single request * can run indefinitely (such as a chain of * batches). The only time we do not increment * the hangcheck score on this ring, if this * ring is in a legitimate wait for another * ring. In that case the waiting ring is a * victim and we want to be sure we catch the * right culprit. Then every time we do kick * the ring, add a small increment to the * score so that we can catch a batch that is * being repeatedly kicked and so responsible * for stalling the machine. /* Gradually reduce the count so that we catch DoS * attempts across multiple batches. stuck[i] ?
"stuck" :
"no progress",
/* Reset timer case chip hangs without another request * SDEIER is also touched by the interrupt handler to work around missed * PCH interrupts. Hence we can't update it after the interrupt handler * is enabled - instead we unconditionally enable all PCH interrupt * sources here, but then only unmask them as needed with SDEIMR. /* XXX hotplug from PCH */ /* XXX hotplug from PCH */ * Enable digital hotplug on the PCH, and configure the DP short pulse * duration to 2ms (which is the minimum in the Display Port spec) * This register is the same on all known PCH chips. /* enable kind of interrupts always enabled */ /* should always can generate irq */ /* Enable PCU event interrupts * spinlocking not required here for correctness since interrupt * setup is guaranteed to run in single-threaded context. But we * need it to make the assert_spin_locked happy. */ /* enable kind of interrupts always enabled */ /* should always can generate irq */ * make sure to set a known state for only the non-RPS bits. * The RMW is extra paranoia since this should be called after being set * to a known state in preinstall. * toggle them based on usage. /* ack & enable invalid PTE error interrupts */ #
if 0
/* FIXME: add support to irq handler for checking these bits */ /* Unmask the interrupts that we always want on. */ * Returns true when a page flip has completed. /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence * the flip is completed (no longer pending). Since this doesn't raise * an interrupt per se, we watch for the change at vblank. /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces * interrupts (for non-MSI). * Clear the PIPE*STAT regs before the IIR /* Clear enable bits; then clear status bits */ /* Unmask the interrupts that we always want on. */ * Returns true when a page flip has completed. /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence * the flip is completed (no longer pending). Since this doesn't raise * an interrupt per se, we watch for the change at vblank. /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces * interrupts (for non-MSI). /* Clear the PIPE*STAT regs before the IIR */ /* Consume port. Then clear IIR or we'll miss events */ /* With MSI, interrupts are only generated when iir * transitions from zero to nonzero. If another bit got * set while we were handling the existing iir bits, then * we would never get another interrupt. * This is fine on non-MSI as well, as if we hit this path * we avoid exiting the interrupt handler only to generate * Note that for MSI this could cause a stray interrupt report * if an interrupt landed in the time between writing IIR and * the posting read. This should be rare enough to never * trigger the 99% of 100,000 interrupts test for disabling /* Clear enable bits; then clear status bits */ /* Unmask the interrupts that we always want on. */ * Enable some error detection, note the instruction error mask * bit is reserved, so we leave it masked. /* Note HDMI and DP share hotplug bits */ /* enable bits are the same for all generations */ /* Programming the CRT detection parameters tends to generate a spurious hotplug event about three seconds later. So just do it once. /* Ignore TV since it's buggy */ /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces * interrupts (for non-MSI). * Clear the PIPE*STAT regs before the IIR /* Consume port. Then clear IIR or we'll miss events */ /* With MSI, interrupts are only generated when iir * transitions from zero to nonzero. If another bit got * set while we were handling the existing iir bits, then * we would never get another interrupt. * This is fine on non-MSI as well, as if we hit this path * we avoid exiting the interrupt handler only to generate * Note that for MSI this could cause a stray interrupt report * if an interrupt landed in the time between writing IIR and * the posting read. This should be rare enough to never * trigger the 99% of 100,000 interrupts test for disabling /* Share pre & uninstall handlers with ILK/SNB */ /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked checks happy. */