919N/A

830N/A

830N/A#ifndef _I915_DRV_H_

830N/A#define _I915_DRV_H_

830N/A

830N/A#include "i915_drm.h"

830N/A#include "i915_reg.h"

830N/A#include "intel_bios.h"

830N/A#include "intel_ringbuffer.h"

830N/A

830N/A#include <sys/systm.h> /* for __lintzero */

830N/A

830N/A

830N/A#define DRIVER_AUTHOR "Tungsten Graphics, Inc."

830N/A

830N/A#define DRIVER_NAME "i915"

830N/A#define DRIVER_DESC "Intel Graphics for Solaris"

830N/A#define DRIVER_DATE "2013/06/19"

830N/A

830N/Aenum pipe {

830N/A PIPE_A = 0,

830N/A PIPE_B,

830N/A PIPE_C,

830N/A I915_MAX_PIPES

830N/A};

830N/A#define pipe_name(p) ((p) + 'A')

enum transcoder {

TRANSCODER_A = 0,

TRANSCODER_B,

TRANSCODER_C,

TRANSCODER_EDP = 0xF,

};

#define transcoder_name(t) ((t) + 'A')

enum plane {

PLANE_A = 0,

PLANE_B,

PLANE_C,

};

#define plane_name(p) ((p) + 'A')

#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')

enum port {

PORT_A = 0,

PORT_B,

PORT_C,

PORT_D,

PORT_E,

I915_MAX_PORTS

};

#define port_name(p) ((p) + 'A')

enum intel_display_power_domain {

POWER_DOMAIN_PIPE_A,

POWER_DOMAIN_PIPE_B,

POWER_DOMAIN_PIPE_C,

POWER_DOMAIN_PIPE_A_PANEL_FITTER,

POWER_DOMAIN_PIPE_B_PANEL_FITTER,

POWER_DOMAIN_PIPE_C_PANEL_FITTER,

POWER_DOMAIN_TRANSCODER_A,

POWER_DOMAIN_TRANSCODER_B,

POWER_DOMAIN_TRANSCODER_C,

POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,

};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)

enum hpd_pin {

HPD_NONE = 0,

HPD_PORT_A = HPD_NONE, /* PORT_A is internal */

HPD_TV = HPD_NONE, /* TV is known to be unreliable */

HPD_CRT,

HPD_SDVO_B,

HPD_SDVO_C,

HPD_PORT_B,

HPD_PORT_C,

HPD_PORT_D,

HPD_NUM_PINS

};

#define I915_GEM_GPU_DOMAINS \

(I915_GEM_DOMAIN_RENDER | \

I915_GEM_DOMAIN_SAMPLER | \

I915_GEM_DOMAIN_COMMAND | \

I915_GEM_DOMAIN_INSTRUCTION | \

I915_GEM_DOMAIN_VERTEX)

#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)

#define for_each_encoder_on_crtc(dev, __crtc, _intel_encoder) \

list_for_each_entry((_intel_encoder), struct intel_encoder, &(dev)->mode_config.encoder_list, base.head) \

if ((_intel_encoder)->base.crtc == (__crtc))

struct drm_i915_private;

enum intel_dpll_id {

DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */

/* real shared dpll ids must be >= 0 */

DPLL_ID_PCH_PLL_A,

DPLL_ID_PCH_PLL_B,

};

#define I915_NUM_PLLS 2

struct intel_dpll_hw_state {

uint32_t dpll;

uint32_t fp0;

uint32_t fp1;

};

struct intel_shared_dpll {

int refcount; /* count of number of CRTCs sharing this PLL */

int active; /* count of number of active CRTCs (i.e. DPMS on) */

bool on; /* is the PLL actually active? Disabled during modeset */

const char *name;

/* should match the index in the dev_priv->shared_dplls array */

enum intel_dpll_id id;

struct intel_dpll_hw_state hw_state;

void (*enable)(struct drm_i915_private *dev_priv,

struct intel_shared_dpll *pll);

void (*disable)(struct drm_i915_private *dev_priv,

struct intel_shared_dpll *pll);

bool (*get_hw_state)(struct drm_i915_private *dev_priv,

struct intel_shared_dpll *pll,

struct intel_dpll_hw_state *hw_state);

};

struct intel_link_m_n {

uint32_t tu;

uint32_t gmch_m;

uint32_t gmch_n;

uint32_t link_m;

uint32_t link_n;

};

void intel_link_compute_m_n(int bpp, int nlanes,

int pixel_clock, int link_clock,

struct intel_link_m_n *m_n);

extern int gpu_dump;

struct intel_ddi_plls {

int spll_refcount;

int wrpll1_refcount;

int wrpll2_refcount;

};

#define DRIVER_MAJOR 1

#define DRIVER_MINOR 6

#define DRIVER_PATCHLEVEL 20130900

#define WATCH_COHERENCY 0

#define WATCH_LISTS 0

#define WATCH_GTT 0

#define I915_GEM_PHYS_CURSOR_0 1

#define I915_GEM_PHYS_CURSOR_1 2

#define I915_GEM_PHYS_OVERLAY_REGS 3

#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)

struct drm_i915_gem_phys_object {

int id;

struct page **page_list;

drm_dma_handle_t *handle;

struct drm_i915_gem_object *cur_obj;

};

struct mem_block {

struct mem_block *next;

struct mem_block *prev;

int start;

int size;

struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */

};

struct opregion_header;

struct opregion_acpi;

struct opregion_swsci;

struct opregion_asle;

struct intel_opregion {

struct opregion_header *header;

struct opregion_acpi *acpi;

struct opregion_swsci *swsci;

struct opregion_asle *asle;

void *vbt;

u32 *lid_state;

};

#define OPREGION_SIZE (8*1024)

struct intel_overlay;

struct intel_overlay_error_state;

struct drm_i915_master_private {

drm_local_map_t *sarea;

struct _drm_i915_sarea *sarea_priv;

};

#define I915_FENCE_REG_NONE -1

#define I915_MAX_NUM_FENCES 32

#define I915_MAX_NUM_FENCE_BITS 6

struct drm_i915_fence_reg {

struct list_head lru_list;

struct drm_i915_gem_object *obj;

int pin_count;

};

#define I2C_NAME_SIZE 20

struct sdvo_device_mapping {

u8 initialized;

u8 dvo_port;

u8 slave_addr;

u8 dvo_wiring;

u8 i2c_pin;

u8 ddc_pin;

};

struct intel_display_error_state;

struct drm_i915_error_state {

struct kref ref;

u32 eir;

u32 pgtbl_er;

u32 ier;

u32 ccid;

u32 derrmr;

u32 forcewake;

bool waiting[I915_NUM_RINGS];

u32 pipestat[I915_MAX_PIPES];

u32 tail[I915_NUM_RINGS];

u32 head[I915_NUM_RINGS];

u32 ctl[I915_NUM_RINGS];

u32 ipeir[I915_NUM_RINGS];

u32 ipehr[I915_NUM_RINGS];

u32 instdone[I915_NUM_RINGS];

u32 acthd[I915_NUM_RINGS];

u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];

u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];

u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */

/* our own tracking of ring head and tail */

u32 cpu_ring_head[I915_NUM_RINGS];

u32 cpu_ring_tail[I915_NUM_RINGS];

u32 error; /* gen6+ */

u32 err_int; /* gen7 */

u32 instpm[I915_NUM_RINGS];

u32 instps[I915_NUM_RINGS];

u32 extra_instdone[I915_NUM_INSTDONE_REG];

u32 seqno[I915_NUM_RINGS];

u64 bbaddr;

u32 fault_reg[I915_NUM_RINGS];

u32 done_reg;

u32 faddr[I915_NUM_RINGS];

u64 fence[I915_MAX_NUM_FENCES];

struct timeval time;

struct drm_i915_error_ring {

struct drm_i915_error_object {

int page_count;

u32 gtt_offset;

u32 **pages;

} *ringbuffer, *batchbuffer;

struct drm_i915_error_request {

long err_jiffies;

u32 seqno;

u32 tail;

} *requests;

int num_requests;

} ring[I915_NUM_RINGS];

struct drm_i915_error_buffer {

size_t size;

u32 name;

u32 rseqno, wseqno;

u32 gtt_offset;

u32 read_domains;

u32 write_domain;

s32 fence_reg:I915_MAX_NUM_FENCE_BITS;

s32 pinned:2;

u32 tiling:2;

u32 dirty:1;

u32 purgeable:1;

u32 ring:4;

u32 cache_level:2;

} *active_bo, *pinned_bo;

u32 active_bo_count, pinned_bo_count;

struct intel_overlay_error_state *overlay;

struct intel_display_error_state *display;

};

struct intel_crtc_config;

struct intel_crtc;

struct intel_limit;

struct dpll;

struct drm_i915_display_funcs {

bool (*fbc_enabled)(struct drm_device *dev);

void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);

void (*disable_fbc)(struct drm_device *dev);

int (*get_display_clock_speed)(struct drm_device *dev);

int (*get_fifo_size)(struct drm_device *dev, int plane);

/**

bool (*find_dpll)(const struct intel_limit *limit,

struct drm_crtc *crtc,

int target, int refclk,

struct dpll *match_clock,

struct dpll *best_clock);

void (*update_wm)(struct drm_device *dev);

void (*update_sprite_wm)(struct drm_device *dev, int pipe,

uint32_t sprite_width, int pixel_size,

bool enable);

void (*modeset_global_resources)(struct drm_device *dev);

/* Returns the active state of the crtc, and if the crtc is active,

bool (*get_pipe_config)(struct intel_crtc *,

struct intel_crtc_config *);

int (*crtc_mode_set)(struct drm_crtc *crtc,

int x, int y,

struct drm_framebuffer *old_fb);

void (*crtc_enable)(struct drm_crtc *crtc);

void (*crtc_disable)(struct drm_crtc *crtc);

void (*off)(struct drm_crtc *crtc);

void (*write_eld)(struct drm_connector *connector,

struct drm_crtc *crtc);

void (*fdi_link_train)(struct drm_crtc *crtc);

void (*init_clock_gating)(struct drm_device *dev);

int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,

struct drm_framebuffer *fb,

struct drm_i915_gem_object *obj);

int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,

int x, int y);

void (*hpd_irq_setup)(struct drm_device *dev);

/* clock updates for mode set */

/* cursor updates */

/* render clock increase/decrease */

/* display clock increase/decrease */

/* pll clock increase/decrease */

};

struct drm_i915_gt_funcs {

void (*force_wake_get)(struct drm_i915_private *dev_priv);

void (*force_wake_put)(struct drm_i915_private *dev_priv);

};

#define DEV_INFO_FOR_EACH_FLAG(func, sep) \

func(is_mobile) sep \

func(is_i85x) sep \

func(is_i915g) sep \

func(is_i945gm) sep \

func(is_g33) sep \

func(need_gfx_hws) sep \

func(is_g4x) sep \

func(is_pineview) sep \

func(is_broadwater) sep \

func(is_crestline) sep \

func(is_ivybridge) sep \

func(is_valleyview) sep \

func(is_haswell) sep \

func(has_force_wake) sep \

func(has_fbc) sep \

func(has_pipe_cxsr) sep \

func(has_hotplug) sep \

func(cursor_needs_physical) sep \

func(has_overlay) sep \

func(overlay_needs_physical) sep \

func(supports_tv) sep \

func(has_bsd_ring) sep \

func(has_blt_ring) sep \

func(has_vebox_ring) sep \

func(has_llc) sep \

func(has_ddi) sep \

func(has_fpga_dbg)

#define DEFINE_FLAG(name) u8 name:1

#define SEP_SEMICOLON ;

struct intel_device_info {

u32 display_mmio_offset;

u8 num_pipes:3;

u8 gen;

DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);

};

#undef DEFINE_FLAG

#undef SEP_SEMICOLON

enum i915_cache_level {

I915_CACHE_NONE = 0,

I915_CACHE_LLC,

I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */

};

typedef uint32_t gen6_gtt_pte_t;

struct i915_gtt {

unsigned long start; /* Start offset of used GTT */

size_t total; /* Total size GTT can map */

size_t stolen_size; /* Total size of stolen memory */

unsigned long mappable_end; /* End offset that we can CPU map */

drm_local_map_t gtt_mapping;

unsigned long mappable_base; /* PA of our GMADR */

struct drm_gem_object *scratch_page;

caddr_t virtual_gtt;

/* global gtt ops */

int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,

size_t *stolen);

void (*gtt_remove)(struct drm_device *dev);

void (*gtt_clear_range)(struct drm_device *dev,

struct drm_i915_gem_object *obj,

uint32_t type);

void (*gtt_insert_entries)(struct drm_i915_gem_object *obj,

enum i915_cache_level cache_level);

gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,

uint64_t addr,

enum i915_cache_level level);

};

#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)

#define I915_PPGTT_PD_ENTRIES 512

#define I915_PPGTT_PT_ENTRIES 1024

struct i915_hw_ppgtt {

struct drm_device *dev;

unsigned num_pd_entries;

pfn_t *pt_pages;

uint32_t pd_offset;

ddi_dma_handle_t dma_hdl;

ddi_acc_handle_t acc_hdl;

caddr_t kaddr;

size_t real_size; /* real size of memory */

uint64_t scratch_page_paddr;

/* pte functions, mirroring the interface of the global gtt. */

void (*clear_range)(struct i915_hw_ppgtt *ppgtt,

unsigned int first_entry,

unsigned int num_entries);

void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,

unsigned first_entry, unsigned num_entries,

pfn_t *pages, enum i915_cache_level cache_level);

gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,

uint64_t addr,

enum i915_cache_level level);

int (*enable)(struct drm_device *dev);

void (*cleanup)(struct i915_hw_ppgtt *ppgtt);

};

struct i915_ctx_hang_stats {

/* This context had batch pending when hang was declared */

unsigned batch_pending;

/* This context had batch active when hang was declared */

unsigned batch_active;

};

#define DEFAULT_CONTEXT_ID 0

struct i915_hw_context {

struct kref ref;

int id;

bool is_initialized;

struct drm_i915_file_private *file_priv;

struct intel_ring_buffer *ring;

struct drm_i915_gem_object *obj;

struct i915_ctx_hang_stats hang_stats;

};

enum no_fbc_reason {

FBC_NO_OUTPUT, /* no outputs enabled to compress */

FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */

FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */

FBC_MODE_TOO_LARGE, /* mode too large for compression */

FBC_BAD_PLANE, /* fbc not supported on plane */

FBC_NOT_TILED, /* buffer not tiled */

FBC_MULTIPLE_PIPES, /* more than one pipe active */

FBC_MODULE_PARAM,

};

enum intel_pch {

PCH_NONE = 0, /* No PCH present */

PCH_IBX, /* Ibexpeak PCH */

PCH_CPT, /* Cougarpoint PCH */

PCH_LPT, /* Lynxpoint PCH */

PCH_NOP,

};

enum intel_sbi_destination {

SBI_ICLK,

SBI_MPHY,

};

#define QUIRK_PIPEA_FORCE (1<<0)

#define QUIRK_LVDS_SSC_DISABLE (1<<1)

#define QUIRK_INVERT_BRIGHTNESS (1<<2)

#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)

struct intel_fbdev;

struct intel_fbc_work;

struct intel_gmbus {

struct i2c_adapter adapter;

bool force_bit;

u32 reg0;

u32 gpio_reg;

struct drm_i915_private *dev_priv;

};

typedef struct drm_i915_bridge_dev {

ldi_ident_t ldi_id;

ldi_handle_t bridge_dev_hdl;

} drm_i915_bridge_dev_t;

struct i915_suspend_saved_registers {

u8 saveLBB;

u32 saveDSPACNTR;

u32 saveDSPBCNTR;

u32 saveDSPARB;

u32 saveHWS;

u32 savePIPEACONF;

u32 savePIPEBCONF;

u32 savePIPEASRC;

u32 savePIPEBSRC;

u32 saveFPA0;

u32 saveFPA1;

u32 saveDPLL_A;

u32 saveDPLL_A_MD;

u32 saveHTOTAL_A;

u32 saveHBLANK_A;

u32 saveHSYNC_A;

u32 saveVTOTAL_A;

u32 saveVBLANK_A;

u32 saveVSYNC_A;

u32 saveBCLRPAT_A;

u32 saveTRANSACONF;

u32 saveTRANS_HTOTAL_A;

u32 saveTRANS_HBLANK_A;

u32 saveTRANS_HSYNC_A;

u32 saveTRANS_VTOTAL_A;

u32 saveTRANS_VBLANK_A;

u32 saveTRANS_VSYNC_A;

u32 savePIPEASTAT;

u32 saveDSPASTRIDE;

u32 saveDSPASIZE;

u32 saveDSPAPOS;

u32 saveDSPAADDR;

u32 saveDSPASURF;

u32 saveDSPATILEOFF;

u32 savePFIT_PGM_RATIOS;

u32 saveBLC_HIST_CTL;

u32 saveBLC_PWM_CTL;

u32 saveBLC_PWM_CTL2;

u32 saveBLC_CPU_PWM_CTL;

u32 saveBLC_CPU_PWM_CTL2;

u32 saveFPB0;

u32 saveFPB1;

u32 saveDPLL_B;

u32 saveDPLL_B_MD;

u32 saveHTOTAL_B;

u32 saveHBLANK_B;

u32 saveHSYNC_B;

u32 saveVTOTAL_B;

u32 saveVBLANK_B;

u32 saveVSYNC_B;

u32 saveBCLRPAT_B;

u32 saveTRANSBCONF;

u32 saveTRANS_HTOTAL_B;

u32 saveTRANS_HBLANK_B;

u32 saveTRANS_HSYNC_B;

u32 saveTRANS_VTOTAL_B;

u32 saveTRANS_VBLANK_B;

u32 saveTRANS_VSYNC_B;

u32 savePIPEBSTAT;

u32 saveDSPBSTRIDE;

u32 saveDSPBSIZE;

u32 saveDSPBPOS;

u32 saveDSPBADDR;

u32 saveDSPBSURF;

u32 saveDSPBTILEOFF;

u32 saveVGA0;

u32 saveVGA1;

u32 saveVGA_PD;

u32 saveVGACNTRL;

u32 saveADPA;

u32 saveLVDS;

u32 savePP_ON_DELAYS;

u32 savePP_OFF_DELAYS;

u32 saveDVOA;

u32 saveDVOB;

u32 saveDVOC;

u32 savePP_ON;

u32 savePP_OFF;

u32 savePP_CONTROL;

u32 savePP_DIVISOR;

u32 savePFIT_CONTROL;

u32 save_palette_a[256];

u32 save_palette_b[256];

u32 saveDPFC_CB_BASE;

u32 saveFBC_CFB_BASE;

u32 saveFBC_LL_BASE;

u32 saveFBC_CONTROL;

u32 saveFBC_CONTROL2;

u32 saveIER;

u32 saveIIR;

u32 saveIMR;

u32 saveDEIER;

u32 saveDEIMR;

u32 saveGTIER;

u32 saveGTIMR;

u32 saveFDI_RXA_IMR;

u32 saveFDI_RXB_IMR;

u32 saveCACHE_MODE_0;

u32 saveMI_ARB_STATE;

u32 saveSWF0[16];

u32 saveSWF1[16];

u32 saveSWF2[3];

u8 saveMSR;

u8 saveSR[8];

u8 saveGR[25];

u8 saveAR_INDEX;

u8 saveAR[21];

u8 saveDACMASK;

u8 saveCR[37];

uint64_t saveFENCE[I915_MAX_NUM_FENCES];

u32 saveCURACNTR;

u32 saveCURAPOS;

u32 saveCURABASE;

u32 saveCURBCNTR;

u32 saveCURBPOS;

u32 saveCURBBASE;

u32 saveCURSIZE;

u32 saveDP_B;

u32 saveDP_C;

u32 saveDP_D;

u32 savePIPEA_GMCH_DATA_M;

u32 savePIPEB_GMCH_DATA_M;

u32 savePIPEA_GMCH_DATA_N;

u32 savePIPEB_GMCH_DATA_N;

u32 savePIPEA_DP_LINK_M;

u32 savePIPEB_DP_LINK_M;

u32 savePIPEA_DP_LINK_N;

u32 savePIPEB_DP_LINK_N;

u32 saveFDI_RXA_CTL;

u32 saveFDI_TXA_CTL;

u32 saveFDI_RXB_CTL;

u32 saveFDI_TXB_CTL;

u32 savePFA_CTL_1;

u32 savePFB_CTL_1;

u32 savePFA_WIN_SZ;

u32 savePFB_WIN_SZ;

u32 savePFA_WIN_POS;

u32 savePFB_WIN_POS;

u32 savePCH_DREF_CONTROL;

u32 saveDISP_ARB_CTL;

u32 savePIPEA_DATA_M1;

u32 savePIPEA_DATA_N1;

u32 savePIPEA_LINK_M1;

u32 savePIPEA_LINK_N1;

u32 savePIPEB_DATA_M1;

u32 savePIPEB_DATA_N1;

u32 savePIPEB_LINK_M1;

u32 savePIPEB_LINK_N1;

u32 saveMCHBAR_RENDER_STANDBY;

u32 savePCH_PORT_HOTPLUG;

u32 pgtbl_ctl;

};

struct batch_info_list {

struct list_head head;

uint32_t num;

uint32_t seqno;

caddr_t *obj_list;

};

struct intel_gen6_power_mgmt {

struct work_struct work;

struct work_struct vlv_work;

struct timer_list vlv_timer;

u32 pm_iir;

/* lock - irqsave spinlock that protectects the work_struct and

spinlock_t lock;

/* The below variables an all the rps hw state are protected by

u8 cur_delay;

u8 min_delay;

u8 max_delay;

u8 rpe_delay;

u8 hw_max;

struct work_struct delayed_resume_work;

struct timer_list delayed_resume_timer;

/*

struct mutex hw_lock;

};

extern spinlock_t mchdev_lock;

struct intel_ilk_power_mgmt {

u8 cur_delay;

u8 min_delay;

u8 max_delay;

u8 fmax;

u8 fstart;

u64 last_count1;

unsigned long last_time1;

unsigned long chipset_power;

u64 last_count2;

clock_t last_time2;

unsigned long gfx_power;

u8 corr;

int c_m;

int r_t;

struct drm_i915_gem_object *pwrctx;

struct drm_i915_gem_object *renderctx;

};

struct i915_power_well {

struct drm_device *device;

spinlock_t lock;

/* power well enable/disable usage count */

int count;

int i915_request;

};

struct i915_dri1_state {

unsigned allow_batchbuffer : 1;

drm_local_map_t gfx_hws_cpu_addr;

unsigned int cpp;

int back_offset;

int front_offset;

int current_page;

int page_flipping;

uint32_t counter;

};

struct intel_l3_parity {

u32 *remap_info;

struct work_struct error_work;

};

struct i915_gem_mm {

/** Memory allocator for GTT stolen memory */

struct drm_mm stolen;

/** Memory allocator for GTT */

struct drm_mm gtt_space;

/** List of all objects in gtt_space. Used to restore gtt

struct list_head bound_list;

/**

struct list_head unbound_list;

/** Usable portion of the GTT for GEM */

unsigned long stolen_base; /* limited to low memory (32-bit) */

int gtt_mtrr;

/** PPGTT used for aliasing the PPGTT with the GTT */

struct i915_hw_ppgtt *aliasing_ppgtt;

/**

struct list_head active_list;

/**

struct list_head inactive_list;

/** LRU list of objects with fence regs on them. */

struct list_head fence_list;

/**

struct work_struct retire_work;

struct timer_list retire_timer;

/**

bool interruptible;

/**

int suspended;

/** Bit 6 swizzling required for X tiling */

uint32_t bit_6_swizzle_x;

/** Bit 6 swizzling required for Y tiling */

uint32_t bit_6_swizzle_y;

/* storage for physical objects */

struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];

/* accounting, useful for userland debugging */

size_t object_memory;

u32 object_count;

};

struct drm_i915_error_state_buf {

unsigned bytes;

unsigned size;

int err;

u8 *buf;

uint64_t start;

uint64_t pos;

};

struct i915_gpu_error {

/* For hangcheck timer */

#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */

#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)

struct timer_list hangcheck_timer;

/* For reset and error_state handling. */

spinlock_t lock;

/* Protected by the above dev->gpu_error.lock. */

struct drm_i915_error_state *first_error;

struct work_struct work;

unsigned long last_reset;

/**

atomic_t reset_counter;

/**

#define I915_RESET_IN_PROGRESS_FLAG 1

#define I915_WEDGED 0xffffffff

/**

wait_queue_head_t reset_queue;

/* For gpu hang simulation. */

unsigned int stop_rings;

};

enum modeset_restore {

MODESET_ON_LID_OPEN,

MODESET_DONE,

MODESET_SUSPENDED,

};

struct intel_vbt_data {

struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

/* Feature bits */

unsigned int int_tv_support:1;

unsigned int lvds_dither:1;

unsigned int lvds_vbt:1;

unsigned int int_crt_support:1;

unsigned int lvds_use_ssc:1;

unsigned int display_clock_mode:1;

unsigned int fdi_rx_polarity_inverted:1;

int lvds_ssc_freq;

unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

/* eDP */

int edp_rate;

int edp_lanes;

int edp_preemphasis;

int edp_vswing;

bool edp_initialized;

bool edp_support;

int edp_bpp;

struct edp_power_seq edp_pps;

int crt_ddc_pin;

int child_dev_num;

struct child_device_config *child_dev;

};

typedef struct drm_i915_private {

struct drm_device *dev;

const struct intel_device_info *info;

int relative_constants_mode;

drm_local_map_t *regs;

struct drm_i915_gt_funcs gt;

/** gt_fifo_count and the subsequent register write are synchronized

unsigned gt_fifo_count;

/** forcewake_count is protected by gt_lock */

unsigned forcewake_count;

/** gt_lock is also taken in irq contexts. */

spinlock_t gt_lock;

struct intel_gmbus gmbus[GMBUS_NUM_PORTS];

/** gmbus_mutex protects against concurrent usage of the single hw gmbus

struct mutex gmbus_mutex;

/**

uint32_t gpio_mmio_base;

wait_queue_head_t gmbus_wait_queue;

struct drm_i915_bridge_dev bridge_dev;

struct intel_ring_buffer ring[I915_NUM_RINGS];

uint32_t last_seqno, next_seqno;

drm_dma_handle_t *status_page_dmah;

uint32_t counter;

atomic_t irq_received;

u32 trace_irq_seqno;

/* protects the irq masks */

spinlock_t irq_lock;

/* DPIO indirect register protection */

spinlock_t dpio_lock;

/** Cached value of IMR to avoid reads in updating the bitfield */

u32 irq_mask;

u32 gt_irq_mask;

struct work_struct hotplug_work;

bool enable_hotplug_processing;

struct {

unsigned long hpd_last_jiffies;

int hpd_cnt;

enum {

HPD_ENABLED = 0,

HPD_DISABLED = 1,

HPD_MARK_DISABLED = 2

} hpd_mark;

} hpd_stats[HPD_NUM_PINS];

u32 hpd_event_bits;

struct timer_list hotplug_reenable_timer;

int num_plane;

unsigned long cfb_size;

unsigned int cfb_fb;

enum plane cfb_plane;

int cfb_y;

struct intel_fbc_work *fbc_work;

struct timer_list fbc_timer;

struct intel_opregion opregion;

struct intel_vbt_data vbt;

/* overlay */

struct intel_overlay *overlay;

unsigned int sprite_scaling_enabled;

/* backlight */

struct {

int level;

bool enabled;

spinlock_t lock; /* bl registers and the above bl fields */

struct backlight_device *device;

} backlight;

/* LVDS info */

struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

bool no_aux_handshake;

struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */

int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */

int num_fence_regs; /* 8 on pre-965, 16 otherwise */

unsigned int fsb_freq, mem_freq, is_ddr3;

struct workqueue_struct *wq;

struct workqueue_struct *other_wq;

/* Display functions */

struct drm_i915_display_funcs display;

/* PCH chipset type */

enum intel_pch pch_type;

unsigned short pch_id;

unsigned long quirks;

bool vt_holding;

bool isX;

bool gfx_state_saved;

/* Register state */

enum modeset_restore modeset_restore;

struct mutex modeset_restore_lock;

struct i915_gtt gtt;

struct i915_gem_mm mm;

/* Kernel Modesetting */

struct sdvo_device_mapping sdvo_mappings[2];

struct drm_crtc *plane_to_crtc_mapping[3];

struct drm_crtc *pipe_to_crtc_mapping[3];

wait_queue_head_t pending_flip_queue;

int num_shared_dpll;

struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

struct intel_ddi_plls ddi_plls;

/* Reclocking support */

bool render_reclock_avail;

bool lvds_downclock_avail;

/* indicates the reduced downclock for LVDS*/

int lvds_downclock;

u16 orig_clock;

bool mchbar_need_disable;

struct intel_l3_parity l3_parity;

/* gen6+ rps state */

struct intel_gen6_power_mgmt rps;

/* ilk-only ips/rps state. Everything in here is protected by the global

struct intel_ilk_power_mgmt ips;

/* Haswell power well */

struct i915_power_well power_well;

enum no_fbc_reason no_fbc_reason;

struct drm_mm_node *compressed_fb;

struct drm_mm_node *compressed_llb;

struct timer_list gpu_top_timer;

struct i915_gpu_error gpu_error;

int gpu_hang;

struct drm_i915_gem_object *vlv_pctx;

/* list of fbdev register on this device */

struct intel_fbdev *fbdev;

struct drm_property *broadcast_rgb_property;

struct drm_property *force_audio_property;

bool hw_contexts_disabled;

uint32_t hw_context_size;

u32 fdi_rx_config;

struct i915_suspend_saved_registers regfile;

struct drm_i915_gem_object *fbcon_obj;

/* Old dri1 support infrastructure, beware the dragons ya fools entering

struct i915_dri1_state dri1;

struct list_head batch_list;

} drm_i915_private_t;

#define for_each_ring(ring__, dev_priv__, i__) \

for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \

if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

enum hdmi_force_audio {

HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */

HDMI_AUDIO_OFF, /* force turn off HDMI audio */

HDMI_AUDIO_AUTO, /* trust EDID */

HDMI_AUDIO_ON, /* force turn on HDMI audio */

};

#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)

struct drm_i915_gem_object_ops {

/* Interface between the GEM object and its backing storage.

int (*get_pages)(struct drm_i915_gem_object *);

void (*put_pages)(struct drm_i915_gem_object *);

};

struct drm_i915_gem_object {

struct drm_gem_object base;

const struct drm_i915_gem_object_ops *ops;

/** Current space allocated to this object in the GTT, if any. */

struct drm_mm_node *gtt_space;

/** Stolen memory for this object, instead of being backed by shmem. */

struct drm_mm_node *stolen;

struct list_head global_list;

/** This object's place on the active/flushing/inactive lists */

struct list_head ring_list;

struct list_head mm_list;

/** This object's place on eviction list */

struct list_head exec_list;

/**

unsigned int active;

/**

unsigned int dirty;

/**

signed int fence_reg;

/**

unsigned int madv;

/**

unsigned int tiling_mode : 2;

/**

unsigned int fence_dirty:1;

/** How many users have pinned this object in GTT space. The following

unsigned int pin_count;

#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf

/**

unsigned int map_and_fenceable;

int agp_mem;

/**

unsigned int fault_mappable;

unsigned int pin_mappable;

/*

unsigned int pending_fenced_gpu_access;

unsigned int fenced_gpu_access;

unsigned int cache_level;

unsigned int has_aliasing_ppgtt_mapping;

unsigned int has_global_gtt_mapping;

unsigned int has_dma_mapping;

caddr_t *page_list;

int pages_pin_count;

/**

struct scatterlist *sg_list;

int num_sg;

/**

unsigned long exec_handle;

struct drm_i915_gem_exec_object2 *exec_entry;

/**

uint32_t gtt_offset;

struct intel_ring_buffer *ring;

/**

uint64_t mmap_offset;

/** Breadcrumb of last rendering to the buffer. */

uint32_t last_read_seqno;

uint32_t last_write_seqno;

/** Breadcrumb of last fenced GPU access to the buffer. */

uint32_t last_fenced_seqno;

/** Current tiling mode for the object. */

uint32_t stride;

/** Record of address bit 17 of each page at last unbind. */

unsigned long *bit_17;

/** User space pin count and filp owning the pin */

uint32_t user_pin_count;

struct drm_file *pin_filp;

/** for phy allocated objects */