1450N/A * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 1450N/A * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 1450N/A * Copyright (c) 2009, 2013, Intel Corporation. 1450N/A * Permission is hereby granted, free of charge, to any person obtaining a 1450N/A * copy of this software and associated documentation files (the 1450N/A * "Software"), to deal in the Software without restriction, including 1450N/A * without limitation the rights to use, copy, modify, merge, publish, 1450N/A * distribute, sub license, and/or sell copies of the Software, and to 1450N/A * permit persons to whom the Software is furnished to do so, subject to 1450N/A * the following conditions: 1450N/A * The above copyright notice and this permission notice (including the 1450N/A * next paragraph) shall be included in all copies or substantial portions 1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1450N/A * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1450N/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 1450N/A * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 1450N/A * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 1450N/A * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 1450N/A * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 1450N/A/* Please note that modifications to all structs defined here are 1450N/A * subject to backwards-compatibility constraints. 1450N/A/* Each region is a minimum of 16k, and there are at most 255 of them. 1450N/A /* fill out some space for old userspace triple buffer */ 1450N/A /* buffer object handles for static buffers. May change 1450N/A * over the lifetime of the client. 1450N/A/* due to userspace building against these headers we need some compat here */ 1450N/A * The device specific ioctl range is 0x40 to 0x79. 1450N/A/* Allow drivers to submit batchbuffers directly to hardware, relying 1450N/A * on the security mechanisms provided by hardware. 1450N/A int DR1;
/* hw flags for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR4;
/* window origin for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR1;
/* hw flags for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR4;
/* window origin for GFX_OP_DRAWRECT_INFO */ 1450N/A/* As above, but pass a pointer to userspace buffer which can be 1450N/A * validated by the kernel prior to sending to hardware. 1450N/A int DR1;
/* hw flags for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR4;
/* window origin for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR1;
/* hw flags for GFX_OP_DRAWRECT_INFO */ 1450N/A int DR4;
/* window origin for GFX_OP_DRAWRECT_INFO */ 1450N/A/* Userspace can request & wait on irq's: 1450N/A/* Ioctl to query kernel params: 1450N/A/* Ioctl to set kernel params: 1450N/A/* A memory manager for regions of shared memory: 1450N/A/* Allow memory manager to be torn down and re-initialized (eg on 1450N/A/* Allow X server to configure which pipes to monitor for vblank signals 1450N/A/* Schedule buffer swap at given vertical blank: 1450N/A * Beginning offset in the GTT to be managed by the DRM memory 1450N/A * Ending offset in the GTT to be managed by the DRM memory 1450N/A * Requested size for the object. 1450N/A * The (page-aligned) allocated size for the object will be returned. 1450N/A * Returned handle for the object. 1450N/A * Object handles are nonzero. 1450N/A /** Handle for the object being read. */ 1450N/A /** Offset into the object to read from */ 1450N/A /** Length of data to read */ 1450N/A * Pointer to write the data into. 1450N/A * This is a fixed-size type for 32/64 compatibility. 1450N/A /** Handle for the object being written to. */ 1450N/A /** Offset into the object to write to */ 1450N/A /** Length of data to write */ 1450N/A * Pointer to read the data from. 1450N/A * This is a fixed-size type for 32/64 compatibility. 1450N/A /** Handle for the object being mapped. */ 1450N/A /** Offset in the object to map. */ 1450N/A * The value will be page-aligned. 1450N/A * Returned pointer the data was mapped at. 1450N/A * This is a fixed-size type for 32/64 compatibility. 1450N/A /** Handle for the object being mapped. */ 1450N/A * Fake offset to use for subsequent mmap call 1450N/A * This is a fixed-size type for 32/64 compatibility. 1450N/A /** Handle for the object */ 1450N/A /** Handle for the object */ 1450N/A * Handle of the buffer being pointed to by this relocation entry. 1450N/A * It's appealing to make this be an index into the mm_validate_entry 1450N/A * list to refer to the buffer, but this allows the driver to create 1450N/A * a relocation list for state buffers and not re-write it per 1450N/A * Value to be added to the offset of the target buffer to make up 1450N/A /** Offset in the buffer the relocation entry will be written into */ 1450N/A * Offset value of the target buffer that the relocation entry was last 1450N/A * If the buffer has the same offset as last time, we can skip syncing 1450N/A * and writing the relocation. This value is written back out by 1450N/A * the execbuffer ioctl when the relocation is written. 1450N/A * Target memory domains read by this operation. 1450N/A * Target memory domains written by this operation. 1450N/A * Note that only one domain may be written by the whole 1450N/A * execbuffer operation, so that where there are conflicts, 1450N/A * the application will get -EINVAL back. 1450N/A * Most of these just align with the various caches in 1450N/A * the system and are used to flush and invalidate as 1450N/A * objects end up cached in different domains. 1450N/A/** Render cache, used by 2D and 3D drawing */ 1450N/A/** Sampler cache, used by texture engine */ 1450N/A/** Command queue, used to load batch buffers */ 1450N/A/** Instruction cache, used by shader programs */ 1450N/A/** GTT domain - aperture and scanout */ 1450N/A * User's handle for a buffer to be bound into the GTT for this 1450N/A /** Number of relocations to be performed on this buffer */ 1450N/A * Pointer to array of struct drm_i915_gem_relocation_entry containing 1450N/A * the relocations to be performed in this buffer. 1450N/A /** Required alignment in graphics aperture */ 1450N/A * Returned value of the updated offset of the object, for future 1450N/A * List of buffers to be validated with their relocations to be 1450N/A * This is a pointer to an array of struct drm_i915_gem_validate_entry. 1450N/A * These buffers must be listed in an order such that all relocations 1450N/A * a buffer is performing refer to buffers that have already appeared 1450N/A /** Offset in the batchbuffer to start execution from. */ 1450N/A /** Bytes used in batchbuffer from batch_start_offset */ 1450N/A /** This is a struct drm_clip_rect *cliprects */ 1450N/A * User's handle for a buffer to be bound into the GTT for this 1450N/A /** Number of relocations to be performed on this buffer */ 1450N/A * Pointer to array of struct drm_i915_gem_relocation_entry containing 1450N/A * the relocations to be performed in this buffer. 1450N/A /** Required alignment in graphics aperture */ 1450N/A * Returned value of the updated offset of the object, for future 1450N/A * List of gem_exec_object2 structs 1450N/A /** Offset in the batchbuffer to start execution from. */ 1450N/A /** Bytes used in batchbuffer from batch_start_offset */ 1450N/A /** This is a struct drm_clip_rect *cliprects */ 1450N/A/* Used for switching the constants addressing mode on gen4+ RENDER ring. 1450N/A * Gen6+ only supports relative addressing to dynamic state (default) and 1450N/A * These flags are ignored for the BSD and BLT rings. 1450N/A/** Resets the SO write offset registers for transform feedback on gen7. */ 1450N/A/** Request a privileged ("secure") batch buffer. Note only available for 1450N/A * DRM_ROOT_ONLY | DRM_MASTER processes. 1450N/A/** Inform the kernel that the batch is and will always be pinned. This 1450N/A * negates the requirement for a workaround to be performed to avoid 1450N/A * an incoherent CS (such as can be found on 830/845). If this flag is 1450N/A * not passed, the kernel will endeavour to make sure the batch is 1450N/A * coherent with the CS before execution. If this flag is passed, 1450N/A * userspace assumes the responsibility for ensuring the same. 1450N/A/** Provide a hint to the kernel that the command stream and auxilliary 1450N/A * state buffers already holds the correct presumed addresses and so the 1450N/A * relocation process may be skipped if no buffers need to be moved in 1450N/A * preparation for the execbuffer. 1450N/A/** Use the reloc.handle as an index into the exec object array rather 1450N/A * than as the per-file handle. 1450N/A /** Handle of the buffer to be pinned. */ 1450N/A /** alignment required within the aperture */ 1450N/A /** Returned GTT offset of the buffer. */ 1450N/A /** Handle of the buffer to be unpinned. */ 1450N/A /** Handle of the buffer to check for busy */ 1450N/A /** Return busy status (1 if busy, 0 if idle). 1450N/A * The high word is used to indicate on which rings the object 1450N/A * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 1450N/A * Handle of the buffer to set/get the caching level of. */ 1450N/A * Cacheing level to apply or return value 1450N/A * bits0-15 are for generic caching control (i.e. the above defined 1450N/A * values). bits16-31 are reserved for platform-specific variations 1450N/A * (e.g. l3$ caching on gen7). */ 1450N/A /** Handle of the buffer to have its tiling state updated */ 1450N/A * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1450N/A * This value is to be set on request, and will be updated by the 1450N/A * kernel on successful return with the actual chosen tiling layout. 1450N/A * The tiling mode may be demoted to I915_TILING_NONE when the system 1450N/A * has bit 6 swizzling that can't be managed correctly by GEM. 1450N/A * Buffer contents become undefined when changing tiling_mode. 1450N/A * Stride in bytes for the object when in I915_TILING_X or 1450N/A * Returned address bit 6 swizzling required for CPU access through 1450N/A /** Handle of the buffer to get tiling state for. */ 1450N/A * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1450N/A * Returned address bit 6 swizzling required for CPU access through 1450N/A /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1450N/A * Available space in the aperture used by i915_gem_execbuffer, in 1450N/A /** ID of CRTC being requested **/ 1450N/A /** pipe of requested CRTC **/ 1450N/A /** Handle of the buffer to change the backing store advice */ 1450N/A /* Advice: either the buffer will be needed again in the near future, 1450N/A * or wont be and could be discarded under memory pressure. 1450N/A /** Whether the backing store still exists. */ 1450N/A /* various flags and src format description */ 1450N/A /* source picture description */ 1450N/A /* stride values and offsets are in bytes, buffer relative */ 1450N/A /* to compensate the scaling factors for partially covered surfaces */ 1450N/A /* output crtc description */ 1450N/A * Sprite pixels within the min & max values, masked against the color channels 1450N/A * specified in the mask field, will be transparent. All other pixels will 1450N/A * be displayed on top of the primary plane. For RGB surfaces, only the min 1450N/A * and mask fields will be used; ranged compares are not allowed. 1450N/A * Primary plane pixels that match the min value, masked against the color 1450N/A * channels specified in the mask field, will be replaced by corresponding 1450N/A * pixels from the sprite plane. 1450N/A * Note that source & destination keying are exclusive; only one can be 1450N/A /** Handle of BO we shall wait on */ 1450N/A /** Number of nanoseconds to wait, Returns time remaining. */ 1450N/A /* output: id of new context*/