drm.h revision 1450
1450N/A/*
1450N/A * Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/**
1450N/A * \file drm.h
1450N/A * Header for the Direct Rendering Manager
1450N/A *
1450N/A * \author Rickard E. (Rik) Faith <faith@valinux.com>
1450N/A *
1450N/A * \par Acknowledgments:
1450N/A * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
1450N/A */
1450N/A
1450N/A/*
1450N/A * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
1450N/A * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
1450N/A * Copyright (c) 2009, Intel Corporation.
1450N/A * All rights reserved.
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
1450N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1450N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1450N/A * OTHER DEALINGS IN THE SOFTWARE.
1450N/A */
1450N/A
1450N/A#ifndef _DRM_H_
1450N/A#define _DRM_H_
1450N/A
1450N/A#include <sys/types32.h>
1450N/A
1450N/A#ifndef __user
1450N/A#define __user
1450N/A#endif
1450N/A
1450N/A#ifdef __GNUC__
1450N/A# define DEPRECATED __attribute__ ((deprecated))
1450N/A#else
1450N/A# define DEPRECATED
1450N/A# define __volatile__ volatile
1450N/A#endif
1450N/A
1450N/Atypedef int8_t __s8;
1450N/Atypedef uint8_t __u8;
1450N/Atypedef int16_t __s16;
1450N/Atypedef uint16_t __u16;
1450N/Atypedef int32_t __s32;
1450N/Atypedef uint32_t __u32;
1450N/Atypedef int64_t __s64;
1450N/Atypedef uint64_t __u64;
1450N/A
1450N/A/* Solaris-specific. */
1450N/A#if defined(__SOLARIS__) || defined(sun)
1450N/A#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
1450N/A
1450N/A#define _IOC_NRBITS 8
1450N/A#define _IOC_TYPEBITS 8
1450N/A#define _IOC_SIZEBITS 14
1450N/A#define _IOC_DIRBITS 2
1450N/A
1450N/A#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
1450N/A#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
1450N/A#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
1450N/A#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
1450N/A
1450N/A#define _IOC_NRSHIFT 0
1450N/A#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
1450N/A#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
1450N/A#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
1450N/A
1450N/A#define _IOC_NONE 0U
1450N/A#define _IOC_WRITE 1U
1450N/A#define _IOC_READ 2U
1450N/A
1450N/A#define _IOC(dir, type, nr, size) \
1450N/A (((dir) << _IOC_DIRSHIFT) | \
1450N/A ((type) << _IOC_TYPESHIFT) | \
1450N/A ((nr) << _IOC_NRSHIFT) | \
1450N/A ((size) << _IOC_SIZESHIFT))
1450N/A
1450N/A/* used for X server compile */
1450N/A#if !defined(_KERNEL)
1450N/A#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
1450N/A#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof (size))
1450N/A#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof (size))
1450N/A#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, \
1450N/A (type), (nr), sizeof (size))
1450N/A
1450N/A#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
1450N/A#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
1450N/A#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
1450N/A
1450N/A#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
1450N/A#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
1450N/A#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
1450N/A#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
1450N/A#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
1450N/A#endif /* _KERNEL */
1450N/A
1450N/A#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
1450N/A
1450N/A#define DRM_IOCTL_NR(n) _IOC_NR(n)
1450N/A#define DRM_IOC_VOID IOC_VOID
1450N/A#define DRM_IOC_READ IOC_OUT
1450N/A#define DRM_IOC_WRITE IOC_IN
1450N/A#define DRM_IOC_READWRITE IOC_INOUT
1450N/A#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
1450N/A
1450N/A#endif /* __Solaris__ or sun */
1450N/A#define XFREE86_VERSION(major,minor,patch,snap) \
1450N/A ((major << 16) | (minor << 8) | patch)
1450N/A
1450N/A#ifndef CONFIG_XFREE86_VERSION
1450N/A#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
1450N/A#endif
1450N/A
1450N/A#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
1450N/A#define DRM_PROC_DEVICES "/proc/devices"
1450N/A#define DRM_PROC_MISC "/proc/misc"
1450N/A#define DRM_PROC_DRM "/proc/drm"
1450N/A#define DRM_DEV_DRM "/dev/drm"
1450N/A#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
1450N/A#define DRM_DEV_UID 0
1450N/A#define DRM_DEV_GID 0
1450N/A#endif
1450N/A
1450N/A#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
1450N/A#ifdef __OpenBSD__
1450N/A#define DRM_MAJOR 81
1450N/A#endif
1450N/A#if defined(__linux__) || defined(__NetBSD__)
1450N/A#define DRM_MAJOR 226
1450N/A#endif
1450N/A#define DRM_MAX_MINOR 15
1450N/A#endif
1450N/A#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
1450N/A#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
1450N/A#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
1450N/A#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
1450N/A
1450N/A#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
1450N/A#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
1450N/A#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
1450N/A#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
1450N/A#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
1450N/A
1450N/A#if defined(__linux__)
1450N/A#if defined(__KERNEL__)
1450N/Atypedef __u64 drm_u64_t;
1450N/A#else
1450N/Atypedef unsigned long long drm_u64_t;
1450N/A#endif
1450N/A
1450N/Atypedef unsigned int drm_handle_t;
1450N/A#else
1450N/A#include <sys/types.h>
1450N/Atypedef uint64_t drm_u64_t;
1450N/Atypedef unsigned long long drm_handle_t; /**< To mapped regions */
1450N/A#endif
1450N/Atypedef unsigned int drm_context_t;
1450N/Atypedef unsigned int drm_drawable_t;
1450N/Atypedef unsigned int drm_magic_t;
1450N/A
1450N/A/**
1450N/A * Cliprect.
1450N/A *
1450N/A * \warning: If you change this structure, make sure you change
1450N/A * XF86DRIClipRectRec in the server as well
1450N/A *
1450N/A * \note KW: Actually it's illegal to change either for
1450N/A * backwards-compatibility reasons.
1450N/A */
1450N/Astruct drm_clip_rect {
1450N/A unsigned short x1;
1450N/A unsigned short y1;
1450N/A unsigned short x2;
1450N/A unsigned short y2;
1450N/A};
1450N/A
1450N/A/**
1450N/A * Drawable information.
1450N/A */
1450N/Astruct drm_drawable_info {
1450N/A unsigned int num_rects;
1450N/A struct drm_clip_rect *rects;
1450N/A};
1450N/A
1450N/A/**
1450N/A * Texture region,
1450N/A */
1450N/Astruct drm_tex_region {
1450N/A unsigned char next;
1450N/A unsigned char prev;
1450N/A unsigned char in_use;
1450N/A unsigned char padding;
1450N/A unsigned int age;
1450N/A};
1450N/A
1450N/A/**
1450N/A * Hardware lock.
1450N/A *
1450N/A * The lock structure is a simple cache-line aligned integer. To avoid
1450N/A * processor bus contention on a multiprocessor system, there should not be any
1450N/A * other data stored in the same cache line.
1450N/A */
1450N/Astruct drm_hw_lock {
1450N/A __volatile__ unsigned int lock; /**< lock variable */
1450N/A char padding[60]; /**< Pad to cache line */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_VERSION ioctl argument type.
1450N/A *
1450N/A * \sa drmGetVersion().
1450N/A */
1450N/Astruct drm_version {
1450N/A int version_major; /**< Major version */
1450N/A int version_minor; /**< Minor version */
1450N/A int version_patchlevel; /**< Patch level */
1450N/A size_t name_len; /**< Length of name buffer */
1450N/A char __user *name; /**< Name of driver */
1450N/A size_t date_len; /**< Length of date buffer */
1450N/A char __user *date; /**< User-space buffer to hold date */
1450N/A size_t desc_len; /**< Length of desc buffer */
1450N/A char __user *desc; /**< User-space buffer to hold desc */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_GET_UNIQUE ioctl argument type.
1450N/A *
1450N/A * \sa drmGetBusid() and drmSetBusId().
1450N/A */
1450N/Astruct drm_unique {
1450N/A size_t unique_len; /**< Length of unique */
1450N/A char __user *unique; /**< Unique name for driver instantiation */
1450N/A};
1450N/A
1450N/Astruct drm_list {
1450N/A int count; /**< Length of user-space structures */
1450N/A struct drm_version __user *version;
1450N/A};
1450N/A
1450N/Astruct drm_block {
1450N/A int unused;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_CONTROL ioctl argument type.
1450N/A *
1450N/A * \sa drmCtlInstHandler() and drmCtlUninstHandler().
1450N/A */
1450N/Astruct drm_control {
1450N/A enum {
1450N/A DRM_ADD_COMMAND,
1450N/A DRM_RM_COMMAND,
1450N/A DRM_INST_HANDLER,
1450N/A DRM_UNINST_HANDLER
1450N/A } func;
1450N/A int irq;
1450N/A};
1450N/A
1450N/A/**
1450N/A * Type of memory to map.
1450N/A */
1450N/Aenum drm_map_type {
1450N/A _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
1450N/A _DRM_REGISTERS = 1, /**< no caching, no core dump */
1450N/A _DRM_SHM = 2, /**< shared, cached */
1450N/A _DRM_AGP = 3, /**< AGP/GART */
1450N/A _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
1450N/A _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
1450N/A _DRM_GEM = 6, /**< GEM object */
1450N/A};
1450N/A
1450N/A/**
1450N/A * Memory mapping flags.
1450N/A */
1450N/Aenum drm_map_flags {
1450N/A _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
1450N/A _DRM_READ_ONLY = 0x02,
1450N/A _DRM_LOCKED = 0x04, /**< shared, cached, locked */
1450N/A _DRM_KERNEL = 0x08, /**< kernel requires access */
1450N/A _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
1450N/A _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
1450N/A _DRM_REMOVABLE = 0x40, /**< Removable mapping */
1450N/A _DRM_DRIVER = 0x80 /**< Managed by driver */
1450N/A};
1450N/A
1450N/Astruct drm_ctx_priv_map {
1450N/A unsigned int ctx_id; /**< Context requesting private mapping */
1450N/A void *handle; /**< Handle of map */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
1450N/A * argument type.
1450N/A *
1450N/A * \sa drmAddMap().
1450N/A */
1450N/Astruct drm_map {
1450N/A unsigned long long offset; /**< Requested physical address (0 for SAREA)*/
1450N/A unsigned long long handle;
1450N/A /**< User-space: "Handle" to pass to mmap() */
1450N/A /**< Kernel-space: kernel-virtual address */
1450N/A unsigned long size; /**< Requested physical size (bytes) */
1450N/A enum drm_map_type type; /**< Type of memory to map */
1450N/A enum drm_map_flags flags; /**< Flags */
1450N/A int mtrr; /**< MTRR slot used */
1450N/A /* Private data */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_GET_CLIENT ioctl argument type.
1450N/A */
1450N/Astruct drm_client {
1450N/A int idx; /**< Which client desired? */
1450N/A int auth; /**< Is client authenticated? */
1450N/A unsigned long pid; /**< Process ID */
1450N/A unsigned long uid; /**< User ID */
1450N/A unsigned long magic; /**< Magic */
1450N/A unsigned long iocs; /**< Ioctl count */
1450N/A};
1450N/A
1450N/Aenum drm_stat_type {
1450N/A _DRM_STAT_LOCK,
1450N/A _DRM_STAT_OPENS,
1450N/A _DRM_STAT_CLOSES,
1450N/A _DRM_STAT_IOCTLS,
1450N/A _DRM_STAT_LOCKS,
1450N/A _DRM_STAT_UNLOCKS,
1450N/A _DRM_STAT_VALUE, /**< Generic value */
1450N/A _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
1450N/A _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
1450N/A
1450N/A _DRM_STAT_IRQ, /**< IRQ */
1450N/A _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
1450N/A _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
1450N/A _DRM_STAT_DMA, /**< DMA */
1450N/A _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
1450N/A _DRM_STAT_MISSED /**< Missed DMA opportunity */
1450N/A /* Add to the *END* of the list */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_GET_STATS ioctl argument type.
1450N/A */
1450N/Astruct drm_stats {
1450N/A unsigned long count;
1450N/A struct {
1450N/A unsigned long value;
1450N/A enum drm_stat_type type;
1450N/A } data[15];
1450N/A};
1450N/A
1450N/A/**
1450N/A * Hardware locking flags.
1450N/A */
1450N/Aenum drm_lock_flags {
1450N/A _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
1450N/A _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
1450N/A _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
1450N/A _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
1450N/A /* These *HALT* flags aren't supported yet
1450N/A -- they will be used to support the
1450N/A full-screen DGA-like mode. */
1450N/A _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
1450N/A _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
1450N/A *
1450N/A * \sa drmGetLock() and drmUnlock().
1450N/A */
1450N/Astruct drm_lock {
1450N/A int context;
1450N/A enum drm_lock_flags flags;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DMA flags
1450N/A *
1450N/A * \warning
1450N/A * These values \e must match xf86drm.h.
1450N/A *
1450N/A * \sa drm_dma.
1450N/A */
1450N/Aenum drm_dma_flags {
1450N/A /* Flags for DMA buffer dispatch */
1450N/A _DRM_DMA_BLOCK = 0x01, /**<
1450N/A * Block until buffer dispatched.
1450N/A *
1450N/A * \note The buffer may not yet have
1450N/A * been processed by the hardware --
1450N/A * getting a hardware lock with the
1450N/A * hardware quiescent will ensure
1450N/A * that the buffer has been
1450N/A * processed.
1450N/A */
1450N/A _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
1450N/A _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
1450N/A
1450N/A /* Flags for DMA buffer request */
1450N/A _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
1450N/A _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
1450N/A _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
1450N/A *
1450N/A * \sa drmAddBufs().
1450N/A */
1450N/Aenum drm_buf_flag {
1450N/A _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
1450N/A _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
1450N/A _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
1450N/A _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
1450N/A _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
1450N/A};
1450N/Astruct drm_buf_desc {
1450N/A int count; /**< Number of buffers of this size */
1450N/A int size; /**< Size in bytes */
1450N/A int low_mark; /**< Low water mark */
1450N/A int high_mark; /**< High water mark */
1450N/A enum drm_buf_flag flags;
1450N/A unsigned long agp_start; /**<
1450N/A * Start address of where the AGP buffers are
1450N/A * in the AGP aperture
1450N/A */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_INFO_BUFS ioctl argument type.
1450N/A */
1450N/Astruct drm_buf_info {
1450N/A int count; /**< Entries in list */
1450N/A struct drm_buf_desc __user *list;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_FREE_BUFS ioctl argument type.
1450N/A */
1450N/Astruct drm_buf_free {
1450N/A int count;
1450N/A int __user *list;
1450N/A};
1450N/A
1450N/A/**
1450N/A * Buffer information
1450N/A *
1450N/A * \sa drm_buf_map.
1450N/A */
1450N/Astruct drm_buf_pub {
1450N/A int idx; /**< Index into the master buffer list */
1450N/A int total; /**< Buffer size */
1450N/A int used; /**< Amount of buffer in use (for DMA) */
1450N/A void __user *address; /**< Address of buffer */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_MAP_BUFS ioctl argument type.
1450N/A */
1450N/Astruct drm_buf_map {
1450N/A int count; /**< Length of the buffer list */
1450N/A#if defined(__cplusplus)
1450N/A void __user *c_virtual;
1450N/A#else
1450N/A void __user *virtual; /**< Mmap'd area in user-virtual */
1450N/A#endif
1450N/A struct drm_buf_pub __user *list; /**< Buffer information */
1450N/A int fd;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_DMA ioctl argument type.
1450N/A *
1450N/A * Indices here refer to the offset into the buffer list in drm_buf_get.
1450N/A *
1450N/A * \sa drmDMA().
1450N/A */
1450N/Astruct drm_dma {
1450N/A int context; /**< Context handle */
1450N/A int send_count; /**< Number of buffers to send */
1450N/A int __user *send_indices; /**< List of handles to buffers */
1450N/A int __user *send_sizes; /**< Lengths of data to send */
1450N/A enum drm_dma_flags flags; /**< Flags */
1450N/A int request_count; /**< Number of buffers requested */
1450N/A int request_size; /**< Desired size for buffers */
1450N/A int __user *request_indices; /**< Buffer information */
1450N/A int __user *request_sizes;
1450N/A int granted_count; /**< Number of buffers granted */
1450N/A};
1450N/A
1450N/Aenum drm_ctx_flags {
1450N/A _DRM_CONTEXT_PRESERVED = 0x01,
1450N/A _DRM_CONTEXT_2DONLY = 0x02
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_ADD_CTX ioctl argument type.
1450N/A *
1450N/A * \sa drmCreateContext() and drmDestroyContext().
1450N/A */
1450N/Astruct drm_ctx {
1450N/A drm_context_t handle;
1450N/A enum drm_ctx_flags flags;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_RES_CTX ioctl argument type.
1450N/A */
1450N/Astruct drm_ctx_res {
1450N/A int count;
1450N/A struct drm_ctx __user *contexts;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
1450N/A */
1450N/Astruct drm_draw {
1450N/A drm_drawable_t handle;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
1450N/A */
1450N/Atypedef enum {
1450N/A DRM_DRAWABLE_CLIPRECTS,
1450N/A} drm_drawable_info_type_t;
1450N/A
1450N/Astruct drm_update_draw {
1450N/A drm_drawable_t handle;
1450N/A unsigned int type;
1450N/A unsigned int num;
1450N/A unsigned long long data;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
1450N/A */
1450N/Astruct drm_auth {
1450N/A drm_magic_t magic;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_IRQ_BUSID ioctl argument type.
1450N/A *
1450N/A * \sa drmGetInterruptFromBusID().
1450N/A */
1450N/Astruct drm_irq_busid {
1450N/A int irq; /**< IRQ number */
1450N/A int busnum; /**< bus number */
1450N/A int devnum; /**< device number */
1450N/A int funcnum; /**< function number */
1450N/A};
1450N/A
1450N/Aenum drm_vblank_seq_type {
1450N/A _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
1450N/A _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
1450N/A /* bits 1-6 are reserved for high crtcs */
1450N/A _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
1450N/A _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
1450N/A _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
1450N/A _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
1450N/A _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
1450N/A _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
1450N/A};
1450N/A#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
1450N/A
1450N/A#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
1450N/A#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
1450N/A _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
1450N/A
1450N/Astruct drm_wait_vblank_request {
1450N/A enum drm_vblank_seq_type type;
1450N/A unsigned int sequence;
1450N/A unsigned long signal;
1450N/A};
1450N/A
1450N/Astruct drm_wait_vblank_reply {
1450N/A enum drm_vblank_seq_type type;
1450N/A unsigned int sequence;
1450N/A long tval_sec;
1450N/A long tval_usec;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
1450N/A *
1450N/A * \sa drmWaitVBlank().
1450N/A */
1450N/Aunion drm_wait_vblank {
1450N/A struct drm_wait_vblank_request request;
1450N/A struct drm_wait_vblank_reply reply;
1450N/A};
1450N/A
1450N/A#define _DRM_PRE_MODESET 1
1450N/A#define _DRM_POST_MODESET 2
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_MODESET_CTL ioctl argument type
1450N/A *
1450N/A * \sa drmModesetCtl().
1450N/A */
1450N/Astruct drm_modeset_ctl {
1450N/A __u32 crtc;
1450N/A __u32 cmd;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_AGP_ENABLE ioctl argument type.
1450N/A *
1450N/A * \sa drmAgpEnable().
1450N/A */
1450N/Astruct drm_agp_mode {
1450N/A unsigned long mode; /**< AGP mode */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
1450N/A *
1450N/A * \sa drmAgpAlloc() and drmAgpFree().
1450N/A */
1450N/Astruct drm_agp_buffer {
1450N/A unsigned long size; /**< In bytes -- will round to page boundary */
1450N/A unsigned long handle; /**< Used for binding / unbinding */
1450N/A unsigned long type; /**< Type of memory to allocate */
1450N/A unsigned long physical; /**< Physical used by i810 */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
1450N/A *
1450N/A * \sa drmAgpBind() and drmAgpUnbind().
1450N/A */
1450N/Astruct drm_agp_binding {
1450N/A unsigned long handle; /**< From drm_agp_buffer */
1450N/A unsigned long offset; /**< In bytes -- will round to page boundary */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_AGP_INFO ioctl argument type.
1450N/A *
1450N/A * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
1450N/A * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
1450N/A * drmAgpVendorId() and drmAgpDeviceId().
1450N/A */
1450N/Astruct drm_agp_info {
1450N/A int agp_version_major;
1450N/A int agp_version_minor;
1450N/A unsigned long mode;
1450N/A unsigned long aperture_base; /* physical address */
1450N/A unsigned long aperture_size; /* bytes */
1450N/A unsigned long memory_allowed; /* bytes */
1450N/A unsigned long memory_used;
1450N/A
1450N/A /* PCI information */
1450N/A unsigned short id_vendor;
1450N/A unsigned short id_device;
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_SG_ALLOC ioctl argument type.
1450N/A */
1450N/Astruct drm_scatter_gather {
1450N/A unsigned long size; /**< In bytes -- will round to page boundary */
1450N/A unsigned long handle; /**< Used for mapping / unmapping */
1450N/A};
1450N/A
1450N/A/**
1450N/A * DRM_IOCTL_SET_VERSION ioctl argument type.
1450N/A */
1450N/Astruct drm_set_version {
1450N/A int drm_di_major;
1450N/A int drm_di_minor;
1450N/A int drm_dd_major;
1450N/A int drm_dd_minor;
1450N/A};
1450N/A
1450N/A/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
1450N/Astruct drm_gem_close {
1450N/A /** Handle of the object to be closed. */
1450N/A __u32 handle;
1450N/A __u32 pad;
1450N/A};
1450N/A
1450N/A/** DRM_IOCTL_GEM_FLINK ioctl argument type */
1450N/Astruct drm_gem_flink {
1450N/A /** Handle for the object being named */
1450N/A __u32 handle;
1450N/A
1450N/A /** Returned global name */
1450N/A __u32 name;
1450N/A};
1450N/A
1450N/A/** DRM_IOCTL_GEM_OPEN ioctl argument type */
1450N/Astruct drm_gem_open {
1450N/A /** Name of object being opened */
1450N/A __u32 name;
1450N/A
1450N/A /** Returned handle for the object */
1450N/A __u32 handle;
1450N/A
1450N/A /** Returned size of the object */
1450N/A __u64 size;
1450N/A};
1450N/A
1450N/A/** DRM_IOCTL_GET_CAP ioctl argument type */
1450N/Astruct drm_get_cap {
1450N/A __u64 capability;
1450N/A __u64 value;
1450N/A};
1450N/A
1450N/A#define DRM_CLOEXEC O_CLOEXEC
1450N/Astruct drm_prime_handle {
1450N/A __u32 handle;
1450N/A
1450N/A /** Flags.. only applicable for handle->fd */
1450N/A __u32 flags;
1450N/A
1450N/A /** Returned dmabuf file descriptor */
1450N/A __s32 fd;
1450N/A};
1450N/A
1450N/A#include "drm_mode.h"
1450N/A
1450N/A#define DRM_IOCTL_BASE 'd'
1450N/A#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
1450N/A#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
1450N/A#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
1450N/A#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
1450N/A
1450N/A#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
1450N/A#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
1450N/A#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
1450N/A#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
1450N/A#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
1450N/A#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
1450N/A#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
1450N/A#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
1450N/A#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
1450N/A#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
1450N/A#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
1450N/A#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
1450N/A#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
1450N/A
1450N/A#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
1450N/A#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
1450N/A#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
1450N/A#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
1450N/A#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
1450N/A#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
1450N/A#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
1450N/A#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
1450N/A#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
1450N/A#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
1450N/A#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
1450N/A
1450N/A#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
1450N/A
1450N/A#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
1450N/A#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
1450N/A
1450N/A#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
1450N/A#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
1450N/A
1450N/A#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
1450N/A#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
1450N/A#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
1450N/A#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
1450N/A#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
1450N/A#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
1450N/A#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
1450N/A#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
1450N/A#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
1450N/A#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
1450N/A#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
1450N/A#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
1450N/A#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
1450N/A
1450N/A#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
1450N/A#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
1450N/A
1450N/A#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
1450N/A#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
1450N/A#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
1450N/A#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
1450N/A#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
1450N/A#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
1450N/A#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
1450N/A#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
1450N/A
1450N/A#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
1450N/A#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
1450N/A
1450N/A#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
1450N/A
1450N/A#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1450N/A
1450N/A#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1450N/A#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
1450N/A#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
1450N/A#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
1450N/A#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
1450N/A#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
1450N/A#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
1450N/A#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
1450N/A#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
1450N/A#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
1450N/A
1450N/A#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
1450N/A#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
1450N/A#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
1450N/A#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
1450N/A#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
1450N/A#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
1450N/A#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
1450N/A#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
1450N/A
1450N/A#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
1450N/A#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
1450N/A#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
1450N/A#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
1450N/A#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
1450N/A#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
1450N/A#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
1450N/A#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
1450N/A#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
1450N/A#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
1450N/A
1450N/A/**
1450N/A * Device specific ioctls should only be in their respective headers
1450N/A * The device specific ioctl range is from 0x40 to 0x99.
1450N/A * Generic IOCTLS restart at 0xA0.
1450N/A *
1450N/A * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1450N/A * drmCommandReadWrite().
1450N/A */
1450N/A#define DRM_COMMAND_BASE 0x40
1450N/A#define DRM_COMMAND_END 0xA0
1450N/A
1450N/A/**
1450N/A * Header for events written back to userspace on the drm fd. The
1450N/A * type defines the type of event, the length specifies the total
1450N/A * length of the event (including the header), and user_data is
1450N/A * typically a 64 bit value passed with the ioctl that triggered the
1450N/A * event. A read on the drm fd will always only return complete
1450N/A * events, that is, if for example the read buffer is 100 bytes, and
1450N/A * there are two 64 byte events pending, only one will be returned.
1450N/A *
1450N/A * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
1450N/A * up are chipset specific.
1450N/A */
1450N/Astruct drm_event {
1450N/A __u32 type;
1450N/A __u32 length;
1450N/A};
1450N/A
1450N/A#define DRM_EVENT_VBLANK 0x01
1450N/A#define DRM_EVENT_FLIP_COMPLETE 0x02
1450N/A
1450N/Astruct drm_event_vblank {
1450N/A struct drm_event base;
1450N/A __u64 user_data;
1450N/A __u64 tv_sec;
1450N/A __u64 tv_usec;
1450N/A __u32 sequence;
1450N/A __u32 reserved;
1450N/A};
1450N/A
1450N/A#define DRM_CAP_DUMB_BUFFER 0x1
1450N/A#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
1450N/A#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
1450N/A#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
1450N/A#define DRM_CAP_PRIME 0x5
1450N/A
1450N/A#define DRM_PRIME_CAP_IMPORT 0x1
1450N/A#define DRM_PRIME_CAP_EXPORT 0x2
1450N/A
1450N/A/* typedef area */
1450N/Atypedef struct drm_clip_rect drm_clip_rect_t;
1450N/Atypedef struct drm_drawable_info drm_drawable_info_t;
1450N/Atypedef struct drm_tex_region drm_tex_region_t;
1450N/Atypedef struct drm_hw_lock drm_hw_lock_t;
1450N/Atypedef struct drm_version drm_version_t;
1450N/Atypedef struct drm_unique drm_unique_t;
1450N/Atypedef struct drm_list drm_list_t;
1450N/Atypedef struct drm_block drm_block_t;
1450N/Atypedef struct drm_control drm_control_t;
1450N/Atypedef enum drm_map_type drm_map_type_t;
1450N/Atypedef enum drm_map_flags drm_map_flags_t;
1450N/Atypedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1450N/Atypedef struct drm_map drm_map_t;
1450N/Atypedef struct drm_client drm_client_t;
1450N/Atypedef enum drm_stat_type drm_stat_type_t;
1450N/Atypedef struct drm_stats drm_stats_t;
1450N/Atypedef enum drm_lock_flags drm_lock_flags_t;
1450N/Atypedef struct drm_lock drm_lock_t;
1450N/Atypedef enum drm_dma_flags drm_dma_flags_t;
1450N/Atypedef struct drm_buf_desc drm_buf_desc_t;
1450N/Atypedef struct drm_buf_info drm_buf_info_t;
1450N/Atypedef struct drm_buf_free drm_buf_free_t;
1450N/Atypedef struct drm_buf_pub drm_buf_pub_t;
1450N/Atypedef struct drm_buf_map drm_buf_map_t;
1450N/Atypedef struct drm_dma drm_dma_t;
1450N/Atypedef union drm_wait_vblank drm_wait_vblank_t;
1450N/Atypedef struct drm_agp_mode drm_agp_mode_t;
1450N/Atypedef enum drm_ctx_flags drm_ctx_flags_t;
1450N/Atypedef struct drm_ctx drm_ctx_t;
1450N/Atypedef struct drm_ctx_res drm_ctx_res_t;
1450N/Atypedef struct drm_draw drm_draw_t;
1450N/Atypedef struct drm_update_draw drm_update_draw_t;
1450N/Atypedef struct drm_auth drm_auth_t;
1450N/Atypedef struct drm_irq_busid drm_irq_busid_t;
1450N/Atypedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1450N/A
1450N/Atypedef struct drm_agp_buffer drm_agp_buffer_t;
1450N/Atypedef struct drm_agp_binding drm_agp_binding_t;
1450N/Atypedef struct drm_agp_info drm_agp_info_t;
1450N/Atypedef struct drm_scatter_gather drm_scatter_gather_t;
1450N/Atypedef struct drm_set_version drm_set_version_t;
1450N/A
1450N/A#endif /* _DRM_H_ */