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sparc_arch.h
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#
ifndef
__SPARC_ARCH_H__
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#
define
__SPARC_ARCH_H__
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#
define
SPARCV9_TICK_PRIVILEGED
(
1
<<0)
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#
define
SPARCV9_PREFER_FPU
(
1
<<
1
)
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#
define
SPARCV9_VIS1
(
1
<<
2
)
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define
SPARCV9_VIS2
(
1
<<
3
)
/* reserved */
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define
SPARCV9_FMADD
(
1
<<
4
)
/* reserved for SPARC64 V */
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define
SPARCV9_BLK
(
1
<<
5
)
/* VIS1 block copy */
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define
SPARCV9_VIS3
(
1
<<
6
)
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define
SPARCV9_RANDOM
(
1
<<
7
)
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#
define
SPARCV9_64BIT_STACK
(
1
<<
8
)
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/*
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* OPENSSL_sparcv9cap_P[1] is copy of Compatibility Feature Register,
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* %asr26, SPARC-T4 and later. There is no SPARCV9_CFR bit in
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* OPENSSL_sparcv9cap_P[0], as %cfr copy is sufficient...
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*/
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define
CFR_AES
0x00000001
/* Supports AES opcodes */
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define
CFR_DES
0x00000002
/* Supports DES opcodes */
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define
CFR_KASUMI
0x00000004
/* Supports KASUMI opcodes */
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define
CFR_CAMELLIA
0x00000008
/* Supports CAMELLIA opcodes */
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define
CFR_MD5
0x00000010
/* Supports MD5 opcodes */
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define
CFR_SHA1
0x00000020
/* Supports SHA1 opcodes */
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define
CFR_SHA256
0x00000040
/* Supports SHA256 opcodes */
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define
CFR_SHA512
0x00000080
/* Supports SHA512 opcodes */
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define
CFR_MPMUL
0x00000100
/* Supports MPMUL opcodes */
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define
CFR_MONTMUL
0x00000200
/* Supports MONTMUL opcodes */
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define
CFR_MONTSQR
0x00000400
/* Supports MONTSQR opcodes */
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define
CFR_CRC32C
0x00000800
/* Supports CRC32C opcodes */
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#
if
defined
(
OPENSSL_PIC
) && !
defined
(
__PIC__
)
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#
define
__PIC__
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#
endif
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#
if
defined
(
__SUNPRO_C
) &&
defined
(
__sparcv9
) && !
defined
(
__arch64__
)
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define
__arch64__
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endif
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define
SPARC_PIC_THUNK
(
reg
) \
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.
align
32
; \
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.
Lpic_thunk
: \
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jmp
%
o7
+
8
; \
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add
%
o7
,
reg
,
reg
;
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define
SPARC_PIC_THUNK_CALL
(
reg
) \
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sethi
%
hi
(
_GLOBAL_OFFSET_TABLE_
-
4
),
reg
; \
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call
.
Lpic_thunk
; \
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or
reg
, %
lo
(
_GLOBAL_OFFSET_TABLE_
+
4
),
reg
;
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if
1
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define
SPARC_SETUP_GOT_REG
(
reg
)
SPARC_PIC_THUNK_CALL
(
reg
)
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#
else
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#
define
SPARC_SETUP_GOT_REG
(
reg
) \
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sethi
%
hi
(
_GLOBAL_OFFSET_TABLE_
-
4
),
reg
; \
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call
.+
8
; \
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or
reg
,%
lo
(
_GLOBAL_OFFSET_TABLE_
+
4
),
reg
; \
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add
%
o7
,
reg
,
reg
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#
endif
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if
defined
(
__arch64__
)
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#
define
SPARC_LOAD_ADDRESS
(
SYM
,
reg
) \
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setx
SYM
, %
o7
,
reg
;
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#
define
LDPTR
ldx
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define
SIZE_T_CC
%
xcc
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define
STACK_FRAME
192
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define
STACK_BIAS
2047
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define
STACK_7thARG
(
STACK_BIAS
+
176
)
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else
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define
SPARC_LOAD_ADDRESS
(
SYM
,
reg
) \
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set
SYM
,
reg
;
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define
LDPTR
ld
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define
SIZE_T_CC
%
icc
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#
define
STACK_FRAME
112
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define
STACK_BIAS
0
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define
STACK_7thARG
92
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define
SPARC_LOAD_ADDRESS_LEAF
(
SYM
,
reg
,
tmp
)
SPARC_LOAD_ADDRESS
(
SYM
,
reg
)
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#
endif
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ifdef
__PIC__
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undef
SPARC_LOAD_ADDRESS
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undef
SPARC_LOAD_ADDRESS_LEAF
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#
define
SPARC_LOAD_ADDRESS
(
SYM
,
reg
) \
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SPARC_SETUP_GOT_REG
(
reg
); \
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sethi
%
hi
(
SYM
), %
o7
; \
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or
%
o7
, %
lo
(
SYM
), %
o7
; \
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LDPTR
[
reg
+ %
o7
],
reg
;
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#
endif
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#
ifndef
SPARC_LOAD_ADDRESS_LEAF
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#
define
SPARC_LOAD_ADDRESS_LEAF
(
SYM
,
reg
,
tmp
) \
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mov
%
o7
,
tmp
; \
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SPARC_LOAD_ADDRESS
(
SYM
,
reg
) \
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mov
tmp
, %
o7
;
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#
endif
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endif
/* __SPARC_ARCH_H__ */