5562N/A/*
5562N/A * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
5562N/A */
5562N/A
5562N/A/*
7118N/A * Redistribution and use in source and binary forms, with or without
7118N/A * modification, are permitted provided that the following conditions are met:
5562N/A *
5562N/A * 1. Redistributions of source code must retain the above copyright notice,
5562N/A * this list of conditions and the following disclaimer.
5562N/A *
5562N/A * 2. Redistributions in binary form must reproduce the above copyright notice,
5562N/A * this list of conditions and the following disclaimer in the documentation
5562N/A * and/or other materials provided with the distribution.
5562N/A *
5562N/A * 3. Neither the name of the copyright holder nor the names of its contributors
7118N/A * may be used to endorse or promote products derived from this software
7118N/A * without specific prior written permission.
5562N/A *
5562N/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
7118N/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7118N/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7118N/A * ARE DISCLAIMED.
7118N/A * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
7118N/A * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7118N/A * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
7118N/A * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
7118N/A * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7118N/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7118N/A * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5562N/A */
5562N/A
5562N/A#ifndef _PSIF_HW_MACRO_H
5562N/A#define _PSIF_HW_MACRO_H
5562N/A
5562N/A#ifdef __cplusplus
5562N/Aextern "C" {
5562N/A#endif
5562N/A
5562N/A#include "psif_api.h"
5562N/A
5562N/A#include "psif_endian.h"
5562N/A#if !defined(__KERNEL__)
5562N/A#include "os_header.h"
5562N/A#endif
5562N/A
5562N/A
7118N/A#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_OFFSET 0
7118N/A#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_SHIFT 32
7118N/A#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_BITS 12
7118N/A#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_MASK 0x00000fff00000000ull
7118N/A
7118N/A#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_OFFSET 0
7118N/A#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_SHIFT 48
7118N/A#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_BITS 12
7118N/A#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_MASK 0x0fff000000000000ull
7118N/A
5562N/A/*
5562N/A * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
5562N/A * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.
5562N/A * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT
5562N/A * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in
5562N/A * the TLB.
5562N/A */
5562N/A#define PSIF_WR_SU_KEY_OFFSET 2
5562N/A#define PSIF_WR_SU_2_KEY_SHIFT 32
5562N/A#define PSIF_WR_SU_2_KEY_BITS 32
5562N/A#define PSIF_WR_SU_2_KEY_MASK 0xffffffff00000000ull
5562N/A
5562N/A/*
5562N/A * Send queue sequence number. Used to map request to a particular work
5562N/A * request in the send queue.
5562N/A */
5562N/A#define PSIF_WR_SQ_SEQ_OFFSET 0
5562N/A#define PSIF_WR_SQ_SEQ_SHIFT 0
5562N/A#define PSIF_WR_SQ_SEQ_BITS 16
5562N/A#define PSIF_WR_SQ_SEQ_MASK 0x000000000000ffffull
5562N/A
5562N/A/*
5562N/A * QP sending this request. XXX: Should name be own_qp_num as defined in QP
5562N/A * state?
5562N/A */
5562N/A#define PSIF_WR_LOCAL_QP_OFFSET 0
5562N/A#define PSIF_WR_LOCAL_QP_SHIFT 32
5562N/A#define PSIF_WR_LOCAL_QP_BITS 24
5562N/A#define PSIF_WR_LOCAL_QP_MASK 0x00ffffff00000000ull
5562N/A
5562N/A/* Completion notification identifier. */
5562N/A#define PSIF_WR_COMPLETION_OFFSET 1
5562N/A#define PSIF_WR_1_COMPLETION_BIT_POSITION 31
5562N/A#define PSIF_WR_1_COMPLETION_BIT 0x0000000080000000ull
5562N/A
5562N/A/*
5562N/A * Checksum used for data protection and consistency between work request and
5562N/A * QP state.
5562N/A */
5562N/A#define PSIF_WR_CHECKSUM_OFFSET 2
5562N/A#define PSIF_WR_2_CHECKSUM_SHIFT 32
5562N/A#define PSIF_WR_2_CHECKSUM_BITS 32
5562N/A#define PSIF_WR_2_CHECKSUM_MASK 0xffffffff00000000ull
5562N/A
5562N/A/*
5562N/A * Index to where elements are added to the send queue by SW. SW is
5562N/A * responsibel for keeping track of how many entries there are in the send
5562N/A * queue. I.e. SW needs to keep track of the head_index so it doesn't
5562N/A * overwrite entries in the send queue which is not yet completed.
5562N/A */
5562N/A#define PSIF_SQ_SW_TAIL_INDX_OFFSET 0
5562N/A#define PSIF_SQ_SW_TAIL_INDX_SHIFT 32
5562N/A#define PSIF_SQ_SW_TAIL_INDX_BITS 16
5562N/A#define PSIF_SQ_SW_TAIL_INDX_MASK 0x0000ffff00000000ull
5562N/A
5562N/A/*
5562N/A * Send queue sequence number used by the SQS to maintain ordering and keep
5562N/A * track of where which send queue elements to fetch. This field is not in
5562N/A * sync with the field in qp_t. This number is typically a little bit before
5562N/A * the number in the qp_t as SQS has to fetch the elements from host memory.
5562N/A * This is also used as tail_index when checking if there are more elements
5562N/A * in the send queue.
5562N/A */
5562N/A#define PSIF_SQ_HW_LAST_SEQ_OFFSET 0
5562N/A#define PSIF_SQ_HW_LAST_SEQ_SHIFT 16
5562N/A#define PSIF_SQ_HW_LAST_SEQ_BITS 16
5562N/A#define PSIF_SQ_HW_LAST_SEQ_MASK 0x00000000ffff0000ull
5562N/A
5562N/A/* QP and UF to be processed next. */
5562N/A#define PSIF_SQ_HW_SQ_NEXT_OFFSET 0
5562N/A#define PSIF_SQ_HW_SQ_NEXT_SHIFT 32
5562N/A#define PSIF_SQ_HW_SQ_NEXT_BITS 32
5562N/A#define PSIF_SQ_HW_SQ_NEXT_MASK 0xffffffff00000000ull
5562N/A
5562N/A/*
5562N/A * This bit is set through the doorbell. SW should check this bit plus
5562N/A * psif_next = null to ensure SW can own the SQ descriptor.
5562N/A */
5562N/A#define PSIF_SQ_HW_DESTROYED_OFFSET 1
5562N/A#define PSIF_SQ_HW_1_DESTROYED_BIT_POSITION 27
5562N/A#define PSIF_SQ_HW_1_DESTROYED_BIT 0x0000000008000000ull
5562N/A
5562N/A/* Software modified index pointing to the tail reecive entry in host memory. */
5562N/A#define PSIF_RQ_SW_TAIL_INDX_OFFSET 0
5562N/A#define PSIF_RQ_SW_TAIL_INDX_SHIFT 32
5562N/A#define PSIF_RQ_SW_TAIL_INDX_BITS 14
5562N/A#define PSIF_RQ_SW_TAIL_INDX_MASK 0x00003fff00000000ull
5562N/A
5562N/A/*
5562N/A * Hardware modified index pointing to the head of the receive queue. TSU is
5562N/A * using this to find the address of the receive queue entry.
5562N/A */
5562N/A#define PSIF_RQ_HW_HEAD_INDX_OFFSET 0
5562N/A#define PSIF_RQ_HW_HEAD_INDX_SHIFT 14
5562N/A#define PSIF_RQ_HW_HEAD_INDX_BITS 14
5562N/A#define PSIF_RQ_HW_HEAD_INDX_MASK 0x000000000fffc000ull
5562N/A
5562N/A/* The desciptor is valid. */
5562N/A#define PSIF_RQ_HW_VALID_OFFSET 3
5562N/A#define PSIF_RQ_HW_3_VALID_BIT_POSITION 55
5562N/A#define PSIF_RQ_HW_3_VALID_BIT 0x0080000000000000ull
5562N/A
5562N/A/*
5562N/A * Receive queue entry ID. This is added to the receive completion using this
5562N/A * receive queue entry.
5562N/A */
5562N/A#define PSIF_RQ_ENTRY_RQE_ID_OFFSET 0
5562N/A#define PSIF_RQ_ENTRY_RQE_ID_SHIFT 0
5562N/A#define PSIF_RQ_ENTRY_RQE_ID_BITS 64
5562N/A#define PSIF_RQ_ENTRY_RQE_ID_MASK 0xffffffffffffffffull
5562N/A
5562N/A/*
5562N/A * This retry tag is the one used by tsu_rqs and added to the packets sent to
5562N/A * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag
5562N/A * whenever the sq_sequence_number in QP state is equal to the one in the
5562N/A * request.
5562N/A */
5562N/A#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_OFFSET 0
5562N/A#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_SHIFT 0
5562N/A#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_BITS 3
5562N/A#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_MASK 0x0000000000000007ull
5562N/A
5562N/A/*
5562N/A * This retry tag is updated by the error block when an error occur. If
5562N/A * tsu_rqs reads this retry tag and it is different than the
5562N/A * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of
5562N/A * retry_tag_err when the sq_sequence_number indicates this is the valid
5562N/A * request. The sq_sequence_number has been updated by tsu_err at the same
5562N/A * time the retry_tag_err is updated.
5562N/A */
5562N/A#define PSIF_QP_CORE_RETRY_TAG_ERR_OFFSET 0
5562N/A#define PSIF_QP_CORE_RETRY_TAG_ERR_SHIFT 3
5562N/A#define PSIF_QP_CORE_RETRY_TAG_ERR_BITS 3
5562N/A#define PSIF_QP_CORE_RETRY_TAG_ERR_MASK 0x0000000000000038ull
5562N/A
5562N/A/*
5562N/A * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
5562N/A * calculate exp_backoff etc..
5562N/A */
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_INIT_OFFSET 0
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_INIT_SHIFT 32
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_INIT_BITS 3
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_INIT_MASK 0x0000000700000000ull
5562N/A
5562N/A/*
5562N/A * Retry counter associated with retries to received NAK or implied NAK. If
5562N/A * it expires, a path migration will be attempted if it is armed, or the QP
5562N/A * will go to error state. Read by tsu_dma and used by tsu_cmpl.
5562N/A */
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_COUNT_OFFSET 0
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_COUNT_SHIFT 35
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_COUNT_BITS 3
5562N/A#define PSIF_QP_CORE_ERROR_RETRY_COUNT_MASK 0x0000003800000000ull
5562N/A
5562N/A/* A hit in the set locally spun out of tsu_cmpl is found. */
5562N/A#define PSIF_QP_CORE_SPIN_HIT_OFFSET 0
5562N/A#define PSIF_QP_CORE_SPIN_HIT_BIT_POSITION 39
5562N/A#define PSIF_QP_CORE_SPIN_HIT_BIT 0x0000008000000000ull
5562N/A
5562N/A/*
5562N/A * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester
5562N/A * receiving the RNR NAK must wait until the timer has expired before the
5562N/A * retry is sent.
5562N/A */
5562N/A#define PSIF_QP_CORE_MIN_RNR_NAK_TIME_OFFSET 1
5562N/A#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_SHIFT 0
5562N/A#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_BITS 5
5562N/A#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_MASK 0x000000000000001full
5562N/A
5562N/A/* QP State for this QP. */
5562N/A#define PSIF_QP_CORE_STATE_OFFSET 1
5562N/A#define PSIF_QP_CORE_1_STATE_SHIFT 5
5562N/A#define PSIF_QP_CORE_1_STATE_BITS 3
5562N/A#define PSIF_QP_CORE_1_STATE_MASK 0x00000000000000e0ull
5562N/A
5562N/A/* QP number for the remote node. */
5562N/A#define PSIF_QP_CORE_REMOTE_QP_OFFSET 1
5562N/A#define PSIF_QP_CORE_1_REMOTE_QP_SHIFT 8
5562N/A#define PSIF_QP_CORE_1_REMOTE_QP_BITS 24
5562N/A#define PSIF_QP_CORE_1_REMOTE_QP_MASK 0x00000000ffffff00ull
5562N/A
5562N/A#define PSIF_QP_CORE_RETRY_SQ_SEQ_OFFSET 2
5562N/A#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_SHIFT 32
5562N/A#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_BITS 16
5562N/A#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_MASK 0x0000ffff00000000ull
5562N/A
5562N/A#define PSIF_QP_CORE_SQ_SEQ_OFFSET 2
5562N/A#define PSIF_QP_CORE_2_SQ_SEQ_SHIFT 48
5562N/A#define PSIF_QP_CORE_2_SQ_SEQ_BITS 16
5562N/A#define PSIF_QP_CORE_2_SQ_SEQ_MASK 0xffff000000000000ull
5562N/A
5562N/A/*
5562N/A * Magic number used to verify use of QP state. This is done by calculating a
5562N/A * checksum of the work request incorporating the magic number. This checksum
5562N/A * is checked against the checksum in the work request.
5562N/A */
5562N/A#define PSIF_QP_CORE_MAGIC_OFFSET 3
5562N/A#define PSIF_QP_CORE_3_MAGIC_SHIFT 0
5562N/A#define PSIF_QP_CORE_3_MAGIC_BITS 32
5562N/A#define PSIF_QP_CORE_3_MAGIC_MASK 0x00000000ffffffffull
5562N/A
5562N/A/*
5562N/A * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key
5562N/A * used on transmit if top bit of Q-Key in WR is set.
5562N/A */
5562N/A#define PSIF_QP_CORE_QKEY_OFFSET 4
5562N/A#define PSIF_QP_CORE_4_QKEY_SHIFT 0
5562N/A#define PSIF_QP_CORE_4_QKEY_BITS 32
5562N/A#define PSIF_QP_CORE_4_QKEY_MASK 0x00000000ffffffffull
5562N/A
5562N/A/*
5562N/A * Sequence number of the last ACK received. Read and written by tsu_cmpl.
5562N/A * Used to verify that the received response packet is a valid response.
5562N/A */
5562N/A#define PSIF_QP_CORE_LAST_ACKED_PSN_OFFSET 4
5562N/A#define PSIF_QP_CORE_4_LAST_ACKED_PSN_SHIFT 40
5562N/A#define PSIF_QP_CORE_4_LAST_ACKED_PSN_BITS 24
5562N/A#define PSIF_QP_CORE_4_LAST_ACKED_PSN_MASK 0xffffff0000000000ull
5562N/A
5562N/A/* Index to scatter element of in progress SEND. */
5562N/A#define PSIF_QP_CORE_SCATTER_INDX_OFFSET 5
5562N/A#define PSIF_QP_CORE_5_SCATTER_INDX_SHIFT 32
5562N/A#define PSIF_QP_CORE_5_SCATTER_INDX_BITS 5
5562N/A#define PSIF_QP_CORE_5_SCATTER_INDX_MASK 0x0000001f00000000ull
5562N/A
5562N/A/*
5562N/A * Expected packet sequence number: Sequence number on next expected packet.
5562N/A */
5562N/A#define PSIF_QP_CORE_EXPECTED_PSN_OFFSET 5
5562N/A#define PSIF_QP_CORE_5_EXPECTED_PSN_SHIFT 40
5562N/A#define PSIF_QP_CORE_5_EXPECTED_PSN_BITS 24
5562N/A#define PSIF_QP_CORE_5_EXPECTED_PSN_MASK 0xffffff0000000000ull
5562N/A
5562N/A/*
5562N/A * TSU quality of service level. Can take values indicating low latency and
5562N/A * high throughput. This is equivalent to high/low BAR when writing doorbells
5562N/A * to PSIF. The qosl bit in the doorbell request must match this bit in the
5562N/A * QP state, otherwise the QP must be put in error. This check only applies
5562N/A * to tsu_rqs.
5562N/A */
5562N/A#define PSIF_QP_CORE_QOSL_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_QOSL_BIT_POSITION 49
5562N/A#define PSIF_QP_CORE_6_QOSL_BIT 0x0002000000000000ull
5562N/A
5562N/A/*
5562N/A * Migration state (migrated, re-arm and armed). Since path migration is
5562N/A * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
5562N/A * handler also be able to change the path?
5562N/A */
5562N/A#define PSIF_QP_CORE_MSTATE_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_MSTATE_SHIFT 50
5562N/A#define PSIF_QP_CORE_6_MSTATE_BITS 2
5562N/A#define PSIF_QP_CORE_6_MSTATE_MASK 0x000c000000000000ull
5562N/A
5562N/A/* This is an IB over IB QP. */
5562N/A#define PSIF_QP_CORE_IPOIB_ENABLE_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT_POSITION 53
5562N/A#define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT 0x0020000000000000ull
5562N/A
5562N/A/* IB defined capability enable for receiving Atomic operations. */
5562N/A#define PSIF_QP_CORE_ATOMIC_ENABLE_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT_POSITION 61
5562N/A#define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT 0x2000000000000000ull
5562N/A
5562N/A/* IB defined capability enable for receiving RDMA WR. */
5562N/A#define PSIF_QP_CORE_RDMA_WR_ENABLE_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT_POSITION 62
5562N/A#define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT 0x4000000000000000ull
5562N/A
5562N/A/* IB defined capability enable for receiving RDMA RD. */
5562N/A#define PSIF_QP_CORE_RDMA_RD_ENABLE_OFFSET 6
5562N/A#define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT_POSITION 63
5562N/A#define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT 0x8000000000000000ull
5562N/A
5562N/A/*
5562N/A * Transmit packet sequence number. Read and updated by tsu_dma before
5562N/A * sending packets to tsu_ibpb and tsu_cmpl.
5562N/A */
5562N/A#define PSIF_QP_CORE_XMIT_PSN_OFFSET 7
5562N/A#define PSIF_QP_CORE_7_XMIT_PSN_SHIFT 0
5562N/A#define PSIF_QP_CORE_7_XMIT_PSN_BITS 24
5562N/A#define PSIF_QP_CORE_7_XMIT_PSN_MASK 0x0000000000ffffffull
5562N/A
5562N/A/*
5562N/A * TSU Service Level used to decide the TSU VL for requests associated with
5562N/A * this QP.
5562N/A */
5562N/A#define PSIF_QP_CORE_TSL_OFFSET 7
5562N/A#define PSIF_QP_CORE_7_TSL_SHIFT 55
5562N/A#define PSIF_QP_CORE_7_TSL_BITS 4
5562N/A#define PSIF_QP_CORE_7_TSL_MASK 0x0780000000000000ull
5562N/A
5562N/A/*
5562N/A * Maximum number of outstanding read or atomic requests allowed by the
5562N/A * remote HCA. Initialized by software.
5562N/A */
5562N/A#define PSIF_QP_CORE_MAX_OUTSTANDING_OFFSET 7
5562N/A#define PSIF_QP_CORE_7_MAX_OUTSTANDING_SHIFT 59
5562N/A#define PSIF_QP_CORE_7_MAX_OUTSTANDING_BITS 5
5562N/A#define PSIF_QP_CORE_7_MAX_OUTSTANDING_MASK 0xf800000000000000ull
5562N/A
5562N/A/* Send Queue RNR retry count initialization value. */
5562N/A#define PSIF_QP_CORE_RNR_RETRY_INIT_OFFSET 8
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_INIT_SHIFT 32
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_INIT_BITS 3
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_INIT_MASK 0x0000000700000000ull
5562N/A
5562N/A/*
5562N/A * Retry counter associated with RNR NAK retries. If it expires, a path
5562N/A * migration will be attempted if it is armed, or the QP will go to error
5562N/A * state.
5562N/A */
5562N/A#define PSIF_QP_CORE_RNR_RETRY_COUNT_OFFSET 8
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_SHIFT 35
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_BITS 3
5562N/A#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_MASK 0x0000003800000000ull
5562N/A
5562N/A/*
5562N/A * When set, RQS should only check that the orig_checksum is equal to magic
5562N/A * number. When not set, RQS should perform the checksum check towards the
5562N/A * checksum in the psif_wr.
5562N/A */
5562N/A#define PSIF_QP_CORE_NO_CHECKSUM_OFFSET 8
5562N/A#define PSIF_QP_CORE_8_NO_CHECKSUM_BIT_POSITION 39
5562N/A#define PSIF_QP_CORE_8_NO_CHECKSUM_BIT 0x0000008000000000ull
5562N/A
5562N/A/*
5562N/A * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for
5562N/A * privileged QPs.
5562N/A */
5562N/A#define PSIF_QP_CORE_TRANSPORT_TYPE_OFFSET 9
5562N/A#define PSIF_QP_CORE_9_TRANSPORT_TYPE_SHIFT 0
5562N/A#define PSIF_QP_CORE_9_TRANSPORT_TYPE_BITS 3
5562N/A#define PSIF_QP_CORE_9_TRANSPORT_TYPE_MASK 0x0000000000000007ull
5562N/A
5562N/A/*
7118N/A * This is an index to completion queue descriptor. The descriptor points to
7118N/A * a receive completion queue, which may or may not be the same as the send
7118N/A * completion queue. For XRC QPs, this field is written by the CQ descriptor
7118N/A * received by the XRCSRQ on the first packet. This way we don't need to look
7118N/A * up the XRCSRQ for every packet. of the message.
7118N/A */
7118N/A#define PSIF_QP_CORE_RCV_CQ_INDX_OFFSET 9
7118N/A#define PSIF_QP_CORE_9_RCV_CQ_INDX_SHIFT 8
7118N/A#define PSIF_QP_CORE_9_RCV_CQ_INDX_BITS 24
7118N/A#define PSIF_QP_CORE_9_RCV_CQ_INDX_MASK 0x00000000ffffff00ull
7118N/A
7118N/A/*
5562N/A * Number of bytes received of in progress RDMA Write or SEND. The data
5562N/A * received for SENDs and RDMA WR w/Imm are needed for completions. This
5562N/A * should be added to the msg_length.
5562N/A */
5562N/A#define PSIF_QP_CORE_BYTES_RECEIVED_OFFSET 9
5562N/A#define PSIF_QP_CORE_9_BYTES_RECEIVED_SHIFT 32
5562N/A#define PSIF_QP_CORE_9_BYTES_RECEIVED_BITS 32
5562N/A#define PSIF_QP_CORE_9_BYTES_RECEIVED_MASK 0xffffffff00000000ull
5562N/A
5562N/A/* This QP is running IP over IB. */
5562N/A#define PSIF_QP_CORE_IPOIB_OFFSET 10
5562N/A#define PSIF_QP_CORE_10_IPOIB_BIT_POSITION 5
5562N/A#define PSIF_QP_CORE_10_IPOIB_BIT 0x0000000000000020ull
5562N/A
5562N/A/*
5562N/A * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain
5562N/A * 'spin set floor' and indicate 'all retries completed', respectively.
5562N/A */
5562N/A#define PSIF_QP_CORE_LAST_RECEIVED_OUTSTANDING_MSN_OFFSET 11
5562N/A#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_SHIFT 0
5562N/A#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_BITS 16
5562N/A#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_MASK 0x000000000000ffffull
5562N/A
5562N/A#define PSIF_QP_CORE_PATH_MTU_OFFSET 13
5562N/A#define PSIF_QP_CORE_13_PATH_MTU_SHIFT 4
5562N/A#define PSIF_QP_CORE_13_PATH_MTU_BITS 3
5562N/A#define PSIF_QP_CORE_13_PATH_MTU_MASK 0x0000000000000070ull
5562N/A
5562N/A/* This PSN is committed - ACKs sent will contain this PSN. */
5562N/A#define PSIF_QP_CORE_COMMITTED_RECEIVED_PSN_OFFSET 13
5562N/A#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_SHIFT 8
5562N/A#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_BITS 24
5562N/A#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_MASK 0x00000000ffffff00ull
5562N/A
5562N/A/*
5562N/A * Message sequence number used in AETH when sending ACKs. The number is
5562N/A * incremented every time a new inbound message is processed.
5562N/A */
5562N/A#define PSIF_QP_CORE_MSN_OFFSET 14
5562N/A#define PSIF_QP_CORE_14_MSN_SHIFT 0
5562N/A#define PSIF_QP_CORE_14_MSN_BITS 24
5562N/A#define PSIF_QP_CORE_14_MSN_MASK 0x0000000000ffffffull
5562N/A
5562N/A/*
5562N/A * This is an index to send completion queue descriptor. The descriptor
5562N/A * points to a send completion queue, which may or may not be the same as the
5562N/A * send completion queue.
5562N/A */
5562N/A#define PSIF_QP_CORE_SEND_CQ_INDX_OFFSET 14
5562N/A#define PSIF_QP_CORE_14_SEND_CQ_INDX_SHIFT 24
5562N/A#define PSIF_QP_CORE_14_SEND_CQ_INDX_BITS 24
5562N/A#define PSIF_QP_CORE_14_SEND_CQ_INDX_MASK 0x0000ffffff000000ull
5562N/A
5562N/A/*
5562N/A * Committed MSN - the MSN of the newest committed request for this QP. Only
5562N/A * the bottom 16 bits of the MSN is used.
5562N/A */
5562N/A#define PSIF_QP_CORE_LAST_COMMITTED_MSN_OFFSET 14
5562N/A#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_SHIFT 48
5562N/A#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_BITS 16
5562N/A#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_MASK 0xffff000000000000ull
5562N/A
5562N/A#define PSIF_QP_CORE_SRQ_PD_OFFSET 15
5562N/A#define PSIF_QP_CORE_15_SRQ_PD_SHIFT 0
5562N/A#define PSIF_QP_CORE_15_SRQ_PD_BITS 24
5562N/A#define PSIF_QP_CORE_15_SRQ_PD_MASK 0x0000000000ffffffull
5562N/A
5562N/A#define PSIF_QP_PATH_REMOTE_GID_0_OFFSET 0
5562N/A#define PSIF_QP_PATH_REMOTE_GID_0_SHIFT 0
5562N/A#define PSIF_QP_PATH_REMOTE_GID_0_BITS 64
5562N/A#define PSIF_QP_PATH_REMOTE_GID_0_MASK 0xffffffffffffffffull
5562N/A
5562N/A#define PSIF_QP_PATH_REMOTE_GID_1_OFFSET 1
5562N/A#define PSIF_QP_PATH_1_REMOTE_GID_1_SHIFT 0
5562N/A#define PSIF_QP_PATH_1_REMOTE_GID_1_BITS 64
5562N/A#define PSIF_QP_PATH_1_REMOTE_GID_1_MASK 0xffffffffffffffffull
5562N/A
5562N/A#define PSIF_QP_PATH_REMOTE_LID_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_REMOTE_LID_SHIFT 0
5562N/A#define PSIF_QP_PATH_2_REMOTE_LID_BITS 16
5562N/A#define PSIF_QP_PATH_2_REMOTE_LID_MASK 0x000000000000ffffull
5562N/A
5562N/A#define PSIF_QP_PATH_PORT_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_PORT_BIT_POSITION 17
5562N/A#define PSIF_QP_PATH_2_PORT_BIT 0x0000000000020000ull
5562N/A
5562N/A#define PSIF_QP_PATH_LOOPBACK_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_LOOPBACK_BIT_POSITION 18
5562N/A#define PSIF_QP_PATH_2_LOOPBACK_BIT 0x0000000000040000ull
5562N/A
5562N/A#define PSIF_QP_PATH_USE_GRH_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_USE_GRH_BIT_POSITION 19
5562N/A#define PSIF_QP_PATH_2_USE_GRH_BIT 0x0000000000080000ull
5562N/A
5562N/A#define PSIF_QP_PATH_SL_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_SL_SHIFT 20
5562N/A#define PSIF_QP_PATH_2_SL_BITS 4
5562N/A#define PSIF_QP_PATH_2_SL_MASK 0x0000000000f00000ull
5562N/A
5562N/A#define PSIF_QP_PATH_HOPLMT_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_HOPLMT_SHIFT 28
5562N/A#define PSIF_QP_PATH_2_HOPLMT_BITS 8
5562N/A#define PSIF_QP_PATH_2_HOPLMT_MASK 0x0000000ff0000000ull
5562N/A
5562N/A#define PSIF_QP_PATH_FLOWLABEL_OFFSET 2
5562N/A#define PSIF_QP_PATH_2_FLOWLABEL_SHIFT 44
5562N/A#define PSIF_QP_PATH_2_FLOWLABEL_BITS 20
5562N/A#define PSIF_QP_PATH_2_FLOWLABEL_MASK 0xfffff00000000000ull
5562N/A
5562N/A#define PSIF_QP_PATH_LOCAL_ACK_TIMEOUT_OFFSET 3
5562N/A#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_SHIFT 27
5562N/A#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_BITS 5
5562N/A#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_MASK 0x00000000f8000000ull
5562N/A
5562N/A#define PSIF_QP_PATH_IPD_OFFSET 3
5562N/A#define PSIF_QP_PATH_3_IPD_SHIFT 32
5562N/A#define PSIF_QP_PATH_3_IPD_BITS 8
5562N/A#define PSIF_QP_PATH_3_IPD_MASK 0x000000ff00000000ull
5562N/A
5562N/A/*
5562N/A * This is the LID path bits. This is used by tsu_ibpb when generating the
5562N/A * SLID in the packet, and it is used by tsu_rcv when checking the DLID.
5562N/A */
5562N/A#define PSIF_QP_PATH_LOCAL_LID_PATH_OFFSET 3
5562N/A#define PSIF_QP_PATH_3_LOCAL_LID_PATH_SHIFT 48
5562N/A#define PSIF_QP_PATH_3_LOCAL_LID_PATH_BITS 7
5562N/A#define PSIF_QP_PATH_3_LOCAL_LID_PATH_MASK 0x007f000000000000ull
5562N/A
5562N/A#define PSIF_QP_PATH_PKEY_INDX_OFFSET 3
5562N/A#define PSIF_QP_PATH_3_PKEY_INDX_SHIFT 55
5562N/A#define PSIF_QP_PATH_3_PKEY_INDX_BITS 9
5562N/A#define PSIF_QP_PATH_3_PKEY_INDX_MASK 0xff80000000000000ull
5562N/A
5562N/A/* L-key state for this DMA validation entry */
5562N/A#define PSIF_KEY_LKEY_STATE_OFFSET 0
5562N/A#define PSIF_KEY_LKEY_STATE_SHIFT 60
5562N/A#define PSIF_KEY_LKEY_STATE_BITS 2
5562N/A#define PSIF_KEY_LKEY_STATE_MASK 0x3000000000000000ull
5562N/A
5562N/A/* R-key state for this DMA validation entry */
5562N/A#define PSIF_KEY_RKEY_STATE_OFFSET 0
5562N/A#define PSIF_KEY_RKEY_STATE_SHIFT 62
5562N/A#define PSIF_KEY_RKEY_STATE_BITS 2
5562N/A#define PSIF_KEY_RKEY_STATE_MASK 0xc000000000000000ull
5562N/A
5562N/A/* Length of memory region this validation entry is associated with. */
5562N/A#define PSIF_KEY_LENGTH_OFFSET 1
5562N/A#define PSIF_KEY_1_LENGTH_SHIFT 0
5562N/A#define PSIF_KEY_1_LENGTH_BITS 64
5562N/A#define PSIF_KEY_1_LENGTH_MASK 0xffffffffffffffffull
5562N/A
5562N/A#define PSIF_KEY_MMU_CONTEXT_OFFSET 2
5562N/A#define PSIF_KEY_2_MMU_CONTEXT_SHIFT 0
5562N/A#define PSIF_KEY_2_MMU_CONTEXT_BITS 64
5562N/A#define PSIF_KEY_2_MMU_CONTEXT_MASK 0xffffffffffffffffull
5562N/A
5562N/A#define PSIF_KEY_BASE_ADDR_OFFSET 3
5562N/A#define PSIF_KEY_3_BASE_ADDR_SHIFT 0
5562N/A#define PSIF_KEY_3_BASE_ADDR_BITS 64
5562N/A#define PSIF_KEY_3_BASE_ADDR_MASK 0xffffffffffffffffull
5562N/A
5562N/A/* sequence number for sanity checking */
5562N/A#define PSIF_EQ_ENTRY_SEQ_NUM_OFFSET 7
5562N/A#define PSIF_EQ_ENTRY_7_SEQ_NUM_SHIFT 0
5562N/A#define PSIF_EQ_ENTRY_7_SEQ_NUM_BITS 32
5562N/A#define PSIF_EQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull
5562N/A
5562N/A/* enum psif_epsc_csr_opcode from request */
5562N/A#define PSIF_EPSC_CSR_RSP_OPCODE_OFFSET 0
5562N/A#define PSIF_EPSC_CSR_RSP_OPCODE_SHIFT 48
5562N/A#define PSIF_EPSC_CSR_RSP_OPCODE_BITS 8
5562N/A#define PSIF_EPSC_CSR_RSP_OPCODE_MASK 0x00ff000000000000ull
5562N/A
5562N/A/* Sequence number from request */
5562N/A#define PSIF_EPSC_CSR_RSP_SEQ_NUM_OFFSET 3
5562N/A#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_SHIFT 0
5562N/A#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_BITS 64
5562N/A#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_MASK 0xffffffffffffffffull
5562N/A
5562N/A/* Sequence number - included in response */
5562N/A#define PSIF_EPSC_CSR_REQ_SEQ_NUM_OFFSET 0
5562N/A#define PSIF_EPSC_CSR_REQ_SEQ_NUM_SHIFT 32
5562N/A#define PSIF_EPSC_CSR_REQ_SEQ_NUM_BITS 16
5562N/A#define PSIF_EPSC_CSR_REQ_SEQ_NUM_MASK 0x0000ffff00000000ull
5562N/A
5562N/A#define PSIF_EPSC_CSR_REQ_OPCODE_OFFSET 0
5562N/A#define PSIF_EPSC_CSR_REQ_OPCODE_SHIFT 56
5562N/A#define PSIF_EPSC_CSR_REQ_OPCODE_BITS 8
5562N/A#define PSIF_EPSC_CSR_REQ_OPCODE_MASK 0xff00000000000000ull
5562N/A
5562N/A/* Index to completion elements added by SW. */
5562N/A#define PSIF_CQ_SW_HEAD_INDX_OFFSET 0
5562N/A#define PSIF_CQ_SW_HEAD_INDX_SHIFT 32
5562N/A#define PSIF_CQ_SW_HEAD_INDX_BITS 32
5562N/A#define PSIF_CQ_SW_HEAD_INDX_MASK 0xffffffff00000000ull
5562N/A
5562N/A/*
5562N/A * EPS-A core number completions are forwarded to if the proxy_enabled bit is
5562N/A * set.
5562N/A */
5562N/A#define PSIF_CQ_HW_EPS_CORE_OFFSET 0
5562N/A#define PSIF_CQ_HW_EPS_CORE_SHIFT 52
5562N/A#define PSIF_CQ_HW_EPS_CORE_BITS 2
5562N/A#define PSIF_CQ_HW_EPS_CORE_MASK 0x0030000000000000ull
5562N/A
5562N/A/*
5562N/A * If set, this completion queue is proxy enabled and should send completions
5562N/A * to EPS core indicated by the eps_core field.
5562N/A */
5562N/A#define PSIF_CQ_HW_PROXY_EN_OFFSET 0
5562N/A#define PSIF_CQ_HW_PROXY_EN_BIT_POSITION 54
5562N/A#define PSIF_CQ_HW_PROXY_EN_BIT 0x0040000000000000ull
5562N/A
5562N/A/* The descriptor is valid. */
5562N/A#define PSIF_CQ_HW_VALID_OFFSET 0
5562N/A#define PSIF_CQ_HW_VALID_BIT_POSITION 60
5562N/A#define PSIF_CQ_HW_VALID_BIT 0x1000000000000000ull
5562N/A
5562N/A/*
5562N/A * VA or PA of the base of the completion queue. If PA the MMU context above
5562N/A * will be a bypass context. Updated by software. The head and tail pointers
5562N/A * can be calculated by the following calculations: Address = base_ptr +
5562N/A * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will
5562N/A * use the same MMU context as the base, and all need to be VA from one
5562N/A * address space, or all need to be PA. In typical use, to allow direct user
5562N/A * access to the head and tail pointer VAs are used.
5562N/A */
5562N/A#define PSIF_CQ_HW_BASE_ADDR_OFFSET 2
5562N/A#define PSIF_CQ_HW_2_BASE_ADDR_SHIFT 0
5562N/A#define PSIF_CQ_HW_2_BASE_ADDR_BITS 64
5562N/A#define PSIF_CQ_HW_2_BASE_ADDR_MASK 0xffffffffffffffffull
5562N/A
5562N/A/* Index to completion elements to be consumed by HW. */
5562N/A#define PSIF_CQ_HW_TAIL_INDX_OFFSET 3
5562N/A#define PSIF_CQ_HW_3_TAIL_INDX_SHIFT 32
5562N/A#define PSIF_CQ_HW_3_TAIL_INDX_BITS 32
5562N/A#define PSIF_CQ_HW_3_TAIL_INDX_MASK 0xffffffff00000000ull
5562N/A
5562N/A/*
5562N/A * Work queue completion ID. For receive completions this is the entry number
5562N/A * in the receive queue and the receive queue descriptor index. For send
5562N/A * completions this is the sq_sequence number.
5562N/A */
5562N/A#define PSIF_CQ_ENTRY_WC_ID_OFFSET 0
5562N/A#define PSIF_CQ_ENTRY_WC_ID_SHIFT 0
5562N/A#define PSIF_CQ_ENTRY_WC_ID_BITS 64
5562N/A#define PSIF_CQ_ENTRY_WC_ID_MASK 0xffffffffffffffffull
5562N/A
5562N/A#define PSIF_CQ_ENTRY_QP_OFFSET 1
5562N/A#define PSIF_CQ_ENTRY_1_QP_SHIFT 0
5562N/A#define PSIF_CQ_ENTRY_1_QP_BITS 24
5562N/A#define PSIF_CQ_ENTRY_1_QP_MASK 0x0000000000ffffffull
5562N/A
5562N/A#define PSIF_CQ_ENTRY_OPCODE_OFFSET 1
5562N/A#define PSIF_CQ_ENTRY_1_OPCODE_SHIFT 24
5562N/A#define PSIF_CQ_ENTRY_1_OPCODE_BITS 8
5562N/A#define PSIF_CQ_ENTRY_1_OPCODE_MASK 0x00000000ff000000ull
5562N/A
5562N/A#define PSIF_CQ_ENTRY_STATUS_OFFSET 2
5562N/A#define PSIF_CQ_ENTRY_2_STATUS_SHIFT 24
5562N/A#define PSIF_CQ_ENTRY_2_STATUS_BITS 8
5562N/A#define PSIF_CQ_ENTRY_2_STATUS_MASK 0x00000000ff000000ull
5562N/A
5562N/A/* sequence number for sanity checking */
5562N/A#define PSIF_CQ_ENTRY_SEQ_NUM_OFFSET 7
5562N/A#define PSIF_CQ_ENTRY_7_SEQ_NUM_SHIFT 0
5562N/A#define PSIF_CQ_ENTRY_7_SEQ_NUM_BITS 32
5562N/A#define PSIF_CQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull
5562N/A
5562N/A#define PSIF_AH_REMOTE_LID_OFFSET 2
5562N/A#define PSIF_AH_2_REMOTE_LID_SHIFT 0
5562N/A#define PSIF_AH_2_REMOTE_LID_BITS 16
5562N/A#define PSIF_AH_2_REMOTE_LID_MASK 0x000000000000ffffull
5562N/A
5562N/A#define PSIF_AH_SL_OFFSET 2
5562N/A#define PSIF_AH_2_SL_SHIFT 20
5562N/A#define PSIF_AH_2_SL_BITS 4
5562N/A#define PSIF_AH_2_SL_MASK 0x0000000000f00000ull
7118N/A#if defined(HOST_LITTLE_ENDIAN)
7118N/A#elif defined(HOST_BIG_ENDIAN)
5562N/A#else
5562N/A#error "Could not determine byte order in psif_hw_macro.h !?"
5562N/A#endif
5562N/A
5562N/A
5562N/A#ifdef __cplusplus
5562N/A}
5562N/A#endif
5562N/A
5562N/A
5562N/A#endif /* _PSIF_HW_MACRO_H */