5203N/A * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. 5203N/A * Redistribution and use in source and binary forms, with or without 5203N/A * modification, are permitted provided that the following conditions are met: 5203N/A * 1. Redistributions of source code must retain the above copyright notice, 5203N/A * this list of conditions and the following disclaimer. 5203N/A * 2. Redistributions in binary form must reproduce the above copyright notice, 5203N/A * this list of conditions and the following disclaimer in the documentation 5203N/A * and/or other materials provided with the distribution. 5203N/A * 3. Neither the name of the copyright holder nor the names of its contributors 5203N/A * may be used to endorse or promote products derived from this software 5203N/A * without specific prior written permission. 5203N/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 5680N/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 5680N/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 5203N/A * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY 5203N/A * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 5680N/A * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 5680N/A * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 5203N/A * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5203N/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 6921N/A * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5680N/A/* Extent of all psif enums */ 6921N/A};
/* enum psif_enum_extent [16 bits] */ 7295N/A /* Padding out to required bits allocated */ 7295N/A};
/* enum psif_port_speed [ 8 bits] */ 7295N/A/** Bits describing the cause(s) for EPSC to have entered degraded mode 7295N/A * response to `EPSC_QUERY_DEGRADED_MODE` and `psif_eq_entry::event_data` 7295N/A/**< degrade cause: no GUID programmed or not readable */ 5203N/A/**< degrade cause: invalid function name in VPD */ 5203N/A/**< degrade cause: HW not supported by FW */ 7295N/A/**< degrade cause: failed MDIO access */ 7295N/A/**< degrade cause: modify QP timeout */ 5208N/A/**< degrade cause: Virtualization mode reconfigured, reset needed */ 5203N/A/**< degrade cause: no credits for sending multicast packets */ 6921N/A /* Padding out to required bits allocated */ 6921N/A};
/* enum psif_epsc_degrade_cause [ 5 bits] */ 5203N/A};
/* enum psif_mmu_translation [ 3 bits] */ * Enumeration for the different supported page sizes. XXX: Define the page };
/* enum psif_page_size [ 4 bits] */ * These are the different work request opcodes supported by PSIF. * PSIF_WR_ENTER_SQ_MODE and PSIF_WR_CANCEL_CMD are special opcodes only used * when writing to a special offset of the VCBs. RQS must check that the * PSIF_WR_SEND_EPS and PSIF_WR_SEND_EPS_DR really comes from the EPS. CBU * must report the source of a WR to RQS. };
/* enum psif_wr_type [ 8 bits] *//* Port number the IB packet is transimitted on. */ };
/* enum psif_port [ 1 bits] */ * Enumeration for using AHA or not. When set, AHA should be used instead of * information from the QP state in appropriate places. };
/* enum psif_use_ah [ 1 bits] */ * Indicating if this QP is configured as a high bandwidth or a low latency };
/* enum psif_tsu_qos [ 1 bits] */ * Completion entry opcode indicating what type of request this completion };
/* enum psif_wc_opcode [ 8 bits] *//* Completion status for this completion. */ /* Padding out to required bits allocated */ };
/* enum psif_wc_status [ 8 bits] *//* TSU Service level required in the QP and WR */ /* Dataplane traffic separated in 4 TSLs */ /* TSL for privelidge QP */ /* Strapped down TSL for testing */ };
/* enum psif_tsl_qp_wr [ 4 bits] *//* MMU table level definition * If page level is not applicable it should be set to PAGE_LEVEL0 * Values beyond PAGE_LEVEL4 (5-7) are reserved by HW /* PAGE_LEVEL4 is SPARC only ? */ };
/* enum psif_table_level [ 3 bits] */};
/* enum ib_opcode [ 8 bits] */ * This is a ring buffer type defining the type of transaction this };
/* enum psif_rb_type [ 3 bits] */ * Core number for EPS-A.1 PSIF_EPS_A_1 PSIF_EPS_A_2 PSIF_EPS_A_3 };
/* enum psif_eps_a_core [ 2 bits] *//* This is the state this QP is in. */ };
/* enum psif_qp_state [ 3 bits] */ * CMPL_NO_ERROR CMPL_RQS_INVALID_REQUEST_ERR CMPL_RQS_QP_IN_WRONG_STATE_ERR * CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR CMPL_RQS_REQUEST_FENCED_ERR * CMPL_RQS_CMD_FROM_EPS_ERR CMPL_DMA_SGL_RD_ERR CMPL_DMA_PYLD_RD_ERR * CMPL_DMA_SGL_LENGTH_ERR CMPL_DMA_LKEY_ERR };
/* enum psif_cmpl_outstanding_error [ 4 bits] */ * 2 bits (next_opcode) 0x0: No operation in progress 0x1: Expect SEND middle * or last 0x2: Expect RDMA_WR middle or last 0x3: Expect DM_PUT middle or };
/* enum psif_expected_op [ 2 bits] */ * Migration state (migrated, re-arm and armed). XXX: Assign values to the };
/* enum psif_migration [ 2 bits] */ * 3 bits (transport) 0x0: RC - Reliable connection. 0x1: UC - Unreliable * connection. 0x2: RD - Reliable datagram - not supported. 0x3: UD - * Unreliable datagram. 0x4: RSVD1 0x5: XRC - Extended reliable connection. * 0x6: MANSP1 - manufacturer specific opcodes. 0x7: MANSP2 - manufacturer };
/* enum psif_qp_trans [ 3 bits] */};
/* enum psif_bool [ 1 bits] */ * EoIB types enumerated type having these enumerations: EOIB_FULL, * EOIB_PARTIAL, EOIB_QKEY_ONLY, EOIB_NONE. };
/* enum psif_eoib_type [ 2 bits] */ * Communication established state. This gets set when a packet is received * error free when in RTR state. };
/* enum psif_comm_live [ 1 bits] *//* Definitions for the different supported MTU sizes. */ };
/* enum psif_path_mtu [ 3 bits] *//* Enumeration for using GRH or not. When set GRH should be used. */ };
/* enum psif_use_grh [ 1 bits] *//* Enumeration for loopback indication NO_LOOPBACK = 0 LOOPBACK = 1. */ };
/* enum psif_loopback [ 1 bits] *//* Depricated data type... */ };
/* enum psif_pcie_wr_offs [12 bits] */};
/* enum psif_qp_command [ 2 bits] */ /* Padding out to required bits allocated */ };
/* enum psif_sibs_mbox_type [ 8 bits] */ /* Padding out to required bits allocated */ };
/* enum psif_mbox_type [ 8 bits] */ * DMA Validation Key states. The valid states are: PSIF_DMA_KEY_INVALID=0 * PSIF_DMA_KEY_FREE = 1 PSIF_DMA_KEY_VALID = 2 PSIF_DMA_KEY_MMU_VALID };
/* enum psif_dma_vt_key_states [ 2 bits] */ * Flash image types. More comming... /* Padding out to required bits allocated */ };
/* enum psif_flash_image_type [32 bits] *//** \brief SW EQ event type * Software events use `eq_entry::port_flags` for the event type. As this is * limited to 4 bits the special value `PSIF_EVENT_EXTENSION` is used to * indicate that the actual event type is to be found in * `eq_entry::extension_type`. This is done for all enum values larger than /** Event without a reason... */ /** GID table have been updated */ /** PKEY table have been updated by the SM */ /** SM lid have been updated by master SM */ /** The SMs SL have changed */ /** New master SM - client must reregister */ /** vHCA have been assigned a new LID */ /** Mailbox request handled (only if EPSC_FL_NOTIFY was set in the request) */ /** The real event type value is found in `eq_entry::extension_type` */ /** Host should retrieve the EPS log for persistent storage */ /** Event queue full (replaces the actual event) */ /** FW entered degraded mode */ /** Request a keep-alive message */ /** FW finished flushing MMU */ /* Padding out to required bits allocated */ };
/* enum psif_event [32 bits] */ * Enumerations of error types. The following error types are defined for the * TSU: TSU_NO_ERROR = 8'h0 TSU_IBPR_ICRC_ERR TSU_IBPR_INVALID_PKEY_ERR * TSU_IBPR_INVALID_QP_ERR TSU_IBPR_VSWITCH_UF_ERR * TSU_IBPR_UNDEFINED_OPCODE_ERR TSU_IBPR_MCAST_NO_GRH_ERR * TSU_IBPR_MCAST_NO_TARGET_ERR TSU_IBPR_INVALID_DGID_ERR TSU_IBPR_BADPKT_ERR * TSU_RCV_QP_INVALID_ERR TSU_RCV_HDR_BTH_TVER_ERR TSU_RCV_HDR_BTH_QP_ERR * TSU_RCV_HDR_GRH_ERR TSU_RCV_HDR_PKEY_ERR TSU_RCV_HDR_QKEY_ERR * TSU_RCV_HDR_LID_ERR TSU_RCV_HDR_MAD_ERR TSU_RCV_EOIB_MCAST_ERR * TSU_RCV_EOIB_BCAST_ERR TSU_RCV_EOIB_UCAST_ERR TSU_RCV_EOIB_FRAGMENT_ERR * TSU_RCV_EOIB_RUNTS_ERR TSU_RCV_EOIB_OUTER_VLAN_ERR * TSU_RCV_EOIB_VLAN_TAG_ERR TSU_RCV_EOIB_VID_ERR TSU_RCV_MCAST_DUP_ERR * TSU_RCV_ECC_ERR TSU_DSCR_RESPONDER_RC_PSN_ERR * TSU_DSCR_RESPONDER_RC_DUPLICATE TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR * TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR * TSU_DSCR_RESPONDER_RC_DMALEN_ERR TSU_DSCR_RESPONDER_XRC_PSN_ERR * TSU_DSCR_RESPONDER_XRC_DUPLICATE TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR * TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR * TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR TSU_DSCR_RESPONDER_XRC_DMALEN_ERR * TSU_DSCR_RESPONDER_UC_PSN_ERR TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR * TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR * TSU_DSCR_RESPONDER_UC_DMALEN_ERR TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR * TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR * TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR * TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR * TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR * TSU_DSCR_XRCETH_ERR TSU_DSCR_RQ_INVALID_ERR TSU_DSCR_RQ_PD_CHECK_ERR * TSU_DSCR_RQ_EMPTY_ERR TSU_DSCR_RQ_IN_ERROR_ERR * TSU_DSCR_TRANSLATION_TYPE_ERR TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR * TSU_DSCR_PCIE_ERR TSU_DSCR_ECC_ERR TSU_RQH_PCIE_ERR TSU_RQH_SGL_LKEY_ERR * TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR TSU_RQH_ECC_ERR TSU_VAL_DUPLICATE_WITH_ERR * TSU_VAL_RKEY_VLD_ERR TSU_VAL_RKEY_ADDR_RANGE_ERR TSU_VAL_RKEY_ACCESS_ERR * TSU_VAL_RKEY_PD_ERR TSU_VAL_RKEY_RANGE_ERR TSU_VAL_LKEY_VLD_ERR * TSU_VAL_LKEY_ADDR_RANGE_ERR TSU_VAL_LKEY_ACCESS_ERR TSU_VAL_LKEY_PD_ERR * TSU_VAL_LKEY_RANGE_ERR TSU_VAL_TRANSLATION_TYPE_ERR TSU_VAL_PCIE_ERR * TSU_VAL_ECC_ERR TSU_MMU_DUPLICATE_WITH_ERR TSU_MMU_PTW_ERR TSU_MMU_UF_ERR * TSU_MMU_AC_ERR TSU_MMU_ECC_ERR TSU_CBLD_CQ_INVALID_ERR * TSU_CBLD_CQ_FULL_ERR TSU_CBLD_CQ_IS_PROXY_ERR * TSU_CBLD_TRANSLATION_TYPE_ERR TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR * TSU_CBLD_ECC_ERR TSU_CBLD_QP_ERR TSU_RQS_CHECKSUM_ERR TSU_RQS_SEQNUM_ERR * TSU_RQS_INVALID_REQUEST_ERR TSU_RQS_QP_IN_WRONG_STATE_ERR * TSU_RQS_STOP_TIMER_ERR TSU_RQS_CMD_FROM_EPS_ERR TSU_RQS_SQ_FLUSH_ERR * TSU_RQS_SMP_NOT_AUTH_ERR TSU_RQS_REQUEST_FENCED_ERR * TSU_RQS_MAX_OUTSTANDING_REACHED_ERR TSU_RQS_ECC_ERR * TSU_RQS_EOIB_QKEY_VIOLATION TSU_RQS_IPOIB_QKEY_VIOLATION * TSU_RQS_EOIB_MODE_VIOLATION TSU_RQS_MISCONFIGURED_QP * TSU_RQS_PORT_AUTH_VIOLATION TSU_DMA_SGL_RD_ERR TSU_DMA_PYLD_RD_ERR * TSU_DMA_SGL_LENGTH_ERR TSU_DMA_LKEY_ERR TSU_DMA_RKEY_ERR * TSU_DMA_LSO_PKTLEN_ERR TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR * TSU_DMA_PCIE_ERR TSU_DMA_ECC_ERR TSU_CMPL_PCIE_ERR TSU_CMPL_ECC_ERR * TSU_CMPL_REQUESTER_PSN_ERR TSU_CMPL_REQUESTER_SYNDROME_ERR * TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR TSU_CMPL_REQUESTER_LEN_ERR * TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR TSU_CMPL_REQUESTER_DUPLICATE * TSU_CMPL_RC_IN_ERROR_ERR TSU_CMPL_NAK_RNR_ERR TSU_CMPL_NAK_SEQUENCE_ERR * TSU_CMPL_NAK_INVALID_REQUEST_ERR TSU_CMPL_NAK_REMOTE_ACCESS_ERR * TSU_CMPL_NAK_REMOTE_OPS_ERR TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR * TSU_CMPL_TIMEOUT_ERR TSU_CMPL_IMPLIED_NAK TSU_CMPL_GHOST_RESP_ERR };
/* enum psif_tsu_error_types [ 8 bits] */ * Here are the different EPS core IDs: PSIF_EVENT_EPS_A_1 PSIF_EVENT_EPS_A_2 * PSIF_EVENT_EPS_A_3 PSIF_EVENT_EPS_A_4 PSIF_EVENT_EPS_C /* Padding out to required bits allocated */ };
/* enum psif_eps_core_id [ 4 bits] */ * \brief Discriminator for PSIF_QUERY of persistent values * the parameter for the PSIF_QUERY sub-operation EPSC_QUERY_NUM_VFS and EPS_QUERY_JUMBO - set in the index field /* Padding out to required bits allocated */ };
/* enum psif_epsc_query_persistent [32 bits] */ * \brief Discriminator for the PSIF_QUER sub-operation EPSC_QUERY_NUM_VFS - obsolete interface * the parameter for the PSIF_QUERY sub-operation EPSC_QUERY_NUM_VFS - set in the index field /* Padding out to required bits allocated */ };
/* enum psif_epsc_query_num_vfs_mode [32 bits] */ * This enum specifies the state of a UF port's port state machine. It * is used to either force a new state or to report the current state * (via \ref EPSC_QUERY_PORT_1 and \ref EPSC_QUERY_PORT_2). * The externally provided version of the documentation should probably * not contain the information about forcing the state as this is only /** The port is in init state. */ /** The port state is armed. */ /** The port is active. */ /** The port is in deferred active state. */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_port_state [32 bits] */ * \brief Version fixed copy of psif_path_mtu * This enum specifies the path MTU values and is the same as `psif_path_mtu` * found in `psif_verbs.h`. The difference is the data type. The version in * Change version in `psif_verbs.h` to 32b and then drop this one here? /** The MTU is 256 bytes. */ /** The MTU is 512 bytes. */ /** The MTU is 1024 bytes. */ /** The MTU is 2048 bytes. */ /** The MTU is 4069 bytes. */ /** The MTU is 10240 bytes. */ /** Not a specific MTU. */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_path_mtu [32 bits] */ * \brief Monitors handling asynchronous event * This is only found in a structure definition in EPS-A but not used there. /* Padding out to required bits allocated */ };
/* enum psif_epsc_monitor [ 4 bits] *//* Logging completely disabled */ /* Redirect logging to host (dma) */ /* Save the set log mode in the flash */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_log_mode [32 bits] */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_log_level [32 bits] */ * \brief Interrupt sources definitions as bit indexes. * In a mask the active interrupt sources are represented by set bits * `bits[x]=(1 << EPSC_INTR_x)`. These values are defined by hardware. /** Interrupt source is LCSR OR_LOW only with own (HI-)pin. */ /** Interrupt source is message box OR_LOW only with own (HI-)pin. */ /** Interrupt source is XIU OR_LOW only with own (HI-)pin. */ /** Interrupt source is IBU-0 OR_LOW only with own (HI-)pin. */ /** Interrupt source is IBU-1 OR_LOW only with own (HI-)pin. */ /** Interrupt source is NCSI. */ /** Interrupt source is IBPB. */ /** Interrupt source is DMA. */ /** Interrupt source is RQS. */ /** Interrupt source is QPS. */ /** Interrupt source is SQS. */ /** Interrupt source is ERR. */ /** Interrupt source is CMPL. */ /** Interrupt source is VAL. */ /** Interrupt source is RQH. */ /** Interrupt source is DSCR. */ /** Interrupt source is RCV. */ /** Interrupt source is IBPR. */ /** Interrupt source is CBU. */ /** Interrupt source is HOST. */ /** Interrupt source is MMU. */ };
/* enum psif_epsc_interrupt_source [ 5 bits] */ * \brief Interrupt severity levels * This lists the interrupt levels as used by the simulators PRM responder * (psifsim) and cosim. They are not in sync with the values used by EPS /** low interrupt priority */ /** high interrupt priority */ };
/* enum psif_epsc_interrupt_pri [ 2 bits] */ * \brief Query HCA verb response member `atomicity guarantee` values * This enum specifies values possible for the (masked) atomicity guarantee * capability reported in the Query HCA verb (via \ref EPSC_QUERY_DEVICE). * psif_epsc_device_attr_t /** no atomicity guarantee */ /** HCA atomicity guarantee */ /** global atomicity guarantee */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_atomic_cap [32 bits] */ * \brief The EPS-C FW status return codes * \details These error codes are retured from the EPS-C. * psif_epsc_csr_rsp member `status` /** Successful exit status. */ /** Key was rejected by service. */ /** Cannot assign requested address. */ /** Operation not supported on transport endpoint. */ /** No data available. */ /** Operation canceled. */ /** Connection reset by peer. */ /** CSR operation failed. */ /** Modify queue pair error: QP index out of range. */ /** Modify queue pair error: QP is invalid. */ /** Modify queue pair error: failed to change QP attribute. */ /** Modify queue pair error: failed to change QP due to invalid or not matching state. */ /** Modify queue pair error: failed to change QP due to invalid or not matching migration state. */ /** Modify queue pair error: the operation timed out. */ /** DMA test failure in HEAD. */ /** DMA test failure in TAIL. */ /** DMA test failure in PATTERN. */ /** Multicast address already exist. */ /** Address out of range */ /** Parameter out of range */ };
/* enum psif_epsc_csr_status [ 8 bits] */ * \brief Host to EPS operation codes * These operation codes are sent in the \ref psif_epsc_csr_req::opcode member * from the host or a particular core (EPS-Ax/EPS-C) to the mailbox thread in * EPS-C or EPS-Ax in order to specify the request. In addition the operation * codes are used as a selector for the \ref psif_epsc_csr_req::u member of * type \ref psif_epsc_csr_details_t in order to specify the particular * structure if the request requires specific arguments. In some cases the * selected structure defines an own set of sub-operation codes like for * \ref EPSC_QUERY with \ref psif_epsc_query_req_t::op of type * \ref psif_epsc_query_op_t. * Responses are always of type \ref psif_epsc_csr_rsp_t but the meaning of the * members of that structure depend on the operation code. The response state * is \ref EPSC_EADDRNOTAVAIL for all not supported operation codes. * see each of the operation codes * - All codes must be unique and fit into a 8 bit number. * - In order to provide backward compatibility new codes must start from the * current value of \ref EPSC_LAST_OP and the value of \ref EPSC_LAST_OP * must be incremented by the number of newly inserted codes. /** Not a valid operation code. */ /** EPS-C ping over mailbox. */ /** Host patting of EPS-C SW watch-dog. */ /** Initial configuration request per UF. * This request is transferred from the host to the epsc at driver * attach using an encoding of the physical mailbox register. It * is not a legal request on an operational mailbox communication * -------|------------------- * u | \ref psif_epsc_csr_config_t * -------|------------------- * addr | number of event queues (EQ) per UF * The version is encoded this way: * Bits | Version Specifier * 63-48 | PSIF_MAJOR_VERSION * 47-32 | PSIF_MINOR_VERSION * 31-16 | EPSC_MAJOR_VERSION * 15-0 | EPSC_MINOR_VERSION /** Final de-configuration request. * This request is sent from the host driver to indicate that it has * cleaned up all queues and flushed caches associated with the current * UF. It is the last command for that UF and the firmware will take down * the associated virtual links and mailbox settings. For further * communication with that UF the mailbox needs to be set up again via /** Operation code for a general set request. * The request usees the same parameter structure as the \ref EPSC_QUERY * request. Upon receive the mailbox thread first processes the set request * in \ref psif_epsc_csr_query_t::info and then the request in * \ref psif_epsc_csr_query_t::data. Both members are of type * \ref psif_epsc_query_req_t and have their own sub-operation codes in * \ref psif_epsc_query_req_t::op (of type \ref psif_epsc_query_op_t). * Therefore requests instantiating only one set attribute * (i.e. \ref psif_epsc_csr_query_t::info or \ref psif_epsc_csr_query_t::data) * have to set the sub-operation code of the other member to * -------|------------------- * u | \ref psif_epsc_csr_query_t * \ref EPSC_SUCCESS, \ref EPSC_EOPNOTSUPP, \ref EPSC_FAIL /** Operation code for a single CSR write request. * The request is deprecated and will be removed as soon as all * references to this opcode have been cleaned up. * \ref EPSC_EADDRNOTAVAIL /** Operation code for setting an arbitrary CSR. * The request is used mainly for debugging tools and will be either removed * completely or limited to certain register addresses. * -------|------------------- * u | `data[0]` value to write to CSR * -------|---------------------------------------- * addr | the value `addr` from the request * data | the value `data[0]` from the request * \ref EPSC_SUCCESS, \ref EPSC_FAIL * valid register addresses depend on UF /** Old operation code to set up a descriptor base address. * The request is deprecated and will be removed as soon as all * references to this opcode have been cleaned up. * \ref EPSC_EADDRNOTAVAIL /** Operation code to set up a descriptor base address. * With this request the driver configures the descriptor base addresses * of queues, queue pairs and address handles. * -------|------------------------------------------- * addr | Descriptor base address setup CSR address * u | \ref psif_epsc_csr_base_addr_t * \ref EPSC_SUCCESS, \ref EPSC_FAIL /** Operation code to set up an event queue (EQ). * With this request the driver configures an EQ descriptor base address * as well as the associated interrupt. * -------|------------------------------------------- * addr | event queue number * u | \ref psif_epsc_csr_base_addr_t * \ref EPSC_SUCCESS, \ref EPSC_FAIL /* Set Local ID for UF (backdoor) */ /* Set Global ID for UF (backdoor) */ /* Set EoIB MAC address (backdoor) */ /* Reset UF at startup */ /* Modify QP complete w/kick */ /* Get single 64bit register - deprecated */ /* Get one 64bit register using CSR addr */ /** Query HW receive queue. */ /* Non-MAD query device */ /* Non-MAD SMA attribute query */ /* Non-MAD SMA attribute setting */ /* Local MC subscription handling */ /* Handle asynchronous events */ /* Program flash content */ /* new update handling */ /* Get EPS-C version details */ /* Force & read back link speed */ /* EPS-A control & communication (to EPS-C) */ /* EPS-A targeted commands (to EPS-A) */ /* Exercise mmu with access from epsc */ /* Access to EPS-C CLI */ /* IB packet proxy to/from host */ /** Generic query epsc interface. */ /* Setup interrupt coalescing etc. */ /** UF control depends on \ref psif_epsc_csr_uf_ctrl_t::opcode. */ /* Flush MMU and-or PTW Caches */ /* Query PMA counters - alternative path to sending MAD's */ /** VIMMA operations depends on \ref psif_epsc_csr_vimma_ctrl_t::opcode. */ /* EPSC BER (Bit Error Report) Data */ /** EOF marker - must be last and highest in this enum type. */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_opcode [ 8 bits] */ /* Request notification (interrupt) when completion is ready */ /* Privileged QP indicator only valid for query and modify QP */ /* Allways report opertion success */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_flags [ 8 bits] */ * Link states for the virtual HCA and switch. The following onehot encoded * states exist: PSIF_LINK_DISABLED = 1 PSIF_LINK_DOWN = 2 PSIF_LINK_INIT = 4 * PSIF_LINK_ARM = 8 PSIF_LINK_ACTIVE = 16 };
/* enum psif_vlink_state [ 5 bits] */ * EPSC_MODIFY_DEVICE operations /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_modify_device_flags [16 bits] */ * EPSC_MODIFY_PORT_{1,2} operations /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_modify_port_flags [16 bits] */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_epsa_command [32 bits] */ /* Padding out to required bits allocated */ };
/* enum psif_epsa_command [32 bits] */ * \brief Sub-operation codes as used by EPSC_QUERY and EPSC_SET requests. * psif_epsc_query_req member `op` /** If initiated from a EPSC_QUERY this operation code will always return zero * and report success. In case of a intended set request (EPSC_SET) this * operation code ignore the request and return success. /* Obsolete - use EPSC_QUERY_CAP_VCB_{LO HI} */ /* Obsolete - use EPSC_QUERY_CAP_PCB_{LO HI} */ /* Corresponds to register TSU_HOST_INT_CTRL_ADDR */ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_0 */ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_1 */ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_2 */ /* Number of VCBs in PCI lo BAR */ /* Number of VCBs in PCI hi BAR */ /* Number of PCBs mapped to lo BAR VCBs */ /* Number of PCBs mapped to hi BAR VCBs */ * QP number for EPS-C to forward PMA responces to host * psif_epsc_query_req.index = IB port number [1,2] /* date the firmware was programmed in epoch time */ /* date the firmware was built in epoch time */ /* current firmware image number (flash slot) */ /* oneshot firmware image number (flash slot) */ /* autostart firmware image number (flash slot) */ /* bit field encoding why the FW image was booted */ /* Requester - number of bad response errors. */ /* Requester - number of bad response errors. */ /* Requester - number of CQEs with status flushed in error. */ /* Responder - number of CQEs with status flushed in error. */ /* Responder - number of local access errors. */ /* Responder - number of local protection errors. */ /* Requester - number of local length errors. */ /* Responder - number of local length errors. */ /* Requester - number local QP operation error. */ /* Responder - number local QP operation error. */ /* Requester - number of NAK-Sequence Error received. */ /* Responder - number of NAK-Sequence Error sent. */ /* Requester - number of RNR nak retries exceeded errors. */ /* Requester - number of transport retries exceeded errors. */ /* Requester - number of NAK-Remote Access Error received. */ * Responder - number of NAK-Remote Access Error sent. NAK-Remote Operation * Error on: 1. Malformed WQE: Responder detected a malformed Receive Queue * WQE while processing the packet. 2. Remote Operation Error: Responder * encountered an error, (local to the responder), which prevented it from * completing the request. * Requester - number of NAK-Remote Access Error received. R_Key Violation: * Responder detected an invalid R_Key while executing an RDMA Request. * Responder - number of NAK-Remote Access Error sent. R_Key Violation * Responder detected an R_Key violation while executing an RDMA request. * The number of UD packets silently discarded on the receive queue due to * lack of receive descriptor. * The number of UC packets silently discarded on the receive queue due to * lack of receive descriptor. * Requester - number of remote invalid request errors NAK-Invalid Request * on: 1. Unsupported OpCode: Responder detected an unsupported OpCode. 2. * Unexpected OpCode: Responder detected an error in the sequence of OpCodes, * such as a missing Last packet. * Responder - number of remote invalid request errors. NAK may or may not be * sent. 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD * only): Inbound request OpCode was either reserved, or was for a function * not supported by thisQP. (E.g. RDMA or ATOMIC on QP not set up for this). * 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic * operation. 3. Too many RDMA READ or ATOMIC Requests: There were more * requests received and not ACKed than allowed for the connection. 4. Out of * Sequence OpCode, current packet is First or Only: The Responder detected * an error in the sequence of OpCodes; a missing Last packet. 5. Out of * Sequence OpCode, current packet is not First or Only: The Responder * detected an error in the sequence of OpCodes; a missing First packet. 6. * Local Length Error: Inbound Send request message exceeded the responder's * available buffer space. 7. Length error: RDMA WRITE request message * contained too much or too little pay-load data compared to the DMA length * advertised in the first or only packet. 8. Length error: Payload length * was not consistent with the opcode: a: only is between 0 and PMTU bytes b: * (first or middle) equals PMTU bytes c: last is between 1 byte and PMTU * bytes 9. Length error: Inbound message exceeded the size supported by the /* Requester - the number of RNR Naks received. */ /* Responder - the number of RNR Naks sent. */ /* twoshot firmware image number (flash slot) */ /* firmware slot size (available space for an image) */ /* version of boot loader that has started the application */ /* boot loader build date in epoch time format */ /* only used by EPSC_SET mark a PQP CQ ID as clean (WA bug 3769) */ /* Number of TSL supported by FW */ /* Reset CBLD Diag counters. Only used by EPSC_SET */ /* Max QP index used since power-on or host reset - to optimize WA for HW bug 3251 */ /** the UF and QP where modify QP timed out ((uf << 32) | (qp)) */ /** the debug register when modify QP timed out */ /** the bit vector containing the reasons for entering degraded mode */ /** CMPL spin set mode (safe = 1 fast = 0) */ /** VPD serial number (big endian sub-string) - 8 byte offset in query index */ /** VPD manufacturer = = Oracle Corporation - 8 byte offset in query index */ /** VPD product name (big endian sub-string) - 8 byte offset in query index */ /** PSIF TSU SL and QoS mapping for for QP 0 - port number in query index */ /** PSIF TSU SL and QoS mapping for priv QP - port number in query index */ /** PSIF TSU SL and QoS mapping for IB SL 0-7 - port number in query index */ /** PSIF TSU SL and QoS mapping for IB SL 8-15 - port number in query index */ /** MMU static configuration of TA_UPPER_TWELVE bits (SPARC only) */ /** MMU static configuration of PA_UPPER_TWELVE bits (SPARC only) */ /** Number of VFs configured - valid values limited to power-of-two. * For BARE_METAL mode, number of VFs is -1 i.e. not applicable. * PSIF_QUERY index as defined in psif_epsc_query_num_vfs_mode * PSIF_SET index = #VFs for next restart /** Development debug only operation: SET and QUERY the TSU credit * mode setup as defined by epsc_cli: cfg tsu_credit /** Query version on onboard CPLD (Titan only Other platforms will return EPSC_ENODATA) */ /** Query portinfo on exernal port (defined in psif_epsc_query_external_port_info_t) */ /* EOF marker - must be last and highest in this enum type. */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_query_op [32 bits] */ * Valid values for struct psif_epsc_csr_update::opcode /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_update_opcode [16 bits] */ * Flash slot numbers used by e.g. EPSC_QUERY::EPSC_QUERY_FW_CURR_IMG /* Padding out to required bits allocated */ };
/* enum psif_epsc_flash_slot [16 bits] */ * Valid values for struct psif_epsc_csr_update::u::set /* Padding out to required bits allocated */ };
/* enum psif_epsc_update_set [32 bits] */ * Opcodes for psif_epsc_csr_uf_ctrl_t::opcode /** For SMP {en dis}able is the flag param a bitvector for which ports * to update, 0x6 hence indicate P1 and P2. /** For Vlink {dis }connect is the flag param a bitvector for which ports * to update, 0x6 hence indicate P1 and P2. /** Retrieve the highest QP number used by the given UF */ /** Reset the highest QP number cache for the given UF */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_uf_ctrl_opcode [32 bits] */ * \brief Host to VIMMA operation codes * These operation codes are sent in the * \ref psif_epsc_csr_vimma_ctrl_t::opcode member * from the host to the mailbox thread in EPS-C in order to specify the * VIMMA request. In addition the operation * codes are used as a selector for the * \ref psif_epsc_csr_vimma_ctrl_t::u member of * psif_epsc_csr_vimma_ctrl_t in order to specify a particular * set of arguments if the request requires specific arguments. * User of the VIMMA operation codes is the "PSIF SRIOV control API" library * running in Dom0 in user space. This library uses libsif to access the * mailbox. Requests are formed by using the VIMMA operation codes. Response * status is always delivered "inline" as return codes when the libsif API * returns from the mailbox operations. * Additional information retrieval can either be delivered "inline" as long * as space permits inside the mailbox response, OR responses * can also be extended by DMA-ing back response structures to pinned memory * The DMA memory is prepared by the library before executing an opcode * that requires DMA for requested data. * INLINE responses: Response data from VIMMA operation codes are delivered * via libsif to the "PSIF SRIOV control API" as two u64 * parameters: "data" and "info". * These are carried by \ref psif_epsc_csr_rsp_t as part of mailbox response. * The encoding of the "data" and "info" responses depend on the VIMMA operation * code. For code using libsif library, the two u64 response codes "data" * and "info" is overlayed with the union * \ref psif_epsc_csr_vimma_ctrl_resp_inline_u, * and by using the opcode as a selector for the union members, the correct info * from the operation will be found. * DMA responses: The requested data using DMA is delivered back to caller in * pinned memory of appropriate size. A pinned memory block of the maximum sized * response structure will do, and this can be obtained as * sizeof(psif_epsc_csr_vimma_ctrl_resp_dma_u) + appropriate extension for * for some variable arrays if those extend outside of * psif_epsc_csr_vimma_ctrl_resp_dma_uend of some union members. * The opcode just executed will be the selector for the union members. * psif_epsc_csr_vimma_ctrl_t * - In order to provide backward compatibility new codes must be added * at the end of the enum. Deprecated codes can not be removed, but will instead * be responded to with error codes if not supported anymore. /* no DMA or DMA if multiple UFs */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_vimma_ctrl_opcode [32 bits] */ /* VFP used as short for VM Fabric Profile */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_vimma_admmode [16 bits] */ * For response structure to EPSC_PMA_COUNTERS Op. * Common PMA counters for TSU and IBU layers. /** Regular counters - IB Spec chapter 16.1.3.5 */ /** Extended counters if Extended Width supported Regular otherwise */ * If ClassPortInfo:CapabilityMask.PortCountersXmitWaitSupported * set to 1. IB Spec chapter 16.1.3.5 /** Strictly Extended counters - IB Spec Chapter 16.1.4.11 */ /* IB Spec Chapter 16.1.4.1 */ /* Padding out to required bits allocated */ };
/* enum psif_epsc_csr_pma_counters_enum [32 bits] */ * \brief PSIF atomic op requester config values. * psif_epsc_csr_config member `atomic_support` /** PSIF requests atomic operations for IB and SQS. */ /** PSIF requests atomic operations for IB. */ /** PSIF requests atomic operations for SQS. */ /** PSIF doesn't request atomic operations. */ };
/* enum psif_epsc_csr_atomic_op [ 2 bits] */ * For data in response structure of EPSC_BER_DATA Op. /* IBU_P1_LINK_SPEED_ACTIVE_ADDR */ /* IBU_P1_LINK_WIDTH_ACTIVE_ADDR */ /* IBU_P1_PCLINK_ERR_REC_CNT_ADDR */ /* IBU_P1_PCLINK_DOWNED_CNT_ADDR */ };
/* enum psif_epsc_csr_ber_counters_enum [ 3 bits] */ * Completion notification states. Could take any of these values: * PSIF_CQ_UNARMED PSIF_CQ_ARMED_SE PSIF_CQ_ARMED_ALL PSIF_CQ_TRIGGERED };
/* enum psif_cq_state [ 2 bits] */ * This is an indication if the RSS hash was generated with port inputs or };
/* enum psif_rss_hash_source [ 1 bits] */#
endif /* _PSIF_HW_DATA_H */