5810N/A * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. 5810N/A * Redistribution and use in source and binary forms, with or without modification, 5810N/A * are permitted provided that the following conditions are met: 5810N/A * 1. Redistributions of source code must retain the above copyright notice, 5810N/A * this list of conditions and the following disclaimer. 5810N/A * 2. Redistributions in binary form must reproduce the above copyright notice, 5810N/A * this list of conditions and the following disclaimer in the documentation 5810N/A * and/or other materials provided with the distribution. 5810N/A * 3. Neither the name of the copyright holder nor the names of its contributors 5810N/A * may be used to endorse or promote products derived from this software without 5810N/A * specific prior written permission. 5810N/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 5810N/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 5810N/A * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5810N/A * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 5810N/A * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 5810N/A * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5810N/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 5810N/A * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 5810N/A * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 5810N/A * OF THE POSSIBILITY OF SUCH DAMAGE. 5810N/A * Context used by tsu_mmu when performing address translation. The structure 5810N/A * is follows: [63:56] st [55:55] no_snoop [54:53] tph [52:52] ro [51:12] 5810N/A * table_ptr [11:11] th [10:8] translation_type [7:4] page_size [3:3] 5810N/A * wr_access [2:0] table_level 5810N/A /* PCIe relaxed ordering. */ 5810N/A * This is bit [51:12] of the table pointer. The lower twelve bits are always 5810N/A * set to zero. The pointer is pointing to a certain level in the page table 5810N/A * structure. Only applicable if translation_type is set. 5810N/A /* Indicates that the TPH field is valid for the PCIe request. */ 5810N/A * Translation types supported by the PSIF MMU. The modes are: 5810N/A * MMU_PASS_THROUGH MMU_GVA2GPA_MODE, MMU_EPSA_MODE, MMU_EPSC_MODE 5810N/A /* Different supported page sizes. */ 5810N/A /* Set for write access. */ 5810N/A * XXX: Should this be enumerated? XXX: Make sure description is added when 5810N/A/* Descriptor for hardware updated portion of XRC receive queue. */ 5810N/A * Do not evict this entry if this bit is set. There can only be a fixed 5810N/A * number of descriptors with this bit set. XXX: Should this be used as a 5810N/A * hint, or should it be fixed? 5810N/A /* This is a shared receive queue. This is always set for XRCSRQs. */ 5810N/A /* The shared receive queue is in error. */ 5810N/A /* This is indicating how many scatter entries are valid. */ 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A /* This is the shift value to use to find start of the receive queue element. */ 5810N/A * Hardware modified index pointing to the head of the receive queue. TSU is 5810N/A * using this to find the address of the receive queue entry. 5810N/A * If set to something greater than zero, event notification is armed. An 5810N/A * Affiliated Synchronous Event will be sent when number of WQE are less than 5810N/A /* Base address for the receive queue in host memory. */ 5810N/A /* Inlined rq : struct psif_rq_no_pad (256 bits) */ 5810N/A * Log2 size of the receive queue. Maximum number of entries in the receive 5810N/A * queue. This is used for calculating when to wrap the head and tail 5810N/A * Pre-fetch threshold (clog2) indicating when to read the software portion 5810N/A * of the descriptor. If there are less entries than indicated by this 5810N/A * threshold, the software portion of the descriptor must be read. 5810N/A /* The desciptor is valid. */ 5810N/A * XRC domain used to check if this descriptor can be used for the incoming 5810N/A /* Completion queue to use for the incoming packet. */ 5810N/A/* Temp.definition of Shared receive queue content */ 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A * Union between the CQ descriptor ID and VLAN pri. The CQ desc id is only 5810N/A * used for privileged requests, and the vlan_pri is only used for EoIB 5810N/A * This is only used for privileged requests. Completion queue descriptor 5810N/A * index where completions for privileged requests end up. This index points 5810N/A * to the completion queue to be used with this work request. 5810N/A * Generic header for work requests to PSIF. This is present for all packet 5810N/A /* Indicates shat type of request this is. */ 5810N/A * QP sending this request. XXX: Should name be own_qp_num as defined in QP 5810N/A * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or 5810N/A * in the AHA?). If it is unequal, the QP should be put in error. 5810N/A /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */ 5810N/A /* Only applicable to UD. This is an indication that AHA should be used. */ 5810N/A * in the QP State. If it is unequal, the QP should be in error. 5810N/A /* Length (number of bytes of valid data in the collect payload buffer). */ 5810N/A * Send queue sequence number. Used to map request to a particular work 5810N/A * request in the send queue. 5810N/A /* Solicited event bit to be set in IB packet. */ 5810N/A /* Dynamic MTU is enabled for this work request. */ 5810N/A /* L3 checksum enabled when set. This is used for EoIB and IPoIB packets. */ 5810N/A /* L4 checksum enabled when set. This is used for EoIB and IPoIB packets. */ 5810N/A /* Number of SGL entries are valid for this request. */ 5810N/A /* UF used for DR loopback packets. This field is ignored otherwise. */ 5810N/A * EPS tag - used by EPS to associate process and work request. This field is 5810N/A * not used by non-EPS work requests. 5810N/A /* Completion notification identifier. */ 5810N/A /* UF used for all EPS-C QP0/1 packets. This field is ignored otherwise. */ 5810N/A /* Union between VLAN priority and CQ descriptor ID. */ 5810N/A * Checksum used for data protection and consistency between work request and 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A /* QP number for the remote node. */ 5810N/A /* Q-Key for the remote node. */ 5810N/A/* Local address structure. */ 5810N/A /* Local key used to validate the memory region this address is pointing to. */ 5810N/A /* This is the total length of the message. */ 5810N/A /* Index into the Address Handle Array. */ 5810N/A * This header is used for IB send operations. The header is a union and 5810N/A * consists of either a connected mode header or a datagram mode header. The 5810N/A * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM 5810N/A * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT 5810N/A * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND 5810N/A * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO 5810N/A /* Header used for IB send commands using UD mode. */ 5810N/A /* Inlined ud : struct psif_wr_ud_send (224 bits) */ 5810N/A * Max segment size used for PSIF_WR_LSO. This field is not used for other 5810N/A * This header is used for IB send operations. The header is a union and 5810N/A * consists of either a connected mode header or a datagram mode header. The 5810N/A * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM 5810N/A * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT 5810N/A * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND 5810N/A * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO 5810N/A * Reserved. XXX: FIX ME - calculation of this field based on constant, not 5810N/A * psif_wr_local_address_header as it should. 5810N/A /* Header used with IB send commands using connected mode. */ 5810N/A /* Inlined uc_rc_xrc : struct psif_wr_cm (224 bits) */ 5810N/A * Max segment size used for PSIF_WR_LSO. This field is not used for other 5810N/A * This header is used for IB send operations. The header is a union and 5810N/A * consists of either a connected mode header or a datagram mode header. The 5810N/A * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM 5810N/A * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT 5810N/A * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND 5810N/A * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO 5810N/A /* Header used for IB send commands using UD mode. */ 5810N/A /* Header used with IB send commands using connected mode. */ 5810N/A/* Remote address structure. */ 5810N/A /* Address to the remote side. */ 5810N/A * Remote key used to validate the memory region the associated address is 5810N/A /* For RDMA and DM this is the length to add to dmalen in RETH of IB packet. */ 5810N/A * This header is used for RDMA type operations. The following opcodes are 5810N/A * using this header: PSIF_WR_RDMA_WR PSIF_WR_RDMA_WR_IMM PSIF_WR_RDMA_RD 5810N/A * PSIF_WR_CMP_SWAP PSIF_WR_FETCH_ADD PSIF_WR_MASK_CMP_SWAP 5810N/A * Completion queue sequence number for the completion queue being re-armed. 5810N/A * This is going into the completion for the privileged request. 5810N/A * Send queue sequence number. This is used to map the completion back to a 5810N/A * request in the send queue. 5810N/A * This field is only valid for ring buffer send completions (proxy type send 5810N/A * requests). In all other cases this field is ignored. 5810N/A /* Completion queue descriptor ID which is the source of the event. */ 5810N/A/* Union containing a send or receive completion ID. */ 5810N/A * Receive Queue completion ID. This is the receive queue entry ID found as 5810N/A * part of receive queue entry. 5810N/A * Send Queue completion ID. This contain the send queue sequence number. In 5810N/A * ring buffer send completions this field also conatain a valid EPS tag. 5810N/A /* Completion queue descriptor ID which is the source of the event. */ 5810N/A * Union used for descriptor types used when operations on the descriptors 5810N/A * themselves are done, like invalidation, resizing etc. It can the take the 5810N/A * follwing types: rq_id xrq_id cq_id target_qp 5810N/A * Receive queue descriptor used for the following request: 5810N/A * PSIF_WR_SET_SRQ_LIM: this is the receive queue to set the new limit for. 5810N/A * XRCSRQ descriptor used for the following request: PSIF_WR_SET_XRCSRQ_LIM: 5810N/A * this is the XRCSRQ to set the new limit for. PSIF_WR_INVALIDATE_XRCSRQ: 5810N/A * Completion queue descriptor ID used when operations are done on the CQ 5810N/A * descriptor, no completion is sent to this CQ. This field is valid for 5810N/A * PSIF_WR_INVALIDATE_CQ, PSIF_WR_RESIZE_CQ, PSIF_WR_REQ_CMPL_NOTIFY, 5810N/A * PSIF_WR_CMPL_NOTIFY_RCVD, PSIF_WR_REARM_CMPL_EVENT. 5810N/A * Target QP for PSIF_WR_INVALIDATE_SGL_CACHE command. This field is also 5810N/A * valid for PSIF_WR_GENERATE_COMPLETION, then this is the QP number put in 5810N/A * This header is used for privileged operations. The following opcodes are 5810N/A * using this header: PSIF_WR_INVALIDATE_LKEY PSIF_WR_INVALIDATE_RKEY 5810N/A * PSIF_WR_INVALIDATE_BOTH_KEYS PSIF_WR_INVALIDATE_TLB PSIF_WR_RESIZE_CQ 5810N/A * PSIF_WR_SET_SRQ_LIM PSIF_WR_SET_XRCSRQ_LIM PSIF_WR_REQ_CMPL_NOTIFY 5810N/A * PSIF_WR_CMPL_NOTIFY_RCVD PSIF_WR_REARM_CMPL_EVENT 5810N/A * PSIF_WR_GENERATE_COMPLETION PSIF_WR_INVALIDATE_RQ PSIF_WR_INVALIDATE_CQ 5810N/A * PSIF_WR_INVALIDATE_XRCSRQ PSIF_WR_INVALIDATE_SGL_CACHE 5810N/A /* PSIF_WR_GENERATE_COMPLETION: This is the WC ID to put in the completion. */ 5810N/A * PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in the 5810N/A * TLB. PSIF_WR_RESIZE_CQ: this is the new address of the CQ. 5810N/A * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in 5810N/A * PSIF_WR_INVALIDATE_TLB: this is the length for invalidate in the TLB. Only 5810N/A * the lower 16 bits are valid for specifying length of TLB invalidation. 5810N/A * PSIF_WR_RESIZE_CQ: this is the new length of the CQ. 5810N/A /* This is used by the PSIF_WR_SET_SRQ_LIM request. */ 5810N/A * This field is valid for PSIF_WR_GENERATE_COMPLETION. This is the opcode 5810N/A * going into the completion. 5810N/A * This field is valid for PSIF_WR_GENERATE_COMPLETION. This is the 5810N/A * completion status to put in the completion. 5810N/A/* SEND RDMA DM ATOMIC or PRIVILEGED data - depending on opcode. */ 5810N/A /* Descriptor index for XRC SRQ. */ 5810N/A /* Indicates shat type of request this is. */ 5810N/A * QP sending this request. XXX: Should name be own_qp_num as defined in QP 5810N/A * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or 5810N/A * in the AHA?). If it is unequal, the QP should be put in error. 5810N/A /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */ 5810N/A /* Only applicable to UD. This is an indication that AHA should be used. */ 5810N/A * in the QP State. If it is unequal, the QP should be in error. 5810N/A /* Length (number of bytes of valid data in the collect payload buffer). */ 5810N/A * Send queue sequence number. Used to map request to a particular work 5810N/A * request in the send queue. 5810N/A /* Solicited event bit to be set in IB packet. */ 5810N/A /* Dynamic MTU is enabled for this work request. */ 5810N/A /* L3 checksum enabled when set. This is used for EoIB and IPoIB packets. */ 5810N/A /* L4 checksum enabled when set. This is used for EoIB and IPoIB packets. */ 5810N/A /* Number of SGL entries are valid for this request. */ 5810N/A /* UF used for DR loopback packets. This field is ignored otherwise. */ 5810N/A * EPS tag - used by EPS to associate process and work request. This field is 5810N/A * not used by non-EPS work requests. 5810N/A /* Completion notification identifier. */ 5810N/A /* UF used for all EPS-C QP0/1 packets. This field is ignored otherwise. */ 5810N/A /* Union between VLAN priority and CQ descriptor ID. */ 5810N/A /* Inlined common : struct psif_wr_common (192 bits) */ 5810N/A * Checksum used for data protection and consistency between work request and 5810N/A /* Immediate data is only valid when indicated by the opcode. */ 5810N/A /* Manually added spacing to pad out wr */ 5810N/A/** \brief Table of TSU SL and QoS mappings 5810N/A * Driver queries EPS-C for mapping of privileged QP and Infinband SL to 5810N/A * TSU SL and QoS. These values then need to be applied in QP and WR 5810N/A * as well as selecting hi or low PCIe BAR VCB (tqos) to obtain PSIF TSU 5810N/A * internal traffic separation. 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m6 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m5 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m4 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m3 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m2 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m1 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m0 : struct psif_tsl_map_entry (8 bits) */ 5810N/A /* PSIF TSU SL assignmnet */ 5810N/A /* PSIF TSU QoS selection */ 5810N/A /* Inlined m7 : struct psif_tsl_map_entry (8 bits) */ 5810N/A/* Hardware structure indicating what is the next QP. */ 5810N/A /* QP number for the next QP to be processed. */ 5810N/A * If all high, the next pointer is null. If next_null == 1, it is transport 5810N/A/* Response (ACK) data structure used by the response queue descriptor. */ 5810N/A /* ib_bth_psn(24[0] bits)Packet Sequence Number */ 5810N/A /* ib_aeth_syndrome(8[0] bits)Syndrome */ 5810N/A /* ib_aeth_msn(24[0] bits)Message Sequence Number */ 5810N/A/* Response descriptor structure used by the response queue descriptor. */ 5810N/A /* QP and UF to be processed next. */ 5810N/A /* resp_sched_sched_ptr(5[0] bits) * Write pointer type to rdma read and atomic data stored in reqsponse queue 5810N/A * descriptor. Every time an rdma read and atomic is performed, this pointer 5810N/A /* ib_bth_psn(24[0] bits)Packet Sequence Number */ 5810N/A * This bit is set through the doorbell. SW should initialize this bit to 0 5810N/A * when the QP is setup and check this bit plus psif_next = null to ensure SW 5810N/A * can own the RSPQ descriptor 5810N/A /* resp_sched_sched_ptr(5[0] bits) * Write pointer type to rdma read and atomic data stored in reqsponse queue 5810N/A * descriptor. Every time an rdma read and atomic is performed, this pointer 5810N/A /* ib_bth_psn(24[0] bits)Packet Sequence Number */ 5810N/A /* Inlining rspq_ack_data_t tail_dup_ack_aeth due to bondary violation */ 5810N/A /* psn divided in two to mitigate for 64 bit bondary crossing */ 5810N/A /* ib_aeth_syndrome(8[0] bits)Syndrome */ 5810N/A /* ib_aeth_msn(24[0] bits)Message Sequence Number */ 5810N/A/* Temp.definition of content */ 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A/* This is the portion of the descriptor which is updated by software. */ 5810N/A * Index to where elements are added to the send queue by SW. SW is 5810N/A * responsibel for keeping track of how many entries there are in the send 5810N/A * queue. I.e. SW needs to keep track of the head_index so it doesn't 5810N/A * overwrite entries in the send queue which is not yet completed. 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A/* Temp.definition of content */ 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A/* Descriptor used by the send queue scheduler to operate on the send queue. */ 5810N/A /* QP and UF to be processed next. */ 5810N/A * Send queue sequence number used by the SQS to maintain ordering and keep 5810N/A * track of where which send queue elements to fetch. This field is not in 5810N/A * sync with the field in qp_t. This number is typically a little bit before 5810N/A * the number in the qp_t as SQS has to fetch the elements from host memory. 5810N/A * This is also used as tail_index when checking if there are more elements 5810N/A * This bit is set through the doorbell. SW should check this bit plus 5810N/A * psif_next = null to ensure SW can own the SQ descriptor. 5810N/A * Done[0] is set when the last SQ WR is processed (sq_sequence_number == 5810N/A * tail_indx). When done[0] is set, SQS only process the SQ WR when 5810N/A * sq_sequence_number != tail_index. Done[1] is set when done[0] is set and 5810N/A * sq_sequence_number == tail_index. 5810N/A * Timestamp qualifier. This bit is set when retry is entered to the queue 5810N/A * and clear when the timestamp has expired. 5810N/A * Indication if this QP is configured as a low latency or high throughput 5810N/A * quality of service level. 5810N/A * The size between each work queue element in the send queue. This is the 5810N/A * shift value to use in order to find the start of a work queue element. 5810N/A /* Maximum number of SGEs supported by this send queue. */ 5810N/A /* Maximum number of SGEs supported by this send queue. */ 5810N/A /* Maximum inline data length supported by this send queue. */ 5810N/A /* The base address to the send queue. */ 5810N/A /* The MMU context used to get the send queue. */ 5810N/A/* Temp.definition of Send queue content */ 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A/* Temp.definition of the send queue entry cache for the completion block 5810N/A * The only info used by the driver is the size of this struct, 5810N/A * when allocating space for the cache in memory: 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A/* Recveive queue scatter entry. */ 5810N/A /* Base address for this scatter element. */ 5810N/A /* Length of scatter element. */ 5810N/A /* L-Key to be used for this scatter element. */ 5810N/A/* Data type for TSU_RQH_QP_BASE_ADDR - rq scratch pad 5810N/A * Layout as defined by struct psif_rq_entry 5810N/A * Receive queue entry ID. This is added to the receive completion using this 5810N/A /* Scatter entries for this receive queue element. */ 5810N/A/* This is the part of the descriptor which is updated by SW (user space). */ 5810N/A /* Software modified index pointing to the tail reecive entry in host memory. */ 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A * Do not evict this entry if this bit is set. There can only be a fixed 5810N/A * number of descriptors with this bit set. XXX: Should this be used as a 5810N/A * hint, or should it be fixed? 5810N/A /* This is a shared receive queue. This is always set for XRCSRQs. */ 5810N/A /* The shared receive queue is in error. */ 5810N/A /* This is indicating how many scatter entries are valid. */ 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A /* This is the shift value to use to find start of the receive queue element. */ 5810N/A * Hardware modified index pointing to the head of the receive queue. TSU is 5810N/A * using this to find the address of the receive queue entry. 5810N/A * If set to something greater than zero, event notification is armed. An 5810N/A * Affiliated Synchronous Event will be sent when number of WQE are less than 5810N/A /* Base address for the receive queue in host memory. */ 5810N/A /* Hardware updated portion of descriptor. */ 5810N/A /* Inlined hw_no_pad : struct psif_rq_no_pad (256 bits) */ 5810N/A * Log2 size of the receive queue. Maximum number of entries in the receive 5810N/A * queue. This is used for calculating when to wrap the head and tail 5810N/A * Pre-fetch threshold (clog2) indicating when to read the software portion 5810N/A * of the descriptor. If there are less entries than indicated by this 5810N/A * threshold, the software portion of the descriptor must be read. 5810N/A /* The desciptor is valid. */ 5810N/A/* A receive queue entry structure contianing scatter entries. */ 5810N/A * Receive queue entry ID. This is added to the receive completion using this 5810N/A /* Scatter entries for this receive queue element. */ 5810N/A/* This is the portion of the descriptor which is updated by software. */ 5810N/A /* Index to ring buffer elements added by SW. */ 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A * Descriptor entry for a ring buffer. This entry is used to address into the 5810N/A * ring buffer and write the correct entries. This structure is the hardware 5810N/A * updateable part of the RB descriptor. 5810N/A /* Do not evict this entry if this bit is set. */ 5810N/A * This functionality is not valid unless armed is set. If set and incoming 5810N/A * message has SE bit set, an event should be generated to the event queue 5810N/A * indicated by eventq_dscr_id. If not set, an event is sent reqardless of 5810N/A * the value of the SE bit in the incoming message. 5810N/A * When this bit is set, the solicited bit is used in order to send events to 5810N/A /* The descriptor is valid. */ 5810N/A /* rb_size_log2(5[0] bits)Log2 size of the ring buffer. */ 5810N/A * Interrupt channel associated with the event queue. In the PSIF design the 5810N/A * event queues are one to one with interrupt channel. 5810N/A * Log2 size of the ring buffer. The entries are specified as 64B entities. 5810N/A * The number indicates when the tail_index should wrap. If one message is 5810N/A * running over the edge, the message is stored in consecutive entries 5810N/A * outside the ring buffer. max_message_size additional space is added to the 5810N/A /* Index to ring buffer elements to be consumed by HW. */ 5810N/A * VA or PA of the base of the completion queue. If PA the MMU context above 5810N/A * will be a bypass context. Updated by software. The head and tail pointers 5810N/A * can be calculated by the following calculations: Address = base_ptr + 5810N/A * (head * 64B ) Head Pointer and Tail Pointer will use the same MMU context 5810N/A * as the base, and all need to be VA from one address space, or all need to 5810N/A * be PA. In typical use, to allow direct user access to the head and tail 5810N/A * Pre-fetch threshold (clog2) indicating when to read the software portion 5810N/A * of the descriptor. If there are less entries than indicated by this 5810N/A * threshold, the software portion of the descriptor must be read. 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A /* XXX: should this be defined as rb_sequence_number_t? */ 5810N/A * Ring buffer header. A ring buffer header is preceding payload data when 5810N/A * written to host memory. The full message with RB header and payload data 5810N/A * is padded out to become a multiple of 64 bytes. The last 4 bytes of every 5810N/A * 64B data written, will contain the ring buffer sequence number. 5810N/A * Defining the packet type the headers valid for this ring buffer. 5810N/A * PSIF_RB_TYPE_INVALID PSIF_RB_TYPE_DM_PUT PSIF_RB_TYPE_DM_GET_RESP 5810N/A * PSIF_RB_TYPE_RCV_PROXY_COMPLETION 5810N/A * PSIF_RB_TYPE_RCV_PROXY_COMPLETION_AND_DATA 5810N/A * PSIF_RB_TYPE_SEND_PROXY_COMPLETION PSIF_RB_TYPE_SEND_COMPLETION 5810N/A /* Applicable only if this is for EPS-A. */ 5810N/A /* ib_bth_qp_number(24[0] bits)Queue Pair */ 5810N/A /* Length of data associated with this ring buffer header. */ 5810N/A /* sequence number for sanity checking */ 5810N/A * QP state information as laid out in system memory. This structure should 5810N/A * be used to cast the state information stored to a register. 5810N/A * If set, this QP will not be evicted unless QP state is filled up by QPs 5810N/A * When 1, indicates that the receive queue of this QP is a shared receive 5810N/A * queue. This bit is used by tsu_err to classify errors. 5810N/A /* Bit used internally in tsu_cmpl. */ 5810N/A * Indication that a receive queue access is in progress. The bit is set on a 5810N/A * Send First packet and cleared on a Send Last packet. It is used to 5810N/A * indicate if there exists an RQ which can be re-used in the case of UC 5810N/A * This is a multicast QP, and is creating UC multicasts. The is_multicast 5810N/A * bit is based on the destination QP being the multicast QP number 5810N/A * (0xffffff). When the QP is not a UD QP, this bit is forwarded to DMA as 5810N/A * Current number of retired read or atomic requests. Initialze to zero. 5810N/A * Updated by tsu_cmpl every time a read or atomic request is completed. 5810N/A * Current number of outstanding read or atomic requests. Intialize to zero. 5810N/A * It is updated by tsu_rqs every time a new read or atomic requests is 5810N/A /* The size (log2 number of entries) of the send queue. */ 5810N/A /* Send queue extent - the clog2 size between the work requests. */ 5810N/A /* A hit in the set locally spun out of tsu_cmpl is found. */ 5810N/A * When 1, indicates that the receive queue of this QP is a shared receive 5810N/A * queue. This bit is used by tsu_err to classify errors. 5810N/A * Retry counter associated with retries to received NAK or implied NAK. If 5810N/A * it expires, a path migration will be attempted if it is armed, or the QP 5810N/A * will go to error state. Read by tsu_dma and used by tsu_cmpl. 5810N/A * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to 5810N/A * calculate exp_backoff etc.. 5810N/A * The XRC domain is used to check against the XRC domain in the XRCSRQ 5810N/A * descriptor indexed by the request. If the XRC domain matches, the 5810N/A * protection domain in the XRCSRQ descriptor is used instead of the 5810N/A * protection domain associated with the QP. 5810N/A * If the DMA is getting an R-Key violation or an error from PCIe when 5810N/A * fetching data for RDMA read responses, it has to set this bit. When set, 5810N/A * all packets sitting behind the RDMA read on this QP (requests and 5810N/A * responses), must be marked bad so they are not transmitted on IB. 5810N/A * If the DMA is getting an L-Key violation or an error from PCIe when 5810N/A * fetching data for requests, it has to set this bit. When set, all requests 5810N/A * behind must be marked in error and not transmitted on IB. Responses are 5810N/A * This retry tag is updated by the error block when an error occur. If 5810N/A * tsu_rqs reads this retry tag and it is different than the 5810N/A * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of 5810N/A * retry_tag_err when the sq_sequence_number indicates this is the valid 5810N/A * request. The sq_sequence_number has been updated by tsu_err at the same 5810N/A * time the retry_tag_err is updated. 5810N/A * This retry tag is the one used by tsu_rqs and added to the packets sent to 5810N/A * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag 5810N/A * whenever the sq_sequence_number in QP state is equal to the one in the 5810N/A /* R-Key of received multipacket message. */ 5810N/A /* QP number for the remote node. */ 5810N/A /* QP State for this QP. */ 5810N/A * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester 5810N/A * receiving the RNR NAK must wait until the timer has expired before the 5810N/A /* sq_seq(16[0] bits) * Send queue sequence number. This sequence number is used to make sure 5810N/A /* sq_seq(16[0] bits) * Send queue sequence number. This sequence number is used to make sure 5810N/A * Number of bytes received for in progress RDMA RD Responses. This is 5810N/A * Completion queue sequence number. This is used for privileged requests, 5810N/A * where sequence number for one CQ is added to a different completion. 5810N/A * Magic number used to verify use of QP state. This is done by calculating a 5810N/A * checksum of the work request incorporating the magic number. This checksum 5810N/A * is checked against the checksum in the work request. 5810N/A * Sequence number of the last ACK received. Read and written by tsu_cmpl. 5810N/A * Used to verify that the received response packet is a valid response. 5810N/A * This is set by CMPL when there are outstanding requests and a TX error is 5810N/A * received from DMA. It is cleared when the error is sent on. 5810N/A * Bit used for internal use when QP is moved to error and error completions 5810N/A * etc should be sent. Should alway be initialized to zero by SW. 5810N/A * When 1, indicates that we have started a flush retry. SQ or QP in error. 5810N/A * Must be cleared on modify QP - SQErr to RTS. 5810N/A /* When 1 indicates that we have a fence retry outstanding. */ 5810N/A /* When 1 indicates that we have an IB retry outstanding. */ 5810N/A * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key 5810N/A * used on transmit if top bit of Q-Key in WR is set. 5810N/A * Expected packet sequence number: Sequence number on next expected packet. 5810N/A * When 1, indicates that a psn_nak has been sent. Need a valid request in 5810N/A * 2 bits (next_opcode) 0x0: No operation in progress 0x1: Expect SEND middle 5810N/A * or last 0x2: Expect RDMA_WR middle or last 5810N/A /* Index to scatter element of in progress SEND. */ 5810N/A /* Offset within scatter element of in progress SEND. */ 5810N/A /* IB defined capability enable for receiving RDMA RD. */ 5810N/A /* IB defined capability enable for receiving RDMA WR. */ 5810N/A /* IB defined capability enable for receiving Atomic operations. */ 5810N/A /* PSIF specific capability enable for receiving Masked Atomic operations. */ 5810N/A /* Enable capability for RSS. */ 5810N/A * This is a proxy QP. Packets less than a particular size are forwarded to 5810N/A * EPS-A core indicated in the CQ descriptor. 5810N/A * Dynamic MTU is enabled - i.e. incoming requests can have 256B payload 5810N/A * instead of MTU size specified in QP state. 5810N/A * separate scatter elements. 5810N/A /* This is an IB over IB QP. */ 5810N/A /* This is an Ethernet over IB QP. */ 5810N/A * Migration state (migrated, re-arm and armed). Since path migration is 5810N/A * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error 5810N/A * handler also be able to change the path? 5810N/A * TSU quality of service level. Can take values indicating low latency and 5810N/A * high throughput. This is equivalent to high/low BAR when writing doorbells 5810N/A * to PSIF. The qosl bit in the doorbell request must match this bit in the 5810N/A * QP state, otherwise the QP must be put in error. This check only applies 5810N/A * When 1, indicates that a NAK has been for committed_psn+1. Need a valid 5810N/A * request in order to clear the bit. This means receiving a good first/only 5810N/A * packet for the committed_psn+1. 5810N/A * Timeout timestamp - if the timer is running and the timestamp indicates a 5810N/A * timeout, a retry iss issued. 5810N/A * Maximum number of outstanding read or atomic requests allowed by the 5810N/A * remote HCA. Initialized by software. 5810N/A * TSU Service Level used to decide the TSU VL for requests associated with 5810N/A /* The timestamp is valid and will indicate when to time out the request.. */ 5810N/A * An error is found by tsu_cmpl. All packets on this QP is forwarded to 5810N/A * tsu_err until this bit is cleared. The bit is cleared either from QP 5810N/A * cleanup or when tsu_cmpl is receiving is_retry. 5810N/A * Index to scatter element of in progress RDMA RD response. This field does 5810N/A * not need to be written to host memory. 5810N/A * Retry transmit packet sequence number. This is the xmit_psn which should 5810N/A * be used on the first packet of a retry. This is set by tsu_err. When 5810N/A * tsu_dma see that a packet is the first of a retry, it must use this psn as 5810N/A * the xmit_psn and write back xmit_psn as this psn+1. 5810N/A * Transmit packet sequence number. Read and updated by tsu_dma before 5810N/A * sending packets to tsu_ibpb and tsu_cmpl. 5810N/A /* Receive capabilities enabled for this QP. */ 5810N/A /* Inlined rcv_cap : struct psif_qp_rcv_cap (64 bits) */ 5810N/A * This is an index to a receive queue descriptor. The descriptor points to 5810N/A * the next receive queue element to be used. Receive queues are used for IB 5810N/A * Send and RDMA Writes with Immediate data. 5810N/A * When set, RQS should only check that the orig_checksum is equal to magic 5810N/A * number. When not set, RQS should perform the checksum check towards the 5810N/A * When this bit is set, ordering from the send queue is ignored. The 5810N/A * sq_sequence_number check in the RQS is ignored. When the bit is not set, 5810N/A * sq_sequence_number check is done. This bit must be set for QP0 and QP1. 5810N/A * Retry counter associated with RNR NAK retries. If it expires, a path 5810N/A * migration will be attempted if it is armed, or the QP will go to error 5810N/A /* Send Queue RNR retry count initialization value. */ 5810N/A * DMA length found in first packet of inbound request. When last packet is 5810N/A * received, it must be made sure the dmalen and received_bytes are equal. 5810N/A * Number of bytes received of in progress RDMA Write or SEND. The data 5810N/A * received for SENDs and RDMA WR w/Imm are needed for completions. This 5810N/A * should be added to the msg_length. 5810N/A * This is an index to completion queue descriptor. The descriptor points to 5810N/A * a receive completion queue, which may or may not be the same as the send 5810N/A * completion queue. For XRC QPs, this field is written by the CQ descriptor 5810N/A * received by the XRCSRQ on the first packet. This way we don't need to look 5810N/A * up the XRCSRQ for every packet. of the message. 5810N/A * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for 5810N/A * This bit is set by RQS when a TSU_RQS_MAX_OUTSTANDING_REACHED_ERR or 5810N/A * TSU_RQS_REQUEST_FENCED_ERR error is seen and cleared when the first packet 5810N/A * of a retry is seen. While this bit is set, all packets towards DMA shall 5810N/A * have the TSU_RQS_SEQNUM_ERR set. 5810N/A * Flag indicating if the swap in the last atomic swap operation was 5810N/A * performed or not. If swapped, the next RDMA WR should be performed towards 5810N/A * host memory. If not swapped, the next RDMA WR should not be performed 5810N/A * towards host memory, but should be ACK'ed at the IB level as normal. 5810N/A * Set when entering response scheduling mode and cleared when going out of 5810N/A * the mode. We exit this mode when resp_sched_count_sched == 5810N/A * Write pointer for the scheduling of responses. Host is updating and 5810N/A * forwarding this to tsu_sqs. 5810N/A * The counter is compared towards the resp_sched_count_done and incremented 5810N/A * every time a packet is sent to the SQS. 5810N/A * The counter is taken from the response packet and stored. tsu_host is 5810N/A * using this value to decide if we go into or out of response scheduling 5810N/A /* Used for retry handling. */ 5810N/A /* Send capabilities enabled for this QP. */ 5810N/A /* Inlined send_cap : struct psif_qp_snd_cap (64 bits) */ 5810N/A /* This QP is running Ethernet over IB. */ 5810N/A /* This QP is running IP over IB. */ 5810N/A * Dynamic MTU is enabled - i.e. requests can use 256B payload instead of 5810N/A * what is specified in QP state. 5810N/A * The privileged QP is not so privileged, which means that it is not allowed 5810N/A * to perform all privileged requests. 5810N/A /* PSIF specific exponential backoff enable. */ 5810N/A * Offloading type for EoIB. Indicating how the Enforcement of EoIB is done 5810N/A /* This is inverted by the APM module when an event should be sent. */ 5810N/A /* This is inverted by the APM module when an event should be sent. */ 5810N/A * When this bit is not equal to apm_success_event_needed, CBLD should send 5810N/A * an event and set this bit equal to apm_success_event_needed. When the QP 5810N/A * is initialized, this value should be set equal to 5810N/A * apm_success_event_needed. 5810N/A * When this bit is not equal to apm_failed_event_needed, CBLD should send an 5810N/A * event and set this bit equal to apm_failed_event_needed. When the QP is 5810N/A * initialized, this value should be set equal to apm_failed_event_needed. 5810N/A * This is set when the field operation_successful == 0 from HOST. It is used 5810N/A * to make sure that no good completion is to be sent after an atomic error 5810N/A * has occurred. When set, the QP state is moved to error when seen on the 5810N/A * This bit indicates that the QP is now handling responses in a safe manner 5810N/A * with respect to MSN values in the incoming IB packets. 5810N/A * This bit is set when a HOST initiated NAK is sent due to errors when 5810N/A * handling an atomic. When this bit is set, no data is forwarded to EPS or 5810N/A * XIU, and no responses or ACK/NAKs should be forwarded to RQS. 5810N/A * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain 5810N/A * 'spin set floor' and indicate 'all retries completed', respectively. 5810N/A * Request address. In the case of RDMA WR, this is the current write 5810N/A * pointer. In the case of a SEND, this is the address to the receive queue 5810N/A * Offset within scatter element of in progress RDMA RD response. This field 5810N/A * does not need to be written to host memory. 5810N/A /* This PSN is committed - ACKs sent will contain this PSN. */ 5810N/A * Communication established bit. When a packet is received when in RTR 5810N/A * state, this bit should be set, and an asynchronous event should be sent. 5810N/A * Write pointer to atomic data stored in QP. Every time an atomic operation 5810N/A * is performed, the original atomic data is stored in order be to returned 5810N/A * in the event of duplicate atomic. 5810N/A * Committed MSN - the MSN of the newest committed request for this QP. Only 5810N/A * the bottom 16 bits of the MSN is used. 5810N/A * This is an index to send completion queue descriptor. The descriptor 5810N/A * points to a send completion queue, which may or may not be the same as the 5810N/A * Message sequence number used in AETH when sending ACKs. The number is 5810N/A * incremented every time a new inbound message is processed. 5810N/A * This is the eps_tag to be used in the case there is an outstanding error 5810N/A * detected in CMPL. The field is owned CMPL and is used for internal 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A * Path specific information. This is information which can be different for 5810N/A * primary and alternate path. 5810N/A /* Inlined grh : struct psif_grh (192 bits) */ 5810N/A /* ib_grh_flowl(20[0] bits)Flow Label */ 5810N/A /* ib_grh_tclass(8[0] bits)Traffic Class */ 5810N/A /* ib_grh_hoplmt(8[0] bits)Hop Limit */ 5810N/A /* ib_lrh_sl(4[0] bits)Service Level */ 5810N/A /* gid_indx(1[0] bits)GID index indicating which of the UFs two GIDs are used. */ 5810N/A /* ib_lrh_lid(16[0] bits)Local ID */ 5810N/A /* pkey_indx(9[0] bits)Index into the P-Key table. */ 5810N/A * This is the LID path bits. This is used by tsu_ibpb when generating the 5810N/A * SLID in the packet, and it is used by tsu_rcv when checking the DLID. 5810N/A /* ipd(8[0] bits)Inter packet delay. Encoded as specified in IB spec. */ 5810N/A /* timeout(5[0] bits) * Local ACK timeout. This is the exponent used to calculate the delay before 5810N/A * an ACK is declared 'lost' 5810N/A /* Reserved field - used by hardware for error handling on PCIe errors. */ 5810N/A /* QP state information from query. */ 5810N/A /* Primary path information. */ 5810N/A /* Alternate path information. */ 5810N/A /* Manually added spacing to pad outpsif_qp_attributes */ 5810N/A /* Change path req_access error if set. */ 5810N/A /* Change path MTU if set. */ 5810N/A /* Change expected PSN (RQ PSN) if set. */ 5810N/A /* Change primary path if set. */ 5810N/A * Change migration state if set. In some cases this might lead to a path 5810N/A /* Change alternate path if set. */ 5810N/A /* Change the state of the QP when set. */ 5810N/A /* Change the receive capabilities when set. */ 5810N/A /* Change the Q-Key when set. */ 5810N/A /* Change P-Key index if set. */ 5810N/A /* Change the local ack timeout when set. */ 5810N/A /* Change the RNR minimum timer value when set. */ 5810N/A /* Change the retry count when set. */ 5810N/A /* Change the RNR retry count when set. */ 5810N/A /* Change the xmit psn (SQ PSN) when set. */ 5810N/A /* Do not modify unless current state is as indicated in command. */ 5810N/A/* XXX: This is how the QP state in host memory is organized. */ 5810N/A * Path information for path A specific for this QP connection. This field 5810N/A * only makes sense for QPs using connected mode. For datagram mode, this 5810N/A * information comes from the AHA. 5810N/A * Path information for path B specific for this QP connection. This field 5810N/A * only makes sense for QPs using connected mode. For datagram mode, this 5810N/A * information comes from the AHA. 5810N/A/* Temp.definition of collect buffers */ 5810N/A /* Content pt. not defined in ASIC XML */ 5810N/A/* Temp.definition of PCIe WR BAR SQS WR layout = first 8 bytes of WR */ 5810N/A * XXX: Naming - do we want to use opcode for this also, or should we use 5810N/A * QP sending this request. XXX: Should name be own_qp_num as defined in QP 5810N/A * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or 5810N/A * in the AHA?). If it is unequal, the QP should be put in error. 5810N/A /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */ 5810N/A /* Only applicable to UD. This is an indication that AHA should be used. */ 5810N/A * in the QP State. If it is unequal, the QP should be in error. 5810N/A /* Length (number of bytes of valid data in the collect payload buffer). */ 5810N/A * Send queue sequence number. Used to map request to a particular work 5810N/A * request in the send queue. 5810N/A/* Temp.definition of PCIe WR BAR layout */ 5810N/A /* Host posting to EPS-x */ 5810N/A /* EPS-x posting to Host */ 5810N/A /* MBOX_EPS_MAX mbox'es for all the EPS's */ 5810N/A /* (Reset all mailboxes) */ 5810N/A /* Q-Key received in incoming IB packet is checked towards this Q-Key. */ 5810N/A * If the DMA is getting an L-Key violation or an error from PCIe when 5810N/A * fetching data for requests, it has to set this bit. When set, all requests 5810N/A * behind must be marked in error and not transmitted on IB. Responses are 5810N/A * Retry counter associated with RNR NAK retries. If it expires, a path 5810N/A * migration will be attempted if it is armed, or the QP will go to error 5810N/A /* Receive capabilities enabled for this QP. */ 5810N/A /* Inlined rcv_cap : struct psif_qp_rcv_cap (64 bits) */ 5810N/A /* IB defined capability enable for receiving RDMA RD. */ 5810N/A /* IB defined capability enable for receiving RDMA WR. */ 5810N/A /* IB defined capability enable for receiving Atomic operations. */ 5810N/A /* PSIF specific capability enable for receiving Masked Atomic operations. */ 5810N/A /* Enable capability for RSS. */ 5810N/A * This is a proxy QP. Packets less than a particular size are forwarded to 5810N/A * EPS-A core indicated in the CQ descriptor. 5810N/A * Dynamic MTU is enabled - i.e. incoming requests can have 256B payload 5810N/A * instead of MTU size specified in QP state. 5810N/A * separate scatter elements. 5810N/A /* This is an IB over IB QP. */ 5810N/A /* This is an Ethernet over IB QP. */ 5810N/A * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to 5810N/A * calculate exp_backoff etc.. 5810N/A * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester 5810N/A * receiving the RNR NAK must wait until the timer has expired before the 5810N/A /* QP State for this QP. */ 5810N/A * Current number of retired read or atomic requests. Initialze to zero. 5810N/A * Updated by tsu_cmpl every time a read or atomic request is completed. 5810N/A * Receive packet sequence number. Read and updated by tsu_dscr before 5810N/A * passing packets to tsu_rqh. 5810N/A * Migration state (migrated, re-arm and armed). Since path migration is 5810N/A * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error 5810N/A * handler also be able to change the path? 5810N/A * Transmit packet sequence number. Read and updated by tsu_dma before 5810N/A * sending packets to tsu_ibpb and tsu_cmpl. 5810N/A /* Primary path information. */ 5810N/A /* Alternate path information. */ 5810N/A/* QP number UF and command for either modify or query QP. */ 5810N/A /* Command indicating operation - query or modify. */ 5810N/A /* UF this QP belongs to. */ 5810N/A * Port number used for accesses to QP0/1. This field is don't care for all 5810N/A /* Current state the QP must be in to do the modification. */ 5810N/A /* QP number for this operation. */ 5810N/A * This will arm interrupt to be sent when the refcount for the QP index used 5810N/A * have reached zero. It should be used when modify to Reset - when interrupt 5810N/A * is seen, there are no outstanding transactions towards RQs or CQs for the 5810N/A * QP, and it should be safe to take these queues down. 5810N/A /* Manually added spacing to pad out psif_modify_command */ 5810N/A * Structure defining DMA Key Validation entries. This structure is specific 5810N/A * to IB and has information about R/L-Key states. One entry kan represent an 5810N/A * R-Key, an L-Key or both at the same time. This is is decided bythe key 5810N/A /* R-key state for this DMA validation entry */ 5810N/A /* L-key state for this DMA validation entry */ 5810N/A /* pd(24[0] bits)Protection domain. */ 5810N/A /* Remote access rights. Used for R-Key accesses when this is a valid R-Key. */ 5810N/A /* Inlined remote_access : struct psif_dma_vt_mem_access (64 bits) */ 5810N/A /* Write access enabled. */ 5810N/A /* Atomic access enabled. */ 5810N/A * Local access rights. Used for L-Key accesses when this is a valid L-Key. 5810N/A * Must be set correctly by SW so that RD access is always set. 5810N/A /* Inlined local_access : struct psif_dma_vt_mem_access (64 bits) */ 5810N/A /* Write access enabled. */ 5810N/A /* Atomic access enabled. */ 5810N/A * If this bit is set, it means that this memory region is enabled for 5810N/A * conditional RDMA write. The bit must be added to the header at tsu_val and 5810N/A * follow the request towards tsu_host. When tsu_host receives this bit, it 5810N/A * is checking the 'swapped' bit in the QP state in order to decide if the 5810N/A * payload is written to host memory or not. 5810N/A * If this bit is set, the va in the key is used as an offset to the base 5810N/A * address given in this descriptor. 5810N/A /* Length of memory region this validation entry is associated with. */ 5810N/A /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */ 5810N/A * Flash image header format for application image 5810N/A * extention of struct psif_flash_header_all 5810N/A /* byte[0:3] signature is 0xdeadbeef */ 5810N/A /* byte[8:11] SHRDMEM start address */ 5810N/A /* byte[16:19] SHRDMEM ZI base address */ 5810N/A /* byte[28:31] Execution start address */ 5810N/A /* byte[24:27] Storage only used by boot loader */ 5810N/A /* byte[36:39] Flash address base of low vectors */ 5810N/A /* byte[32:35] SHRDMEM address base of low vectors */ 5810N/A /* byte[44:47] FLASH_DATE_LEN > = sizeof(__DATE__) */ 5810N/A /* byte[40:43] Size of low vectors */ 5810N/A /* byte[60:63] FLASH_TIME_LEN > = sizeof(__TIME__) */ 5810N/A /* byte[72:79] FLASH_REV_STR_LEN > = sizeof(REV_STRING) */ 5810N/A /* byte[80:83] checkssum_ptr - this value + 4 equals the size of the immage in bytes */ 5810N/A * Flash image header format 5810N/A * Note: image length is not valid for the boot loader image itself (64k bytes) 5810N/A * struct is always located at offset 0x800 within an image 5810N/A /* byte[0:3] signature of 0xdeadbeef */ 5810N/A /* byte[12:15] image length. 5810N/A The length is defined in bytes and starts at offset 0x0A00 into the image. */ 5810N/A /* byte[8:11] execution base */ 5810N/A/* This is the portion of the descriptor which is updated by software. */ 5810N/A /* Index to event elements consumed by SW. */ 5810N/A * Descriptor entry for an event queue. This entry is used to address into 5810N/A * the event queue and write the correct entries. This structure is the 5810N/A * hardware updateable part of the EQ descriptor. 5810N/A /* Inlined ctrl : struct psif_eq_ctrl (64 bits) */ 5810N/A /* The descriptor is valid. */ 5810N/A * The size between event queue entries. This is the shift value to find the 5810N/A * The size (log2 number of entries) of the event queue. This is used for 5810N/A * calculating when to wrap the head and tail indexes. 5810N/A * Event queue sequence number. This is the sequence number to be used for 5810N/A * this event. When used by a client, it is incremented and written back to 5810N/A * VA or PA of the base of the queue. If PA the MMU context above will be a 5810N/A * bypass context. Updated by software. The head and tail pointers can be 5810N/A * calculated by the following calculations: Address = base_ptr + (head * 5810N/A * ($bits(event_entry_t)/8 ) Head Pointer and Tail Pointer will use the same 5810N/A * MMU context as the base, and all need to be VA from one address space, or 5810N/A * all need to be PA. In typical use, to allow direct user access to the head 5810N/A * and tail pointer VAs are used. 5810N/A /* Index to event queue elements added by HW. */ 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A /* PSIF_EVENT_PATH_MIGRATED. */ 5810N/A /* PSIF_EVENT_COMMUNICATION_ESTABLISHED. */ 5810N/A /* PSIF_EVENT_SRQ_LIMIT_REACHED. */ 5810N/A /* PSIF_EVENT_LAST_WQE_REACHED. */ 5810N/A /* PSIF_EVENT_INVALID_REQUEST_LOCAL_WQ_ERROR. */ 5810N/A /* PSIF_EVENT_LOCAL_ACCESS_VIOLATION_WQ_ERROR. */ 5810N/A /* PSIF_EVENT_PATH_MIGRATION_REQUEST_ERROR. */ 5810N/A /* PSIF_EVENT_XRC_DOMAIN_VIOLATION. */ 5810N/A /* PSIF_EVENT_INVALID_XRCETH. */ 5810N/A /* PSIF_EVENT_SRQ_CATASTROPHIC_ERROR. */ 5810N/A /* PSIF_EVENT_LOCAL_WORK_QUEUE_CATASTROPHIC_ERROR. */ 5810N/A /* PSIF_EVENT_PORT_ACTIVE. */ 5810N/A /* PSIF_EVENT_CLIENT_REGISTRATION. */ 5810N/A /* PSIF_EVENT_PORT_CHANGED. */ 5810N/A /* PSIF_EVENT_LOCAL_CATASTROPHIC_ERROR. */ 5810N/A /* PSIF_EVENT_PORT_ERROR. */ 5810N/A /* PSIF_EVENT_CMPL_NOTIFY. */ 5810N/A * The port_flags are only applicable for port type events. These are not set 5810N/A * from the TSU, but implemented from EPS. 5810N/A /* Error field indicating vendor error when this is an error event. */ 5810N/A /* Completion queue descriptor ID. */ 5810N/A /* vendor_fields(3[0] bits)Should this be an enum? */ 5810N/A /* Receive queue descriptor ID. */ 5810N/A /* Inlined event_status : struct psif_event_status (64 bits) */ 5810N/A /* Completion queue sequence number causing the event to be sent. */ 5810N/A /* Event type if port_flags is PSIF_EVENT_EXTENSION */ 5810N/A /* Additional data on event */ 5810N/A /* Padding out struct bulk */ 5810N/A /* Padding out struct last */ 5810N/A /* sequence number for sanity checking */ 5810N/A /* Owned by epsc runs all the way to 64 bit */ 5810N/A /* Owned by host real offset modulo sz */ 5810N/A /** maximum supported path MTU */ 5810N/A /** currently configured path MTU */ 5810N/A * Query GID response in host memory 5810N/A /* MMU context supplied by driver */ 5810N/A /* Buffer length in bytes */ 5810N/A * CSR Query device structure 5810N/A * The eps-c fw csr to host sw completion 5810N/A * Response to a CSR request 5810N/A /* return status of operation */ 5810N/A /* enum psif_epsc_csr_opcode from request */ 5810N/A /* Sequence number from request */ 5810N/A * \brief Padded base address structure 5810N/A * With this structure the driver provides the information needed be the 5810N/A * firmware to set up queue, queue pair and address handle descriptor base 5810N/A * addresses before they can be used. 5810N/A * psif_epsc_csr_details for \ref EPSC_SET_BASEADDR and 5810N/A * \ref EPSC_SET_BASEADDR_EQ mailbox requests 5810N/A /** base address in host memory to be used for the descriptor */ 5810N/A /** MMU context for `address` */ 5810N/A /** number of entries in the table */ 5810N/A /** size of an entry as log2 value. The address to an entry is calculated 5810N/A * as host_addr + entry_num*(1 << extent_log2) */ 5810N/A /** MSI-X interrupt index only valid for EQ setup */ 5810N/A/* CSR automated type for TSU_QPS_MODIFY_QP_CTRL */ 5810N/A * implemented in hardware - one at a time. EPS implements one register per 5810N/A * UF. When one is written, the modify data is written to modify_qp_data 5810N/A * register before this register is written. The Modify or Query QP command 5810N/A * is autmatically kicked when this register is written. Is one outstanding 5810N/A /* Command indicating operation - query or modify. */ 5810N/A /* UF this QP belongs to. */ 5810N/A * Port number used for accesses to QP0/1. This field is don't care for all 5810N/A /* Current state the QP must be in to do the modification. */ 5810N/A /* QP number for this operation. */ 5810N/A * This will arm interrupt to be sent when the refcount for the QP index used 5810N/A * have reached zero. It should be used when modify to Reset - when interrupt 5810N/A * is seen, there are no outstanding transactions towards RQs or CQs for the 5810N/A * QP, and it should be safe to take these queues down. 5810N/A /* Manually added spacing to pad out psif_modify_command */ 5810N/A /* Inlined cmd_attributes : struct psif_qp_attributes (24 bits) */ 5810N/A /* Manually added spacing to pad outpsif_qp_attributes */ 5810N/A /* Change path req_access error if set. */ 5810N/A /* Change path MTU if set. */ 5810N/A /* Change expected PSN (RQ PSN) if set. */ 5810N/A /* Change primary path if set. */ 5810N/A * Change migration state if set. In some cases this might lead to a path 5810N/A /* Change alternate path if set. */ 5810N/A /* Change the state of the QP when set. */ 5810N/A /* Change the receive capabilities when set. */ 5810N/A /* Change the Q-Key when set. */ 5810N/A /* Change P-Key index if set. */ 5810N/A /* Change the local ack timeout when set. */ 5810N/A /* Change the RNR minimum timer value when set. */ 5810N/A /* Change the retry count when set. */ 5810N/A /* Change the RNR retry count when set. */ 5810N/A /* Change the xmit psn (SQ PSN) when set. */ 5810N/A /* Do not modify unless current state is as indicated in command. */ 5810N/A /* Inlined cmd : struct psif_modify_command (40 bits) */ 5810N/A * int ibv_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, enum 5810N/A * ibv_qp_attr_mask attr_mask, struct ibv_qp_init_attr *init_attr) 5810N/A * qp struct ibv_qp from ibv_create_qp 5810N/A * attr_mask bitmask of items to query (see ibv_modify_qp) 5810N/A * attr struct ibv_qp_attr to be filled in with requested attributes 5810N/A * init_attr struct ibv_qp_init_attr to be filled in with initial 5810N/A * 0 on success, errno on failure. 5810N/A /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */ 5810N/A /* MMU context supplied by driver */ 5810N/A/* CSR automated type for TSU_RQS_P{1,2}_OWN_LID_BASE */ 5810N/A * Own LIDs base and LMC. Potentially all own LID bits come from the QP state 5810N/A * entry. The number of bits to use is based on the LMC. Per UF register. 5810N/A /* ib_lrh_lid(16[0] bits)Local ID */ 5810N/A /* lmc(3[0] bits)LID Mask Control data type. */ 5810N/A/* CSR automated type for TSU_IBPB_P{1,2}_OWN_LID_BASE */ 5810N/A * Own LIDs base and LMC. Potentially all own LID bits come from the QP state 5810N/A * entry. The number of bits to use is based on the LMC. Per UF register. 5810N/A /* ib_lrh_lid(16[0] bits)Local ID */ 5810N/A /* lmc(3[0] bits)LID Mask Control data type. */ 5810N/A/* CSR automated type for TSU_IBPR_P{1,2}_OWN_LID_BASE */ 5810N/A * Own LIDs base and LMC. Potentially all own LID bits come from the QP state 5810N/A * entry. The number of bits to use is based on the LMC. Per UF register. 5810N/A /* Inlined data : struct psif_lid_base (64 bits) */ 5810N/A /* If set GID routing must be used. */ 5810N/A /* Index pt. not used (PSIF.ARCH.03.12 and later) */ 5810N/A /* universal_function(6[0] bits)UF */ 5810N/A * EPSC_QUERY_DEVICE, EPSC_QUERY_PORT, EPSC_QUERY_INFO, 5810N/A /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */ 5810N/A /* MMU context supplied by driver */ 5810N/A * EPSC_QUERY_PKEY, EPSC_QUERY_GID, 5810N/A * EPSC_MC_ATTACH, EPSC_MC_DETACH, EPSC_QUERY_MC 5810N/A /* Will become : psif_eq_event event */ 5810N/A * Test operations : EPSC_TEST_HOST_RD & EPSC_TEST_HOST_WR 5810N/A /* pattern number 0..xxx */ 5810N/A * Flash programming: EPSC_FLASH_START, EPSC_FLASH_RD, 5810N/A * EPSC_FLASH_WR & EPSC_FLASH_STOP 5810N/A * IB packet trace acquire : EPSC_TRACE_ACQUIRE 5810N/A /* Pointer to trace buffer */ 5810N/A /* Buffer offset in bytes */ 5810N/A /* Buffer length in bytes */ 5810N/A /* MMU context supplied by driver */ 5810N/A /* Fields only used by log mode EPSC_LOG_MODE_HOST: 5810N/A Start address of the data area to write to */ 5810N/A /* pointer to a log_stat data area */ 5810N/A /* Length in bytes of the buffer */ 5810N/A /* Address in EPS-A memory */ 5810N/A /* MMU context supplied by driver */ 5810N/A /* Buffer adress in host memory */ 5810N/A * EPSC_CLI_ACCESS - buffer size is assumed to be 4K 5810N/A /* ib_reth_dmalen(32[0] bits)Direct Memory Access Length */ 5810N/A /* ib_bth_qp_number(24[0] bits)Queue Pair */ 5810N/A /* Only valid for UD QPs. */ 5810N/A /* Flags indicating GRH and immediate presence.Only valid if not privileged. */ 5810N/A /* Inlined wc_flags : struct psif_wc_flags (64 bits) */ 5810N/A /* P-Key index from UD packet. */ 5810N/A /* Only valid for UD QPs. */ 5810N/A /* IB portnumber this packet was received on. Only valid if not privileged. */ 5810N/A * SLID taken from the received packet. This is only valid for UD QPs. Only 5810N/A * Path bits (lower 7 bits) taken from the DLID in the received packet. This 5810N/A * is only valid for UD QPs. Only valid if not privileged. 5810N/A /* Value for EPSC_SET operation */ 5810N/A /* Query destin for the response data field */ 5810N/A /* Query destin for the response info field */ 5810N/A /* Set destin for the response data field */ 5810N/A /* Set destin for the response info field */ 5810N/A * EPSC_HOST_INT_COMMON_CTRL - PF only 5810N/A /* Moderate total interrupt generation. How many usecs to delay. */ 5810N/A * EPSC_HOST_INT_CHANNEL_CTRL - PF + VF 5810N/A /* Mask of attributes to set */ 5810N/A /* Set to 1 for adaptive coalescing */ 5810N/A /* rx-to-tx timer scaling factor 2-exponent value */ 5810N/A /* Message rate in messages per second. Low rate threshold. */ 5810N/A /* Message rate in messages per second. High rate threshold. */ 5810N/A /* How many usecs to delay after first packet. */ 5810N/A /* How many usecs to delay after first packet. Low rate value. */ 5810N/A /* How many usecs to delay after first packet. High rate value. */ 5810N/A /* How many usecs to delay after packet. */ 5810N/A /* How many usecs to delay after packet. Low rate value. */ 5810N/A /* How many usecs to delay after packet. High rate value. */ 5810N/A * Flash update: EPSC_UPDATE 5810N/A * UF maintenance: EPSC_UF_CTRL 5810N/A/* CSR automated type for TSU_MMU_FLUSH_CACHES */ 5810N/A/* Flush MMU and-or PTW Caches. */ 5810N/A * Flush MMU and-or PTW Caches: EPSC_FLUSH_CACHES 5810N/A * Structure for EPSC_PMA_COUNTERS 5810N/A * Common structure for virtual port per UF and 5810N/A * external (physical) port per vSwitch. 5810N/A * If MSB is set then it's a physical port number. 5810N/A * Otherwise it's a virtual port number. 5810N/A /* Base address in host memory */ 5810N/A * Bitmask to indicate which counters to clear. Bit 5810N/A * positions are based on the response structure's enum. 5810N/A/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER 5810N/A This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS 5810N/A /* lowest uf index set in array below */ 5810N/A /* highest uf index set in array below */ 5810N/A /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */ 5810N/A/** \brief Struct defintion for vHCA registration details 5810N/A This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS 5810N/A/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_ADMIN_MODE 5810N/A This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS 5810N/A /* lowest uf index set in array below */ 5810N/A /* highest uf index set in array below */ 5810N/A /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */ 5810N/A/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER 5810N/A This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS 5810N/A /* lowest uf index set in array below */ 5810N/A /* highest uf index set in array below */ 5810N/A /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */ 5810N/A/** \brief Defining params for VIMMA opcodes 5810N/A /* all union elements are size 5*u64 */ 5810N/A/** \brief Defines the complete command params for VIMMA opcodes 5810N/A This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_BASIC_CAPS 5810N/A and should never change in an incompatible way. 5810N/A /* VIMMA sub-opcodes triggered by EPSC_VIMMA_CTRL */ 5810N/A /* length of DMA response buffer pinned in host memory */ 5810N/A /* Size 5*64 bits: union of the params for the various opcodes */ 5810N/A /* Place to DMA back longer responses during retrieval */ 5810N/A /* Summing up to 11 * u64 which is total and max */ 5810N/A/* Public API for mailbox requests details */ 5810N/A /* Descriptor base address */ 5810N/A /* Set LID entry (backdoor setup) */ 5810N/A /* Set GID entry (backdoor setup) */ 5810N/A /* Set EoIB MAC address (backdoor setup) */ 5810N/A /* Query HW state of device port or other */ 5810N/A /* Query table info pkey or gid */ 5810N/A /* EPSC_MODIFY_PORT_{1 2} */ 5810N/A /* EPSC_TEST_HOST_RD & EPSC_TEST_HOST_WR */ 5810N/A /* EPSC_FLASH_START EPSC_FLASH_RD EPSC_FLASH_WR & EPSC_FLASH_STOP */ 5810N/A /* Issue commands to serial console */ 5810N/A /* Process incomming (QP 1) packet from host */ 5810N/A /* Send MAD formated WR to host for sending */ 5810N/A /* Setup interrupt control */ 5810N/A /* EPSC_UPDATE (update firmware) */ 5810N/A /* EPSC_UF_CTRL: UF maintenance functions */ 5810N/A /* EPSC_FLUSH_CACHES: Flush MMU and-or PTW Caches */ 5810N/A /* EPSC_VIMMA_CTRL: VIMMA functions */ 5810N/A * The host sw to eps-c fw csr workrequest 5810N/A * The EPSC will post the completion responses for request `#seq_num` 5810N/A * into the completion queue at : 5810N/A * `index = #seq_num % epsc_cq.base_addr.num_entries` 5810N/A * as provided by the initial EPSC_SETUP work request: 5810N/A /* Sequence number - included in response */ 5810N/A /* UF - only valid for UF 0 - must be 0 otherwise */ 5810N/A /* Register offset or port number */ 5810N/A /* Operation specific data */ 5810N/A /** Identical to head to assure 8 byte atomic write */ 5810N/A * Basic configuration data for each UF 5810N/A /** Minor protocol version identifier. */ 5810N/A /** Major protocol version identifier. */ 5810N/A /** Request base address. */ 5810N/A /** Respose base address. */ 5810N/A /** Number of entries in table. */ 5810N/A /** Size of request entry. */ 5810N/A /** Size of response entry. */ 5810N/A /** MMU context for mailbox. */ 5810N/A /** PCI access: setup for sparc memory layout (PF only). */ 5810N/A /** PCI access: enable atomic support from SIF (PF only). */ 5810N/A /** Flush SIF pipeline similar to FLR (PF and VF). */ 5810N/A /** PCI access: Select host endian memory layout (PF only). */ 5810N/A /** VCB access: Exact length for scoreboard data copy (PF only). */ 5810N/A /** Enable all VFs to receive SMPs at startup (PF only). */ 5810N/A /** Connect all vlinks to external port (PF only). */ 5810N/A /** Setup CMPL spin set mode to be fast - default is safe (PF only). */ 5810N/A/* This is the portion of the descriptor which is updated by software. */ 5810N/A /* Index to completion elements added by SW. */ 5810N/A /* Info: Edge padding added (for endian convert) */ 5810N/A * Descriptor entry for a completion queue. This entry is used to address 5810N/A * into the completion queue and write the correct entries. This structure is 5810N/A * the hardware updateable part of the CQ descriptor. 5810N/A /* Do not evict this entry if this bit is set. */ 5810N/A * CQ notification states. The use of these are as defined in the description 5810N/A * of the PSIF interrupt coalsecing scheme. 5810N/A /* The descriptor is valid. */ 5810N/A * Log2 size of the completion queue. Maximum number of entries in the 5810N/A * completion queue. This is used for calculating when to wrap the head and 5810N/A * If set, this completion queue is proxy enabled and should send completions 5810N/A * to EPS core indicated by the eps_core field. 5810N/A * EPS-A core number completions are forwarded to if the proxy_enabled bit is 5810N/A * Pre-fetch threshold (clog2) indicating when to read the software portion 5810N/A * of the descriptor. If there are less entries than indicated by this 5810N/A * threshold, the software portion of the descriptor must be read. 5810N/A * Set by DSCR when CQ overrun async event is sent for this CQ. Not cleared 5810N/A * Interrupt channel associated with the event queue. In the PSIF design the 5810N/A * event queues are one to one with interrupt channel. 5810N/A /* cq_max_msg(32[0] bits)Maximum message size in bytes. */ 5810N/A * VA or PA of the base of the completion queue. If PA the MMU context above 5810N/A * will be a bypass context. Updated by software. The head and tail pointers 5810N/A * can be calculated by the following calculations: Address = base_ptr + 5810N/A * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will 5810N/A * use the same MMU context as the base, and all need to be VA from one 5810N/A * address space, or all need to be PA. In typical use, to allow direct user 5810N/A * access to the head and tail pointer VAs are used. 5810N/A /* Index to completion elements to be consumed by HW. */ 5810N/A * Completion queue sequence number. This is the sequence number to be used 5810N/A * for this completion. When used by a client, it is incremented and written 5810N/A * Union between CQ sequence number and immediate date. CQ sequence number is 5810N/A * only valid for privileged QP requests. 5810N/A * Completion queue sequence number for arming of completion queues. This is 5810N/A * the CQ sequence number for the completion queue which was armed. 5810N/A /* ib_immediate(32[0] bits)Immediate Data */ 5810N/A /* RSS hash. Only valid if not privileged. */ 5810N/A * Packet classification structure for offloading packets. Only valid if not 5810N/A /* Inlined packet_classification : struct psif_packet_classification (64 bits) */ 5810N/A * 0: means LLC_SNAP, 1: means Ethernet type 2. (L2 packet classification.) 5810N/A * This field is applicable for EoIB only. 5810N/A /* Inlined packet_classification_ip_class : struct psif_ip_class (64 bits) */ 5810N/A /* This is set for IPv4 packets only. */ 5810N/A /* This is set for IPv6 packets only. */ 5810N/A /* IPv4 options or IPv6 extension headers present. */ 5810N/A /* Unsupported IPv6 extension headers detected. */ 5810N/A * L3 checksum calculated ok. This is either an IPv6 packet or a correctly 5810N/A * checksummed IPv4 header. Only valid if not privileged. 5810N/A * L4 checksum calculated ok. This is either correct TCP/UDP checksum or UDP 5810N/A * checksum not generated by the transmitter. Only valid if not privileged. 5810N/A * Original UF for QP0/1 packets going to the EPS-C. Only valid if not 5810N/A /* This is set if the packet was a DR packet. Only valid if not privileged. */ 5810N/A /* Inlined hdr_split : struct psif_hdr_split_offload (64 bits) */ 5810N/A * header is added to one scatter element. 5810N/A * Receive Tossed Packet. PSIF thought there was something wrong with this 5810N/A * offloaded packet so it should be tossed. 5810N/A * This bit is set if the incoming request is a conditional RDMA WR w/Imm 5810N/A * which is not written to memory. 5810N/A * Union - offload is valid for normal QPs. For privileged QPs, it is the WC 5810N/A * ID needed to completed if outstanding is set. 5810N/A * This is used if this is a privileged commend INVALIDATE_SGL_CACHE. 5810N/A * Software must figure out if this WC_ID is valid or not. 5810N/A /* This countain offload or PSIF specific infornation. */ 5810N/A * Completion entry. A completion entry written to host memory, will be 5810N/A * padded out to 64 bytes. The last 4 bytes will contain a completion queue 5810N/A * Work queue completion ID. For receive completions this is the entry number 5810N/A * in the receive queue and the receive queue descriptor index. For send 5810N/A * completions this is the sq_sequence number. 5810N/A /* Length of message. Only valid if not privileged. */ 5810N/A /* ib_bth_qp_number(24[0] bits)Queue Pair */ 5810N/A /* Only valid for UD QPs. */ 5810N/A /* P-Key index from UD packet. */ 5810N/A /* Only valid for UD QPs. */ 5810N/A /* IB portnumber this packet was received on. Only valid if not privileged. */ 5810N/A * SLID taken from the received packet. This is only valid for UD QPs. Only 5810N/A * Path bits (lower 7 bits) taken from the DLID in the received packet. This 5810N/A * is only valid for UD QPs. Only valid if not privileged. 5810N/A * Checksum with error. This is not inverted for UDP if zero result from 5810N/A * check. It can be either a full or partial checksum. Only valid if not 5810N/A /* RSS source. Only valid if not privileged. */ 5810N/A * For normal QPs, this is offload information. For privileged QPs, this is 5810N/A * WC ID for in progress RQE. 5810N/A /* Flags indicating GRH and immediate presence.Only valid if not privileged. */ 5810N/A /* Inlined wc_flags : struct psif_wc_flags (64 bits) */ 5810N/A /* Padding out struct bulk */ 5810N/A /* Padding out struct last */ 5810N/A /* sequence number for sanity checking */ 5810N/A/* Compact Base Address Register format. Not for use in register definitions. */ 5810N/A /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */ 5810N/A /* Number of entries in table. */ 5810N/A /* Manually added spacing to pad out base addr */ 5810N/A * clog2_extent used for entry alignment. This field used to calculate 5810N/A * address for a particular entry. Address to an entry is calculated as 5810N/A * follows: host_addr + entry_num*(1 (leftshift) clog2_extent) 5810N/A/* Retry data for one atomic request. Layout per BugZilla 3710 */ 5810N/A /* [255:192] response atomic data */ 5810N/A /* [191:184] padding. always zero */ 5810N/A /* [159] When set to one entry has been used. When set to zero 5810N/A no duplicate has been written in this entry. */ 5810N/A /* [158] This atomic response was in error. */ 5810N/A /* [157:0] Padding. Always set to zero. */ 5810N/A/* Data type for TSU_HOST_QP_BASE_ADDR - atomic replay scratch pad 5810N/A * Layout as of 16 deep atomic queue - elements padded to 32 byte 5810N/A * Address handle array entry used for sending UD packets. The structure 5810N/A * contains information about the destination for a request. 5810N/A /* Inlined grh : struct psif_grh (192 bits) */ 5810N/A /* ib_grh_flowl(20[0] bits)Flow Label */ 5810N/A /* ib_grh_tclass(8[0] bits)Traffic Class */ 5810N/A /* ib_grh_hoplmt(8[0] bits)Hop Limit */ 5810N/A /* ib_lrh_sl(4[0] bits)Service Level */ 5810N/A /* gid_indx(1[0] bits)GID index indicating which of the UFs two GIDs are used. */ 5810N/A /* ib_lrh_lid(16[0] bits)Local ID */ 5810N/A /* ib_lrh_lid_path_bits(7[0] bits)Path bits for the LID. Used as the least signficant bits in a LID */ 5810N/A /* ipd(8[0] bits)Inter packet delay. Encoded as specified in IB spec. */ 5810N/A * The protection domain is checked against the protection domain in the QP 5810N/A * state. As long as they are equal, the QP is allowed to use this AHA entry. 5810N/A/* CSR automated type for TSU_IBPR_P{1,2}_EOIB_MAC1 */ 5810N/A/* Per vHCA + EPS-C ethernet MAC address register. */ 5810N/A#
endif /* _PSIF_HW_DATA_H_BE */