20829N/A const int NJ_MAX_REGISTERS = 30; // L0 - L7, I0 - I5, F2 - F14
20829N/A- const int LARGEST_UNDERRUN_PROT = 32; // largest value passed to underrunProtect
20829N/A+ const int LARGEST_UNDERRUN_PROT = 72; // largest value passed to underrunProtect
20829N/A #define NJ_MAX_STACK_ENTRY 8192
20829N/A #define DECLARE_PLATFORM_REGALLOC()
20829N/A #define DECLARE_PLATFORM_ASSEMBLER() \
20829N/A+ friend class SafeUnderrunProtect; \
20829N/A const static Register argRegs[6], retRegs[1]; \
20829N/A void underrunProtect(int bytes); \
20829N/A bool hardenNopInsertion(const Config& /*c*/) { return false; } \
20829N/A NIns* asm_branchd(bool, LIns*, NIns*); \
20829N/A void Format_4_5(Register rd, int32_t op3, int32_t cond, int32_t opf_cc, int32_t opf_low, Register rs2) { \
20829N/A Format_3A(2, rd, op3, (cond & 0xF) << 14 | (opf_cc & 0x7) << 11 | (opf_low & 0x3F) << 5 | _reg_(rs2)); \
20829N/A- void IntegerOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char *opcode); \
20829N/A- void IntegerOperationI(Register rs1, int32_t simm13, Register rd, int32_t op3, const char *opcode); \
20829N/A- void FloatOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char *opcode); \
20829N/A- void Bicc(int32_t a, int32_t dsp22, int32_t cond, const char *opcode); \
20829N/A- void FBfcc(int32_t a, int32_t dsp22, int32_t cond, const char *opcode); \
20829N/A+ void IntegerOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char* opcode); \
20829N/A+ void IntegerOperationI(Register rs1, int32_t simm13, Register rd, int32_t op3, const char* opcode); \
20829N/A+ void FloatOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char* opcode); \
20829N/A+ void Bicc(int32_t a, int32_t dsp22, int32_t cond, const char* opcode); \
20829N/A+ void FBfcc(int32_t a, int32_t dsp22, int32_t cond, const char* opcode); \
20829N/A void LoadOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char* opcode); \
20829N/A void LoadOperationI(Register rs1, int32_t simm13, Register rd, int32_t op3, const char* opcode); \
20829N/A- void MOVcc(Register rs, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char *opcode); \
20829N/A- void MOVccI(int32_t simm11, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char *opcode); \
20829N/A- void FMOVDcc(Register rs, int32_t opt_cc, Register rd, int32_t cond, const char *opcode); \
20829N/A+ void MOVcc(Register rs, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char* opcode); \
20829N/A+ void MOVccI(int32_t simm11, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char* opcode); \
20829N/A+ void FMOVDcc(Register rs, int32_t opt_cc, Register rd, int32_t cond, const char* opcode); \
20829N/A void ShiftOperation(Register rs1, Register rs2, Register rd, int32_t op3, const char* opcode); \
20829N/A void ShiftOperationI(Register rs1, int32_t shcnt32, Register rd, int32_t op3, const char* opcode); \
20829N/A void Store(Register rd, Register rs1, Register rs2, int32_t op3, const char* opcode); \
20829N/A void STB(Register rd, Register rs1, Register rs2); \
20829N/A void STBI(Register rd, int32_t simm13, Register rs1); \
20829N/A void STB32(Register rd, int32_t immI, Register rs1); \
20829N/A- bool isIMM13(int32_t imm) { return (imm) <= 0xfff && (imm) >= -0x1000; } \
20829N/A- bool isIMM19(int32_t imm) { return (imm) <= 0x3ffff && (imm) >= -0x40000; } \
20829N/A- bool isIMM22(int32_t imm) { return (imm) <= 0x1fffff && (imm) >= -0x200000; } \
20829N/A- void JMP_long_nocheck(int32_t t); \
20829N/A+ static bool isIMM13(int32_t imm) { return (imm) <= 0xfff && (imm) >= -0x1000; } \
20829N/A+ static bool isIMM19(int32_t imm) { return (imm) <= 0x3ffff && (imm) >= -0x40000; } \
20829N/A+ static bool isIMM22(int32_t imm) { return (imm) <= 0x1fffff && (imm) >= -0x200000; } \
20829N/A void MR(Register rd, Register rs);
20829N/A #endif // __nanojit_NativeSparc__
20829N/A JS_SetNativeStackQuota(JSContext *cx, size_t stackSize)
20829N/A+ stackSize = stackSize * 8; // more stack is required on SPARC
20829N/A+ // stackSize = stackSize * 2; // PGO needs more stack, why?
20829N/A+ SafeUnderrunProtect(Assembler* assembler, int n)
20829N/A+ _assembler->underrunProtect(n);
20829N/A+ _priorIns = _assembler->_nIns;
20829N/A+ _priorStart = _assembler->codeStart;
20829N/A+ NanoAssert(_priorStart == _assembler->codeStart);
20829N/A+ NanoAssert((intptr_t)_priorIns - (intptr_t)_assembler->_nIns <= _nprotect);
20829N/A "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",
20829N/A "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7",
20829N/A "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7",
20829N/A inline void Assembler::IntegerOperation
20829N/A- (Register rs1, Register rs2, Register rd, int32_t op3, const char *opcode) {
20829N/A+ (Register rs1, Register rs2, Register rd, int32_t op3, const char* opcode) {
20829N/A Format_3_1(2, rd, op3, rs1, 0, rs2);
20829N/A asm_output("%s %s, %s, %s", opcode, gpn(rs1), gpn(rs2), gpn(rd));
20829N/A inline void Assembler::IntegerOperationI
20829N/A- (Register rs1, int32_t simm13, Register rd, int32_t op3, const char *opcode) {
20829N/A+ (Register rs1, int32_t simm13, Register rd, int32_t op3, const char* opcode) {
20829N/A Format_3_1I(2, rd, op3, rs1, simm13);
20829N/A asm_output("%s %s, %d, %s", opcode, gpn(rs1), simm13, gpn(rd));
20829N/A IntegerOperation(rs1, rs2, rd, 0x3, "xor");
20829N/A- inline void Assembler::Bicc(int32_t a, int32_t dsp22, int32_t cond, const char *opcode) {
20829N/A+ inline void Assembler::Bicc(int32_t a, int32_t dsp22, int32_t cond, const char* opcode) {
20829N/A Format_2_2(a, cond, 0x2, dsp22);
20829N/A- asm_output("%s 0x%x", opcode, _nIns + dsp22 - 1);
20829N/A+ asm_output("%s 0x%x", opcode, _nIns + dsp22);
20829N/A inline void Assembler::BA (int32_t a, int32_t dsp22) { Bicc(a, dsp22, 0x8, "ba"); }
20829N/A asm_output("faddd %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd));
20829N/A- inline void Assembler::FBfcc(int32_t a, int32_t dsp22, int32_t cond, const char *opcode) {
20829N/A+ inline void Assembler::FBfcc(int32_t a, int32_t dsp22, int32_t cond, const char* opcode) {
20829N/A Format_2_2(a, cond, 0x6, dsp22);
20829N/A asm_output("%s 0x%x", opcode, _nIns + dsp22 - 1);
20829N/A inline void Assembler::FloatOperation
20829N/A- (Register rs1, Register rs2, Register rd, int32_t opf, const char *opcode) {
20829N/A+ (Register rs1, Register rs2, Register rd, int32_t opf, const char* opcode) {
20829N/A Format_3_8(2, rd, 0x34, rs1, opf, rs2);
20829N/A asm_output("%s %s, %s, %s", opcode, gpn(rs1), gpn(rs2), gpn(rd));
20829N/A- (Register rs, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char *opcode) {
20829N/A+ (Register rs, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char* opcode) {
20829N/A Format_4_2(rd, 0x2c, cc2, cond, cc1, cc0, rs);
20829N/A asm_output("%s %s, %s", opcode, gpn(rs), gpn(rd));
20829N/A- (int32_t simm11, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char *opcode) {
20829N/A+ (int32_t simm11, int32_t cc2, int32_t cc1, int32_t cc0, Register rd, int32_t cond, const char* opcode) {
20829N/A Format_4_2I(rd, 0x2c, cc2, cond, cc1, cc0, simm11);
20829N/A asm_output("%s 0x%x, %s", opcode, simm11, gpn(rd));
20829N/A inline void Assembler::MOVFGI (int32_t simm11, Register rd) { MOVccI(simm11, 0, 0, 0, rd, 0x6, "movfg"); }
20829N/A inline void Assembler::MOVFGEI(int32_t simm11, Register rd) { MOVccI(simm11, 0, 0, 0, rd, 0xb, "movfge"); }
20829N/A- inline void Assembler::FMOVDcc(Register rs, int32_t opt_cc, Register rd, int32_t cond, const char *opcode) {
20829N/A+ inline void Assembler::FMOVDcc(Register rs, int32_t opt_cc, Register rd, int32_t cond, const char* opcode) {
20829N/A Format_4_5(rd, 0x35, cond, opt_cc, 0x2, rs);
20829N/A asm_output("%s %s, %s", opcode, gpn(rs), gpn(rd));
20829N/A- inline void Assembler::JMP_long_nocheck(int32_t t) {
20829N/A+ inline void Assembler::JMP_long(int32_t t) {
20829N/A+ SafeUnderrunProtect protect(this, 16);
20829N/A+ int32_t tt = ((intptr_t)t - (intptr_t)_nIns + 16) >> 2;
20829N/A- inline void Assembler::JMP_long(int32_t t) {
20829N/A inline void Assembler::JMP_long_placeholder() {
20829N/A- inline int32_t Assembler::JCC(void *t) {
20829N/A+ inline int32_t Assembler::JCC(void* t) {
20829N/A+ SafeUnderrunProtect protect(this, 32);
20829N/A int32_t tt = ((intptr_t)t - (intptr_t)_nIns + 8) >> 2;
20829N/A- void Assembler::JMP(void *t) {
20829N/A+ void Assembler::JMP(void* t) {
20829N/A void Assembler::MR(Register rd, Register rs) {
20829N/A+ SafeUnderrunProtect protect(this, 28);
20829N/A uint32_t frameSize = stackNeeded + kcalleeAreaSize + kLinkageAreaSize;
20829N/A frameSize = BIT_ROUND_UP(frameSize, 8);
20829N/A // The frame size in SAVE is faked. We will still re-caculate SP later.
20829N/A // We can use 0 here but it is not good for debuggers.
20829N/A- void Assembler::asm_align_code() {
20829N/A+ void Assembler::asm_align_code()
20829N/A void Assembler::nFragExit(LIns* guard)
20829N/A SideExit* exit = guard->record()->exit;
20829N/A- Fragment *frag = exit->target;
20829N/A- // Target doesn't exit yet. Emit jump to epilog, and set up to patch later.
20829N/A- JMP_long((intptr_t)_epilogue);
20829N/A+ Fragment* frag = exit->target;
20829N/A+ if (frag && frag->fragEntry) {
20829N/A+ // Target doesn't exit yet. Emit jump to epilog, and set up to patch later.
20829N/A+ JMP_long((intptr_t)_epilogue);
20829N/A // return value is GuardRecord*
20829N/A- NIns *Assembler::genEpilogue()
20829N/A+ NIns* Assembler::genEpilogue()
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A void Assembler::asm_call(LIns* ins)
20829N/A- Register retReg = ( ins->isop(LIR_calld) ? F0 : retRegs[0] );
20829N/A- deprecated_prepResultReg(ins, rmask(retReg));
20829N/A+ Register retReg = (ins->isop(LIR_calld) ? F0 : retRegs[0]);
20829N/A+ prepareResultReg(ins, rmask(retReg));
20829N/A+ evictScratchRegsExcept(rmask(retReg));
20829N/A- // Do this after we've handled the call result, so we don't
20829N/A- // force the call result to be spilled unnecessarily.
20829N/A const CallInfo* ci = ins->callInfo();
20829N/A uint32_t argc = ci->getArgTypes(argTypes);
20829N/A verbose_only(if (_logc->lcbits & LC_Native)
20829N/A bool indirect = ci->isIndirect();
20829N/A+ SafeUnderrunProtect protect(this, 8);
20829N/A+ Register r = findSpecificRegFor(ins->arg(argc), I0);
20829N/A- Register r = findSpecificRegFor(ins->arg(argc), I0);
20829N/A uint32_t offset = kLinkageAreaSize; // start of parameters stack postion.
20829N/A- Register r = findRegFor(ins->arg(j), FpRegs);
20829N/A+ for (int i = 0; i < argc; i++) {
20829N/A+ Register r = findRegFor(ins->arg(j), FpRegs);
20829N/A- // We might be calling a varargs function.
20829N/A- // So, make sure the GPR's are also loaded with
20829N/A- // the value, or the stack contains it.
20829N/A- LDSW32(SP, offset+4, GPRIndex);
20829N/A+ SafeUnderrunProtect protect(this, 48);
20829N/A+ // We might be calling a varargs function.
20829N/A+ // So, make sure the GPR's are also loaded with
20829N/A+ // the value, or the stack contains it.
20829N/A+ LDSW32(SP, offset+4, GPRIndex);
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A+ Register r = findRegFor(ins->arg(j), GpRegs);
20829N/A- Register r = findRegFor(ins->arg(j), GpRegs);
20829N/A- Register r = findSpecificRegFor(ins->arg(j), GPRIndex);
20829N/A+ Register r = findSpecificRegFor(ins->arg(j), GPRIndex);
20829N/A Register Assembler::nRegisterAllocFromSet(RegisterMask set)
20829N/A void Assembler::nPatchBranch(NIns* branch, NIns* location)
20829N/A- *(uint32_t*)&branch[0] &= 0xFFC00000;
20829N/A- *(uint32_t*)&branch[0] |= ((intptr_t)location >> 10) & 0x3FFFFF;
20829N/A- *(uint32_t*)&branch[1] &= 0xFFFFFC00;
20829N/A- *(uint32_t*)&branch[1] |= (intptr_t)location & 0x3FF;
20829N/A+ intptr_t addr_diff = ((intptr_t)location - (intptr_t)branch) >> 2;
20829N/A+ *(uint32_t*)&branch[0] = 0x05000000 | ((intptr_t)location >> 10) & 0x3FFFFF; // sethi ..., %g2
20829N/A+ *(uint32_t*)&branch[1] = 0x8410a000 | (intptr_t)location & 0x3FF; // bset ..., %g2
20829N/A+ *(uint32_t*)&branch[2] = 0x81c00002; // jmp %g2
20829N/A+ *(uint32_t*)&branch[0] = 0x10800000 | (addr_diff & 0x3FFFFF); // ba
20829N/A+ *(uint32_t*)&branch[1] = 0x01000000; // nop
20829N/A+ *(uint32_t*)&branch[2] = 0x01000000; // nop
20829N/A RegisterMask Assembler::nHint(LIns* ins)
20829N/A void Assembler::asm_restore(LIns* i, Register r)
20829N/A+ SafeUnderrunProtect protect(this, 24);
20829N/A- int32_t d = deprecated_disp(i);
20829N/A- void Assembler::asm_store32(LOpcode op, LIns *value, int dr, LIns *base)
20829N/A+ void Assembler::asm_store32(LOpcode op, LIns* value, int dr, LIns* base)
20829N/A- Register rb = getBaseReg(base, dr, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 20);
20829N/A+ Register rb = getBaseReg(base, dr, GpRegs);
20829N/A+ case LIR_sti: STW32(L2, dr, rb); break;
20829N/A+ case LIR_sti2c: STB32(L2, dr, rb); break;
20829N/A+ case LIR_sti2s: STH32(L2, dr, rb); break;
20829N/A- // make sure what is in a register
20829N/A- ra = findRegFor(value, GpRegs);
20829N/A- getBaseReg2(GpRegs, value, ra, GpRegs, base, rb, dr);
20829N/A+ // make sure what is in a register
20829N/A+ ra = findRegFor(value, GpRegs);
20829N/A+ getBaseReg2(GpRegs, value, ra, GpRegs, base, rb, dr);
20829N/A+ case LIR_sti: STW32(ra, dr, rb); break;
20829N/A+ case LIR_sti2c: STB32(ra, dr, rb); break;
20829N/A+ case LIR_sti2s: STH32(ra, dr, rb); break;
20829N/A void Assembler::asm_spill(Register rr, int d, bool quad)
20829N/A+ SafeUnderrunProtect protect(this, 24);
20829N/A+ SafeUnderrunProtect protect(this, 48);
20829N/A Register rb = getBaseReg(base, db, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 48);
20829N/A Register rb = getBaseReg(base, dr, GpRegs);
20829N/A Register rv = ( !value->isInReg()
20829N/A- // if a constant 64-bit value just store it now rather than
20829N/A+ // if a constant 64-bit value just store it now rather than
20829N/A- // value is 64bit struct or int64_t, or maybe a double.
20829N/A- // it may be live in an FPU reg. Either way, don't
20829N/A- // put it in an FPU reg just to load & store it.
20829N/A+ // value is 64bit struct or int64_t, or maybe a double.
20829N/A+ // it may be live in an FPU reg. Either way, don't
20829N/A+ // put it in an FPU reg just to load & store it.
20829N/A- // a) if we know it's not a double, this is right.
20829N/A- // b) if we guarded that its a double, this store could be on
20829N/A- // the side exit, copying a non-double.
20829N/A- // c) maybe its a double just being stored. oh well.
20829N/A+ // a) if we know it's not a double, this is right.
20829N/A+ // b) if we guarded that its a double, this store could be on
20829N/A+ // the side exit, copying a non-double.
20829N/A+ // c) maybe its a double just being stored. oh well.
20829N/A // if value already in a reg, use that, otherwise
20829N/A LOpcode condop = cond->opcode();
20829N/A- return Branches(asm_branchd(branchOnFalse, cond, targ));
20829N/A+ return Branches(asm_branchd(branchOnFalse, cond, targ));
20829N/A- intptr_t tt = ((intptr_t)targ - (intptr_t)_nIns + 8) >> 2;
20829N/A- // !targ means that it needs patch.
20829N/A- if( !(isIMM22((int32_t)tt)) || !targ ) {
20829N/A- JMP_long_nocheck((intptr_t)targ);
20829N/A+ SafeUnderrunProtect protect(this, 32);
20829N/A+ intptr_t tt = ((intptr_t)targ - (intptr_t)_nIns + 8) >> 2;
20829N/A+ // !targ means that it needs patch.
20829N/A+ if( !(isIMM22((int32_t)tt)) || !targ ) {
20829N/A- else //if (condop == LIR_geui)
20829N/A+ case LIR_eqi : BNE (0, tt); break;
20829N/A+ case LIR_lti : BGE (0, tt); break;
20829N/A+ case LIR_lei : BG (0, tt); break;
20829N/A+ case LIR_gti : BLE (0, tt); break;
20829N/A+ case LIR_gei : BL (0, tt); break;
20829N/A+ case LIR_ltui: BCC (0, tt); break;
20829N/A+ case LIR_leui: BGU (0, tt); break;
20829N/A+ case LIR_gtui: BLEU(0, tt); break;
20829N/A+ case LIR_geui: BCS (0, tt); break;
20829N/A+ NanoAssertMsg(0, "asm_branch should never receive this cond opcode");
20829N/A+ case LIR_eqi : BE (0, tt); break;
20829N/A+ case LIR_lti : BL (0, tt); break;
20829N/A+ case LIR_lei : BLE (0, tt); break;
20829N/A+ case LIR_gti : BG (0, tt); break;
20829N/A+ case LIR_gei : BGE (0, tt); break;
20829N/A+ case LIR_ltui: BCS (0, tt); break;
20829N/A+ case LIR_leui: BLEU(0, tt); break;
20829N/A+ case LIR_gtui: BGU (0, tt); break;
20829N/A+ case LIR_geui: BCC (0, tt); break;
20829N/A+ NanoAssertMsg(0, "asm_branch should never receive this cond opcode");
20829N/A- else //if (condop == LIR_geui)
20829N/A NIns* Assembler::asm_branch_ov(LOpcode op, NIns* targ)
20829N/A+ SafeUnderrunProtect protect(this, 32);
20829N/A intptr_t tt = ((intptr_t)targ - (intptr_t)_nIns + 8) >> 2;
20829N/A // !targ means that it needs patch.
20829N/A- if( !(isIMM22((int32_t)tt)) || !targ ) {
20829N/A- JMP_long_nocheck((intptr_t)targ);
20829N/A+ if (!(isIMM22((int32_t)tt)) || !targ) {
20829N/A- if( op == LIR_mulxovi || op == LIR_muljovi )
20829N/A+ if (op == LIR_mulxovi || op == LIR_muljovi)
20829N/A- void Assembler::asm_cmp(LIns *cond)
20829N/A+ void Assembler::asm_cmp(LIns* cond)
20829N/A NanoAssert(lhs->isI() && rhs->isI());
20829N/A- Register r = findRegFor(lhs, GpRegs);
20829N/A- if (c == 0 && cond->isop(LIR_eqi)) {
20829N/A+ Register r = findRegFor(lhs, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A+ if (c == 0 && cond->isop(LIR_eqi)) {
20829N/A- findRegFor2(GpRegs, lhs, ra, GpRegs, rhs, rb);
20829N/A+ findRegFor2(GpRegs, lhs, ra, GpRegs, rhs, rb);
20829N/A void Assembler::asm_condd(LIns* ins)
20829N/A- Register r = deprecated_prepResultReg(ins, AllowableFlagRegs);
20829N/A+ Register r = prepareResultReg(ins, AllowableFlagRegs);
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A LOpcode condop = ins->opcode();
20829N/A NanoAssert(isCmpDOpcode(condop));
20829N/A- else // if (condop == LIR_gtd)
20829N/A+ case LIR_eqd: MOVFEI (1, r); break;
20829N/A+ case LIR_led: MOVFLEI(1, r); break;
20829N/A+ case LIR_ltd: MOVFLI (1, r); break;
20829N/A+ case LIR_ged: MOVFGEI(1, r); break;
20829N/A+ case LIR_gtd: MOVFGI (1, r); break;
20829N/A+ NanoAssertMsg(0, "asm_condd should never receive this cond opcode");
20829N/A void Assembler::asm_cond(LIns* ins)
20829N/A- Register r = deprecated_prepResultReg(ins, AllowableFlagRegs);
20829N/A+ LOpcode condop = ins->opcode();
20829N/A+ Register r = prepareResultReg(ins, AllowableFlagRegs);
20829N/A+ SafeUnderrunProtect protect(this, 20);
20829N/A+ case LIR_eqi : MOVEI (1, r); break;
20829N/A+ case LIR_lti : MOVLI (1, r); break;
20829N/A+ case LIR_lei : MOVLEI (1, r); break;
20829N/A+ case LIR_gti : MOVGI (1, r); break;
20829N/A+ case LIR_gei : MOVGEI (1, r); break;
20829N/A+ case LIR_ltui: MOVCSI (1, r); break;
20829N/A+ case LIR_leui: MOVLEUI(1, r); break;
20829N/A+ case LIR_gtui: MOVGUI (1, r); break;
20829N/A+ case LIR_geui: MOVCCI (1, r); break;
20829N/A+ NanoAssertMsg(0, "asm_cond should never receive this cond opcode");
20829N/A void Assembler::asm_arith(LIns* ins)
20829N/A+ SafeUnderrunProtect protect(this, 28);
20829N/A- Register rb = deprecated_UnknownReg;
20829N/A bool forceReg = (op == LIR_muli || op == LIR_mulxovi || op == LIR_muljovi || !rhs->isImmI());
20829N/A- if ((rb = asm_binop_rhs_reg(ins)) == deprecated_UnknownReg) {
20829N/A- else if ((op == LIR_addi || op == LIR_addxovi || op == LIR_addjovi) && lhs->isop(LIR_allocp) && rhs->isImmI()) {
20829N/A+ } else if ((op == LIR_addi || op == LIR_addxovi || op == LIR_addjovi) && lhs->isop(LIR_allocp) && rhs->isImmI()) {
20829N/A- Register rr = deprecated_prepResultReg(ins, allow);
20829N/A+ Register rr = prepareResultReg(ins, allow);
20829N/A int d = findMemFor(lhs) + rhs->immI();
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A- Register rr = deprecated_prepResultReg(ins, allow);
20829N/A- // if this is last use of lhs in reg, we can re-use result reg
20829N/A- // else, lhs already has a register assigned.
20829N/A- Register ra = ( !lhs->isInReg()
20829N/A+ Register rr = prepareResultReg(ins, allow);
20829N/A+ // If 'lhs' isn't in a register, it can be clobbered by 'ins'.
20829N/A+ Register ra = lhs->isInReg() ? lhs->getReg() : rr;
20829N/A- if (op == LIR_addi || op == LIR_addxovi || op == LIR_addjovi)
20829N/A- else if (op == LIR_subi || op == LIR_subxovi || op == LIR_subjovi)
20829N/A- else if (op == LIR_mulxovi || op == LIR_muljovi) {
20829N/A NanoAssertMsg(0, "Unsupported");
20829N/A- if (op == LIR_addi || op == LIR_addxovi || op == LIR_addjovi)
20829N/A- else if (op == LIR_subi || op == LIR_subxovi || op == LIR_subjovi)
20829N/A NanoAssertMsg(0, "Unsupported");
20829N/A+ findSpecificRegForUnallocated(lhs, ra);
20829N/A void Assembler::asm_neg_not(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, GpRegs);
20829N/A+ Register rr = prepareResultReg(ins, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 16);
20829N/A- // if this is last use of lhs in reg, we can re-use result reg
20829N/A- // else, lhs already has a register assigned.
20829N/A- Register ra = ( !lhs->isInReg()
20829N/A+ // If 'lhs' isn't in a register, it can be clobbered by 'ins'.
20829N/A+ Register ra = lhs->isInReg() ? lhs->getReg() : rr;
20829N/A+ findSpecificRegForUnallocated(lhs, ra);
20829N/A void Assembler::asm_load32(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, GpRegs);
20829N/A+ Register rr = prepareResultReg(ins, GpRegs);
20829N/A Register ra = getBaseReg(base, d, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A+ case LIR_lduc2ui: LDUB32(ra, d, rr); break;
20829N/A+ case LIR_ldus2ui: LDUH32(ra, d, rr); break;
20829N/A+ case LIR_ldi : LDSW32(ra, d, rr); break;
20829N/A+ case LIR_ldc2i : LDSB32(ra, d, rr); break;
20829N/A+ case LIR_lds2i : LDSH32(ra, d, rr); break;
20829N/A NanoAssertMsg(0, "asm_load32 should never receive this LIR opcode");
20829N/A+ if (!base->isop(LIR_allocp) && !base->isInReg()) {
20829N/A+ findSpecificRegForUnallocated(base, ra);
20829N/A void Assembler::asm_cmov(LIns* ins)
20829N/A (op == LIR_cmovd && iftrue->isD() && iffalse->isD()));
20829N/A RegisterMask rm = (op == LIR_cmovi) ? GpRegs : FpRegs;
20829N/A- const Register rr = deprecated_prepResultReg(ins, rm);
20829N/A+ const Register rr = prepareResultReg(ins, rm);
20829N/A const Register iffalsereg = findRegFor(iffalse, rm & ~rmask(rr));
20829N/A case LIR_leui: MOVGU (iffalsereg, rr); break;
20829N/A case LIR_gtui: MOVLEU(iffalsereg, rr); break;
20829N/A case LIR_geui: MOVCS (iffalsereg, rr); break;
20829N/A- debug_only( default: NanoAssert(0); break; )
20829N/A+ NanoAssertMsg(0, "asm_comv should never receive this cond opcode");
20829N/A case LIR_ltd: FMOVDFUGE(iffalsereg, rr); isIcc = false; break;
20829N/A case LIR_ged: FMOVDFUL (iffalsereg, rr); isIcc = false; break;
20829N/A case LIR_gtd: FMOVDFULE(iffalsereg, rr); isIcc = false; break;
20829N/A- debug_only( default: NanoAssert(0); break; )
20829N/A+ NanoAssertMsg(0, "asm_comv should never receive this cond opcode");
20829N/A /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
20829N/A void Assembler::asm_param(LIns* ins)
20829N/A NanoAssertMsg(ins->paramKind() == 0, "savedRegs are not used on SPARC");
20829N/A- if (a < sizeof(argRegs)/sizeof(argRegs[0])) { // i0 - i5
20829N/A+ if (a < sizeof(argRegs) / sizeof(argRegs[0])) { // i0 - i5
20829N/A prepareResultReg(ins, rmask(argRegs[a]));
20829N/A Register r = prepareResultReg(ins, GpRegs);
20829N/A int32_t d = a * sizeof (intptr_t) + kLinkageAreaSize;
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A void Assembler::asm_immi(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, GpRegs);
20829N/A+ Register rr = prepareResultReg(ins, GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 12);
20829N/A void Assembler::asm_immd(LIns* ins)
20829N/A- Register rr = ins->deprecated_getReg();
20829N/A- if (rr != deprecated_UnknownReg)
20829N/A- // @todo -- add special-cases for 0 and 1
20829N/A- NanoAssert((rmask(rr) & FpRegs) != 0);
20829N/A+ SafeUnderrunProtect protect(this, 64);
20829N/A+ // @todo -- add special-cases for 0 and 1
20829N/A+ NanoAssert((rmask(rr) & FpRegs) != 0);
20829N/A // @todo, if we used xor, ldsd, fldz, etc above, we don't need mem here
20829N/A void Assembler::asm_fneg(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, FpRegs);
20829N/A+ Register rr = prepareResultReg(ins, FpRegs);
20829N/A- // lhs into reg, prefer same reg as result
20829N/A- // if this is last use of lhs in reg, we can re-use result reg
20829N/A- // else, lhs already has a different reg assigned
20829N/A- Register ra = ( !lhs->isInReg()
20829N/A+ // If 'lhs' isn't in a register, it can be clobbered by 'ins'.
20829N/A+ Register ra = lhs->isInReg() ? lhs->getReg() : rr;
20829N/A+ findSpecificRegForUnallocated(lhs, ra);
20829N/A void Assembler::asm_fop(LIns* ins)
20829N/A findRegFor2(allow, lhs, ra, allow, rhs, rb);
20829N/A- Register rr = deprecated_prepResultReg(ins, allow);
20829N/A+ Register rr = prepareResultReg(ins, allow);
20829N/A+ case LIR_addd: FADDD(ra, rb, rr); break;
20829N/A+ case LIR_subd: FSUBD(ra, rb, rr); break;
20829N/A+ case LIR_muld: FMULD(ra, rb, rr); break;
20829N/A+ case LIR_divd: FDIVD(ra, rb, rr); break;
20829N/A+ NanoAssertMsg(0, "asm_fop should never receive this opcode");
20829N/A void Assembler::asm_i2d(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, FpRegs);
20829N/A+ Register rr = prepareResultReg(ins, FpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 32);
20829N/A int d = findMemFor(ins->oprnd1());
20829N/A void Assembler::asm_ui2d(LIns* ins)
20829N/A- Register rr = deprecated_prepResultReg(ins, FpRegs);
20829N/A+ Register rr = prepareResultReg(ins, FpRegs);
20829N/A Register rt = registerAllocTmp(FpRegs & ~(rmask(rr)));
20829N/A Register gr = findRegFor(ins->oprnd1(), GpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 72);
20829N/A void Assembler::asm_d2i(LIns* ins) {
20829N/A Register rr = prepareResultReg(ins, GpRegs);
20829N/A Register ra = findRegFor(lhs, FpRegs);
20829N/A+ SafeUnderrunProtect protect(this, 28);
20829N/A void Assembler::asm_nongp_copy(Register r, Register s)
20829N/A NanoAssert((rmask(r) & FpRegs) && (rmask(s) & FpRegs));
20829N/A- NIns * Assembler::asm_branchd(bool branchOnFalse, LIns *cond, NIns *targ)
20829N/A+ NIns* Assembler::asm_branchd(bool branchOnFalse, LIns* cond, NIns* targ)
20829N/A LOpcode condop = cond->opcode();
20829N/A NanoAssert(isCmpDOpcode(condop));
20829N/A+ SafeUnderrunProtect protect(this, 32);
20829N/A intptr_t tt = ((intptr_t)targ - (intptr_t)_nIns + 8) >> 2;
20829N/A // !targ means that it needs patch.
20829N/A if( !(isIMM22((int32_t)tt)) || !targ ) {
20829N/A- JMP_long_nocheck((intptr_t)targ);
20829N/A+ case LIR_eqd: FBNE (0, tt); break;
20829N/A+ case LIR_led: FBUG (0, tt); break;
20829N/A+ case LIR_ltd: FBUGE(0, tt); break;
20829N/A+ case LIR_ged: FBUL (0, tt); break;
20829N/A+ case LIR_gtd: FBULE(0, tt); break;
20829N/A+ NanoAssertMsg(0, "asm_branchd should never receive this cond opcode");
20829N/A+ case LIR_eqd: FBE (0, tt); break;
20829N/A+ case LIR_led: FBLE(0, tt); break;
20829N/A+ case LIR_ltd: FBL (0, tt); break;
20829N/A+ case LIR_ged: FBGE(0, tt); break;
20829N/A+ case LIR_gtd: FBG (0, tt); break;
20829N/A+ NanoAssertMsg(0, "asm_branchd should never receive this cond opcode");
20829N/A- void Assembler::asm_cmpd(LIns *cond)
20829N/A+ void Assembler::asm_cmpd(LIns* cond)
20829N/A- Register Assembler::asm_binop_rhs_reg(LIns* ins)
20829N/A void Assembler::nativePageSetup()
20829N/A Assembler::underrunProtect(int n)
20829N/A+ NanoAssertMsg(n <= LARGEST_UNDERRUN_PROT, "constant LARGEST_UNDERRUN_PROT is too small %d");
20829N/A // This may be in a normal code chunk or an exit code chunk.
20829N/A+ if ((intptr_t)eip - n < (intptr_t)codeStart) {
20829N/A codeAlloc(codeStart, codeEnd, _nIns verbose_only(, codeBytes));
20829N/A- JMP_long_nocheck((intptr_t)eip);
20829N/A findSpecificRegFor(val, retRegs[0]);