2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License (the "License"). 2N/A * You may not use this file except in compliance with the License. 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2N/A * Use is subject to license terms. 2N/A * Contains all the structure definitions and #defines for all Tavor 2N/A * hardware resources and registers. 2N/A * Most of these definitions have been replicated from the tavor_hw.h 2N/A * header file used by the tavor device driver. 2N/A * Ownership flags used to define hardware or software ownership for 2N/A * various Tavor resources 2N/A * Tavor Completion Queue Entries (CQE) 2N/A * Each CQE contains enough information for the software to associate the 2N/A * completion with the Work Queue Element (WQE) to which it corresponds. 2N/A * Note: The following structure is not #define'd with both little-endian 2N/A * and big-endian definitions. This is because each CQE's individual 2N/A * fields are not directly accessed except through the macros defined below. 2N/A * The following defines are used for Tavor CQ error handling. Note: For 2N/A * CQEs which correspond to error events, the Tavor device requires some 2N/A * special handling by software. These defines are used to identify and 2N/A * extract the necessary information from each error CQE, including status 2N/A * code (above), doorbell count, and whether a error completion is for a 2N/A * send or receive work request. 2N/A * These are the defines for the Tavor CQ entry types. They are also 2N/A * specified by the Tavor register specification. They indicate what type 2N/A * of work request is completing (for successful completions). Note: The 2N/A * "SND" or "RCV" in each define is used to indicate whether the completion 2N/A * work request was from the Send work queue or the Receive work queue on 2N/A * the associated QP. 2N/A * These are the defines for the Tavor CQ completion statuses. They are 2N/A * specified by the Tavor register specification. 2N/A * The following macros are used for extracting (and in some cases filling in) 2N/A * information from CQEs 2N/A * Tavor User Access Region (UAR) 2N/A * Tavor doorbells are each rung by writing to the doorbell registers that 2N/A * form a User Access Region (UAR). A doorbell is a write-only hardware 2N/A * register which enables passing information from software to hardware 2N/A * with minimum software latency. A write operation from the host software 2N/A * to these doorbell registers passes information about the HCA resources 2N/A * and initiates processing of the doorbell data. There are 6 types of 2N/A * doorbells in Tavor. 2N/A * "Send Doorbell" for synchronizing the attachment of a WQE (or a chain 2N/A * of WQEs) to the send queue. 2N/A * "RD Send Doorbell" (Same as above, except for RD QPs) is not supported. 2N/A * "Receive Doorbell" for synchronizing the attachment of a WQE (or a chain 2N/A * of WQEs) to the receive queue. 2N/A * "CQ Doorbell" for updating the CQ consumer index and requesting 2N/A * completion notifications. 2N/A * "EQ Doorbell" for updating the EQ consumer index, arming interrupt 2N/A * triggering, and disarming CQ notification requests. 2N/A * "InfiniBlast" (which would have enabled access to the "InfiniBlast 2N/A * buffer") is not supported. 2N/A * Note: The tavor_hw_uar_t below is the container for all of the various 2N/A * doorbell types. Below we first define several structures which make up 2N/A * the contents of those doorbell types. 2N/A * Note also: The following structures are not #define'd with both little- 2N/A * endian and big-endian definitions. This is because each doorbell type 2N/A * is not directly accessed except through a single ddi_put64() operation 2N/A * (see tavor_qp_send_doorbell, tavor_qp_recv_doorbell, tavor_cq_doorbell, 2N/A * or tavor_eq_doorbell) 2N/A/* Max descriptors per Tavor doorbell */ 2N/A/* Default value for use in NOTIFY_CQ doorbell */ 2N/A * Tavor Send Work Queue Element (WQE) 2N/A * A Tavor Send WQE is built of the following segments, each of which is a 2N/A * multiple of 16 bytes. Note: Each individual WQE may contain only a 2N/A * subset of these segments described below (according to the operation type 2N/A * and transport type of the QP). 2N/A * The first 16 bytes of ever WQE are formed from the "Next/Ctrl" segment. 2N/A * This segment contains the address of the next WQE to be executed and the 2N/A * information required in order to allocate the resources to execute the 2N/A * next WQE. The "Ctrl" part of this segment contains the control 2N/A * information required to execute the WQE, including the opcode and other 2N/A * control information. 2N/A * The "Datagram" segment contains address information required in order to 2N/A * form a UD message. 2N/A * The "Bind" segment contains the parameters required for a Bind Memory 2N/A * The "Remote Address" segment is present only in RDMA or Atomic WQEs and 2N/A * specifies remote virtual addresses and RKey, respectively. Length of 2N/A * The "Atomic" segment is present only in Atomic WQEs and specifies 2N/A * Note: The following structures are not #define'd with both little-endian 2N/A * and big-endian definitions. This is because their individual fields are 2N/A * not directly accessed except through macros defined below. 2N/A * Tavor Receive Work Queue Element (WQE) 2N/A * Like the Send WQE, the Receive WQE is built of 16-byte segments. The 2N/A * segment is the "Next/Ctrl" segment (defined below). It is followed by 2N/A * some number of scatter list entries for the incoming message. 2N/A * The format of the scatter-gather list entries is also shown below. For 2N/A * Receive WQEs the "inline_data" field must be cleared (i.e. data segments 2N/A * cannot contain inline data). 2N/A * This bit must be set in the next/ctrl field of all Receive WQEs 2N/A * as a workaround to a Tavor hardware erratum related to having 2N/A * the first 32-bits in the WQE set to zero. 2N/A * The tavor_sw_wqe_dbinfo_t structure is used internally by the Tavor 2N/A * driver to return information (from the tavor_wqe_mlx_build_nextctl() and 2N/A * tavor_wqe_send_build_nextctl() routines) regarding the type of Tavor 2N/A * doorbell necessary. 2N/A * The following macros are used for building each of the individual 2N/A * segments that can make up a Tavor WQE. Note: We try not to use the 2N/A * structures (with their associated bitfields) here, instead opting to 2N/A * build and put 64-bit or 32-bit chunks to the WQEs as appropriate, 2N/A * primarily because using the bitfields appears to force more read-modify- 2N/A * TAVOR_WQE_BUILD_REMADDR - Builds Remote Address Segment using 2N/A * RDMA info from the work request 2N/A * TAVOR_WQE_BUILD_BIND - Builds the Bind Memory Window 2N/A * Segment using bind info from the 2N/A * TAVOR_WQE_LINKNEXT - Links the current WQE to the 2N/A * TAVOR_WQE_LINKFIRST - Links the first WQE on the current 2N/A * chain to the previous WQE 2N/A * The following macro is used to convert WQE address and size into the 2N/A * "wqeaddrsz" value needed in the tavor_wrid_entry_t (see below). 2N/A * The following macros are used to calculate pointers to the Send or Receive 2N/A * WQEs on a given QP, respectively 2N/A * Maximum header before the data bytes when inlining data. 2N/A * "Header" includes the link (nextctrl) struct, a remote address struct 2N/A * (only for RDMA Write, not for Send) and the 32-bit byte count field. 2N/A * Function signatures 2N/A#
endif /* _DAPL_TAVOR_HW_H */