2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License, Version 1.0 only
2N/A * (the "License"). You may not use this file except in compliance
2N/A * with the License.
2N/A *
2N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2N/A * or http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When distributing Covered Code, include this CDDL HEADER in each
2N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A/*
2N/A * Copyright (c) 1999 by Sun Microsystems, Inc.
2N/A * All rights reserved.
2N/A */
2N/A
2N/A#ifndef _RESET_INFO_H
2N/A#define _RESET_INFO_H
2N/A
2N/A#pragma ident "%Z%%M% %I% %E% SMI"
2N/A
2N/A#ifdef __cplusplus
2N/Aextern "C" {
2N/A#endif
2N/A
2N/A/*
2N/A * All of the following data structures and defines come from sun4u server
2N/A * POST. If the data in POST changes, then these structures must reflect
2N/A * those changes.
2N/A */
2N/A
2N/A#include <sys/fhc.h> /* To get MAX_BOARDS constant */
2N/A
2N/A/* BDA bit assignments */
2N/A#define BOARD_PRESENT (1<<0)
2N/A#define BOARD_OK (1<<1)
2N/A#define BOARD_TYPE_MSK (7<<2)
2N/A#define BOARD_TYPE(x) (((x) & BOARD_TYPE_MSK) >> 2)
2N/A
2N/A/* Board state mask and defines */
2N/A#define BD_STATE_MASK 0x3
2N/A#define BD_LPM_FZN 0
2N/A#define BD_ONLINE_FAIL 1
2N/A#define BD_NOT_PRESENT 2
2N/A#define BD_ONLINE_NORMAL 3
2N/A
2N/A/* define CPU 0 fields */
2N/A#define CPU0_PRESENT (1<<8)
2N/A#define CPU0_OK (1<<9)
2N/A#define CPU0_FAIL_CODE_MSK (7<<10)
2N/A
2N/A/* define CPU 1 fields */
2N/A#define CPU1_PRESENT (1<<16)
2N/A#define CPU1_OK (1<<17)
2N/A#define CPU1_FAIL_CODE_MSK (7<<18)
2N/A
2N/A/* supported board types */
2N/A#define CPU_TYPE 0
2N/A#define MEM_TYPE 1 /* CPU/MEM board with only memory */
2N/A#define IO_TYPE1 2
2N/A#define IO_TYPE2 3
2N/A#define IO_TYPE3 4
2N/A#define IO_TYPE4 5 /* same as IO TYPE 1 but no HM or PHY chip */
2N/A#define CLOCK_TYPE 7
2N/A
2N/A/* for CPU type UPA ports */
2N/Atypedef struct {
2N/A u_longlong_t afsr; /* Fault status register for CPU */
2N/A u_longlong_t afar; /* Fault address register for CPU */
2N/A} cpu_reset_state;
2N/A
2N/A/* For the clock board */
2N/Atypedef struct {
2N/A unsigned long clk_ssr_1; /* reset status for the clock board */
2N/A} clock_reset_state;
2N/A
2N/Astruct board_info {
2N/A u_longlong_t board_desc;
2N/A cpu_reset_state cpu[2]; /* could be a CPU */
2N/A u_longlong_t ac_error_status;
2N/A u_longlong_t dc_shadow_chain;
2N/A uint_t fhc_csr;
2N/A uint_t fhc_rcsr;
2N/A};
2N/A
2N/Astruct reset_info {
2N/A int length; /* size of the structure */
2N/A int version; /* Version of the structure */
2N/A struct board_info bd_reset_info[MAX_BOARDS];
2N/A clock_reset_state clk; /* one clock board */
2N/A unsigned char tod_timestamp[7];
2N/A};
2N/A
2N/A#ifdef __cplusplus
2N/A}
2N/A#endif
2N/A
2N/A#endif /* _RESET_INFO_H */