2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License (the "License"). 2N/A * You may not use this file except in compliance with the License. 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved. 2N/A * Copyright 2007 Jason King. All rights reserved. 2N/A * Use is subject to license terms. 2N/A/* which set of registers are used with an instruction */ 2N/A#
define REG_INT 0x00 /* regular integer registers */ 2N/A#
define REG_FP 0x01 /* single-precision fp registers */ 2N/A#
define REG_FPD 0x02 /* double-precision fp registers */ 2N/A#
define REG_FPQ 0x03 /* quad-precision fp registers */ 2N/A#
define REG_CP 0x04 /* coprocessor registers (v8) */ 2N/A/* the size fo the displacement for branches */ 2N/A/* get/set the register set name for the rd field of an instruction */ 2N/A#
define FLG_STORE (
0x1L <<
24)
/* the instruction is not a load */ 2N/A/* flags for ALU instructions */ 2N/A/* set/get register set name for 1st argument position */ 2N/A/* get/set reg set for 2nd argument position */ 2N/A/* set if the arguments do not contain immediate values */ 2N/A/* flags for branch instructions */ 2N/A/* has branch prediction */ 2N/A/* get/set condition code register set -- usually REG_NONE */ 2N/A#
endif /* _DIS_SPARC_FMT_H */