2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License, Version 1.0 only 2N/A * (the "License"). You may not use this file except in compliance 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 2N/A * Use is subject to license terms. 2N/A#
pragma ident "%Z%%M% %I% %E% SMI" 2N/A * Configuration data for Pentium Pro performance counters. 2N/A * Definitions taken from [3]. See the reference to 2N/A * understand what any of these settings actually means. 2N/A * [3] "Pentium Pro Family Developer's Manual, Volume 3: 2N/A * Operating Systems Writer's Manual," January 1996 2N/A#
define V_P5 (
1u << 0)
/* specific to Pentium cpus */ 2N/A#
define V_P6 (
1u <<
2)
/* specific to Pentium II cpus */ 2N/A * map from "cpu version" to flag bits 2N/A * Basic Pentium events 2N/A {v,
0x0,
"data_read"}, \
2N/A {v,
0x1,
"data_write"}, \
2N/A {v,
0x2,
"data_tlb_miss"}, \
2N/A {v,
0x3,
"data_read_miss"}, \
2N/A {v,
0x4,
"data_write_miss"}, \
2N/A {v,
0x5,
"write_hit_to_M_or_E"}, \
2N/A {v,
0x6,
"dcache_lines_wrback"}, \
2N/A {v,
0x7,
"external_snoops"}, \
2N/A {v,
0x8,
"external_dcache_snoop_hits"}, \
2N/A {v,
0x9,
"memory_access_in_both_pipes"}, \
2N/A {v,
0xa,
"bank_conflicts"}, \
2N/A {v,
0xb,
"misaligned_ref"}, \
2N/A {v,
0xc,
"code_read"}, \
2N/A {v,
0xd,
"code_tlb_miss"}, \
2N/A {v,
0xe,
"code_cache_miss"}, \
2N/A {v,
0xf,
"any_segreg_loaded"}, \
2N/A {v,
0x12,
"branches"}, \
2N/A {v,
0x13,
"btb_hits"}, \
2N/A {v,
0x14,
"taken_or_btb_hit"}, \
2N/A {v,
0x15,
"pipeline_flushes"}, \
2N/A {v,
0x16,
"instr_exec"}, \
2N/A {v,
0x17,
"instr_exec_V_pipe"}, \
2N/A {v,
0x18,
"clks_bus_cycle"}, \
2N/A {v,
0x19,
"clks_full_wbufs"}, \
2N/A {v,
0x1a,
"pipe_stall_read"}, \
2N/A {v,
0x1b,
"stall_on_write_ME"}, \
2N/A {v,
0x1c,
"locked_bus_cycle"}, \
2N/A {v,
0x1d,
"io_rw_cycles"}, \
2N/A {v,
0x1e,
"reads_noncache_mem"}, \
2N/A {v,
0x1f,
"pipeline_agi_stalls"}, \
2N/A {v,
0x22,
"flops"}, \
2N/A {v,
0x23,
"bp_match_dr0"}, \
2N/A {v,
0x24,
"bp_match_dr1"}, \
2N/A {v,
0x25,
"bp_match_dr2"}, \
2N/A {v,
0x26,
"bp_match_dr3"}, \
2N/A {v,
0x27,
"hw_intrs"}, \
2N/A {v,
0x28,
"data_rw"}, \
2N/A {v,
0x29,
"data_rw_miss"}
2N/A * Pentium Pro and Pentium II events 2N/A {
V_P6,
0x48,
"dcu_miss_outstanding"},
2N/A * Instruction fetch unit 2N/A * External bus logic 2N/A {
V_P6,
0x60,
"bus_req_outstanding"},
2N/A * Floating point unit 2N/A {
V_P6,
0xc1,
"flops"},
/* 0 only */ 2N/A {
V_P6,
0x10,
"fp_comp_ops_exe"},
/* 0 only */ 2N/A {
V_P6,
0x11,
"fp_assist"},
/* 1 only */ 2N/A {
V_P6,
0x14,
"cycles_div_busy"},
/* 0 only */ 2N/A * Instruction decoding and retirement 2N/A {
V_P6,
0xc7,
"cycles_int_pending_and_masked"},
2N/A {
V_P6,
0xc5,
"br_miss_pred_retired"},
2N/A {
V_P6,
0xca,
"br_miss_pred_taken_ret"},
2N/A {
V_P6,
0xd2,
"partial_rat_stalls"},
2N/A * Segment register loads 2N/A case 0xc1:
/* flops */ 2N/A case 0x10:
/* fp_comp_ops_exe */ 2N/A case 0x14:
/* cycles_div_busy */ 2N/A /* only reg0 counts these */ 2N/A case 0x11:
/* fp_assist */ 2N/A case 0x12:
/* mul */ 2N/A case 0x13:
/* div */ 2N/A /* only 1 can count these */ 2N/A * Register names can be specified as strings or even as numbers 2N/A return (
"Pentium with MMX");
2N/A return (
"Pentium Pro, Pentium II");
2N/A return (
"Pentium Pro with MMX, Pentium II");
2N/A "See Appendix A.2 of the \"Intel Architecture " 2N/A "Software Developer's Manual,\" 243192, 1997"));
2N/A "See Appendix A.1 of the \"Intel Architecture " 2N/A "Software Developer's Manual,\" 243192, 1997"));
2N/A * This is a functional interface to allow CPUs with fewer %pic registers 2N/A * to share the same data structure as those with more %pic registers 2N/A * within the same instruction set family. 2N/A (((v) >> (l)) & ((
1 << (
1 + (u) - (l))) -
1))
2N/A * Return the version of the current processor. 2N/A * Version -1 is defined as 'not performance counter capable' 2N/A * map family and model into the performance 2N/A * counter architectures we currently understand. 2N/A * for further explanation. 2N/A case 5:
/* Pentium and Pentium with MMX */ 2N/A case 6:
/* Pentium Pro and Pentium II and III */ 2N/A case 0xf:
/* Pentium IV */