2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License (the "License").
2N/A * You may not use this file except in compliance with the License.
2N/A *
2N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2N/A * or http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When distributing Covered Code, include this CDDL HEADER in each
2N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A
2N/A/*
2N/A * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
2N/A */
2N/A
2N/A .file "memcmp.s"
2N/A
2N/A/*
2N/A * memcmp(s1, s2, len)
2N/A *
2N/A * Compare n bytes: s1>s2: >0 s1==s2: 0 s1<s2: <0
2N/A *
2N/A * Fast assembler language version of the following C-program for memcmp
2N/A * which represents the `standard' for the C-library.
2N/A *
2N/A * int
2N/A * memcmp(const void *s1, const void *s2, size_t n)
2N/A * {
2N/A * if (s1 != s2 && n != 0) {
2N/A * const char *ps1 = s1;
2N/A * const char *ps2 = s2;
2N/A * do {
2N/A * if (*ps1++ != *ps2++)
2N/A * return(ps1[-1] - ps2[-1]);
2N/A * } while (--n != 0);
2N/A * }
2N/A * return (0);
2N/A * }
2N/A */
2N/A
2N/A#include <sys/asm_linkage.h>
2N/A#include <sys/sun4asi.h>
2N/A
2N/A ANSI_PRAGMA_WEAK(memcmp,function)
2N/A
2N/A ENTRY(memcmp)
2N/A cmp %o0, %o1 ! s1 == s2?
2N/A be %ncc, .cmpeq
2N/A
2N/A ! for small counts byte compare immediately
2N/A cmp %o2, 48
2N/A bleu,a %ncc, .bytcmp
2N/A mov %o2, %o3 ! o3 <= 48
2N/A
2N/A ! Count > 48. We will byte compare (8 + num of bytes to dbl align)
2N/A ! bytes. We assume that most miscompares will occur in the 1st 8 bytes
2N/A
2N/A.chkdbl:
2N/A and %o0, 7, %o4 ! is s1 aligned on a 8 byte bound
2N/A mov 8, %o3 ! o2 > 48; o3 = 8
2N/A sub %o4, 8, %o4 ! o4 = -(num of bytes to dbl align)
2N/A ba %ncc, .bytcmp
2N/A sub %o3, %o4, %o3 ! o3 = 8 + (num of bytes to dbl align)
2N/A
2N/A
2N/A1: ldub [%o1], %o5 ! byte compare loop
2N/A inc %o1
2N/A inc %o0
2N/A dec %o2
2N/A cmp %o4, %o5
2N/A bne %ncc, .noteq
2N/A.bytcmp:
2N/A deccc %o3
2N/A bgeu,a %ncc, 1b
2N/A ldub [%o0], %o4
2N/A
2N/A ! Check to see if there are more bytes to compare
2N/A cmp %o2, 0 ! is o2 > 0
2N/A bgu,a %ncc, .blkchk ! we should already be dbl aligned
2N/A cmp %o2, 320 ! if cnt < 256 + 64 - no Block ld/st
2N/A.cmpeq:
2N/A retl ! strings compare equal
2N/A sub %g0, %g0, %o0
2N/A
2N/A.noteq:
2N/A retl ! strings aren't equal
2N/A sub %o4, %o5, %o0 ! return(*s1 - *s2)
2N/A
2N/A
2N/A ! Now src1 is Double word aligned
2N/A.blkchk:
2N/A bgeu,a %ncc, blkcmp ! do block cmp
2N/A andcc %o0, 63, %o3 ! is src1 block aligned
2N/A
2N/A ! double word compare - using ldd and faligndata. Compares upto
2N/A ! 8 byte multiple count and does byte compare for the residual.
2N/A
2N/A.dwcmp:
2N/A
2N/A rd %fprs, %o3 ! o3 = fprs
2N/A
2N/A ! if fprs.fef == 0, set it. Checking it, reqires 2 instructions.
2N/A ! So set it anyway, without checking.
2N/A wr %g0, 0x4, %fprs ! fprs.fef = 1
2N/A
2N/A andn %o2, 7, %o4 ! o4 has 8 byte aligned cnt
2N/A sub %o4, 8, %o4
2N/A alignaddr %o1, %g0, %g1
2N/A ldd [%g1], %d0
2N/A4:
2N/A add %g1, 8, %g1
2N/A ldd [%g1], %d2
2N/A ldd [%o0], %d6
2N/A faligndata %d0, %d2, %d8
2N/A fcmpne32 %d6, %d8, %o5
2N/A fsrc1 %d6, %d6 ! 2 fsrc1's added since o5 cannot
2N/A fsrc1 %d8, %d8 ! be used for 3 cycles else we
2N/A fmovd %d2, %d0 ! create 9 bubbles in the pipeline
2N/A brnz,a,pn %o5, 6f
2N/A sub %o1, %o0, %o1 ! o1 gets the difference
2N/A subcc %o4, 8, %o4
2N/A add %o0, 8, %o0
2N/A add %o1, 8, %o1
2N/A bgu,pt %ncc, 4b
2N/A sub %o2, 8, %o2
2N/A
2N/A.residcmp:
2N/A ba 6f
2N/A sub %o1, %o0, %o1 ! o1 gets the difference
2N/A
2N/A5: ldub [%o0 + %o1], %o5 ! byte compare loop
2N/A inc %o0
2N/A cmp %o4, %o5
2N/A bne %ncc, .dnoteq
2N/A6:
2N/A deccc %o2
2N/A bgeu,a %ncc, 5b
2N/A ldub [%o0], %o4
2N/A
2N/A and %o3, 0x4, %o3 ! fprs.du = fprs.dl = 0
2N/A wr %o3, %g0, %fprs ! fprs = o3 - restore fprs
2N/A retl
2N/A sub %g0, %g0, %o0 ! strings compare equal
2N/A
2N/A.dnoteq:
2N/A and %o3, 0x4, %o3 ! fprs.du = fprs.dl = 0
2N/A wr %o3, %g0, %fprs ! fprs = o3 - restore fprs
2N/A retl
2N/A sub %o4, %o5, %o0 ! return(*s1 - *s2)
2N/A
2N/A
2N/Ablkcmp:
2N/A save %sp, -SA(MINFRAME), %sp
2N/A rd %fprs, %l5 ! l5 = fprs
2N/A
2N/A ! if fprs.fef == 0, set it. Checking it, reqires 2 instructions.
2N/A ! So set it anyway, without checking.
2N/A wr %g0, 0x4, %fprs ! fprs.fef = 1
2N/A
2N/A bz,pn %ncc, .blalign ! now block aligned
2N/A sub %i3, 64, %i3
2N/A neg %i3 ! bytes till block aligned
2N/A
2N/A ! Compare %i3 bytes till dst is block (64 byte) aligned. use
2N/A ! double word compares.
2N/A
2N/A alignaddr %i1, %g0, %g1
2N/A ldd [%g1], %d0
2N/A7:
2N/A add %g1, 8, %g1
2N/A ldd [%g1], %d2
2N/A ldd [%i0], %d6
2N/A faligndata %d0, %d2, %d8
2N/A fcmpne32 %d6, %d8, %i5
2N/A fsrc1 %d6, %d6 ! 2 fsrc1's added since i5 cannot
2N/A fsrc1 %d8, %d8 ! be used for 3 cycles else we
2N/A fmovd %d2, %d0 ! create 9 bubbles in the pipeline
2N/A brnz,a,pn %i5, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A subcc %i3, 8, %i3
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A bgu,pt %ncc, 7b
2N/A sub %i2, 8, %i2
2N/A
2N/A.blalign:
2N/A
2N/A ! src1 is block aligned
2N/A membar #StoreLoad
2N/A srl %i1, 3, %l6 ! bits 3,4,5 are now least sig in %l6
2N/A andcc %l6, 7, %l6 ! mask everything except bits 1,2 3
2N/A andn %i2, 63, %i3 ! calc number of blocks
2N/A alignaddr %i1, %g0, %g0 ! gen %gsr
2N/A andn %i1, 0x3F, %l7 ! blk aligned address
2N/A sub %i2, %i3, %l2
2N/A andn %l2, 7, %i4 ! calc doubles left after blkcpy
2N/A
2N/A be,a %ncc, 1f ! branch taken if src2 is 64-byte aligned
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A
2N/A call .+8 ! get the address of this instruction in %o7
2N/A sll %l6, 2, %l4
2N/A add %o7, %l4, %o7
2N/A jmp %o7 + 16 ! jump to the starting ldd instruction
2N/A nop
2N/A ldd [%l7+8], %d2
2N/A ldd [%l7+16], %d4
2N/A ldd [%l7+24], %d6
2N/A ldd [%l7+32], %d8
2N/A ldd [%l7+40], %d10
2N/A ldd [%l7+48], %d12
2N/A ldd [%l7+56], %d14
2N/A1:
2N/A add %l7, 64, %l7
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A sub %i3, 128, %i3
2N/A
2N/A ! switch statement to get us to the right 8 byte blk within a
2N/A ! 64 byte block
2N/A
2N/A cmp %l6, 4
2N/A bgeu,a hlf
2N/A cmp %l6, 6
2N/A cmp %l6, 2
2N/A bgeu,a sqtr
2N/A nop
2N/A cmp %l6, 1
2N/A be,a seg1
2N/A nop
2N/A ba seg0
2N/A nop
2N/Asqtr:
2N/A be,a seg2
2N/A nop
2N/A
2N/A ba,a seg3
2N/A nop
2N/A
2N/Ahlf:
2N/A bgeu,a fqtr
2N/A nop
2N/A cmp %l6, 5
2N/A be,a seg5
2N/A nop
2N/A ba seg4
2N/A nop
2N/Afqtr:
2N/A be,a seg6
2N/A nop
2N/A ba seg7
2N/A nop
2N/A
2N/A! The fsrc1 instructions are to make sure that the results of the fcmpne32
2N/A! are used 3 cycles later - else spitfire adds 9 bubbles.
2N/A
2N/A#define FCMPNE32_D32_D48 \
2N/A fcmpne32 %d48, %d32, %l0 ;\
2N/A fcmpne32 %d50, %d34, %l1 ;\
2N/A fcmpne32 %d52, %d36, %l2 ;\
2N/A fcmpne32 %d54, %d38, %l3 ;\
2N/A brnz,a %l0, add ;\
2N/A mov 0, %l4 ;\
2N/A fcmpne32 %d56, %d40, %l0 ;\
2N/A brnz,a %l1, add ;\
2N/A mov 8, %l4 ;\
2N/A fcmpne32 %d58, %d42, %l1 ;\
2N/A brnz,a %l2, add ;\
2N/A mov 16, %l4 ;\
2N/A fcmpne32 %d60, %d44, %l2 ;\
2N/A brnz,a %l3, add ;\
2N/A mov 24, %l4 ;\
2N/A fcmpne32 %d62, %d46, %l3 ;\
2N/A brnz,a %l0, add ;\
2N/A mov 32, %l4 ;\
2N/A fsrc1 %d48, %d48 ;\
2N/A brnz,a %l1, add ;\
2N/A mov 40, %l4 ;\
2N/A fsrc1 %d48, %d48 ;\
2N/A brnz,a %l2, add ;\
2N/A mov 48, %l4 ;\
2N/A fsrc1 %d48, %d48 ;\
2N/A brnz,a %l3, add ;\
2N/A mov 56, %l4
2N/A
2N/Aadd:
2N/A add %l4, %i0, %i0
2N/A add %l4, %i1, %i1
2N/A ba .remcmp
2N/A sub %i1, %i0, %i1
2N/A
2N/A#define FALIGN_D0 \
2N/A faligndata %d0, %d2, %d48 ;\
2N/A faligndata %d2, %d4, %d50 ;\
2N/A faligndata %d4, %d6, %d52 ;\
2N/A faligndata %d6, %d8, %d54 ;\
2N/A faligndata %d8, %d10, %d56 ;\
2N/A faligndata %d10, %d12, %d58 ;\
2N/A faligndata %d12, %d14, %d60 ;\
2N/A faligndata %d14, %d16, %d62
2N/A
2N/A#define FALIGN_D16 \
2N/A faligndata %d16, %d18, %d48 ;\
2N/A faligndata %d18, %d20, %d50 ;\
2N/A faligndata %d20, %d22, %d52 ;\
2N/A faligndata %d22, %d24, %d54 ;\
2N/A faligndata %d24, %d26, %d56 ;\
2N/A faligndata %d26, %d28, %d58 ;\
2N/A faligndata %d28, %d30, %d60 ;\
2N/A faligndata %d30, %d0, %d62
2N/A
2N/Aseg0:
2N/A FALIGN_D0
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D16
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg0
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D0
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd16
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D16
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd0
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D2 \
2N/A faligndata %d2, %d4, %d48 ;\
2N/A faligndata %d4, %d6, %d50 ;\
2N/A faligndata %d6, %d8, %d52 ;\
2N/A faligndata %d8, %d10, %d54 ;\
2N/A faligndata %d10, %d12, %d56 ;\
2N/A faligndata %d12, %d14, %d58 ;\
2N/A faligndata %d14, %d16, %d60 ;\
2N/A faligndata %d16, %d18, %d62
2N/A
2N/A#define FALIGN_D18 \
2N/A faligndata %d18, %d20, %d48 ;\
2N/A faligndata %d20, %d22, %d50 ;\
2N/A faligndata %d22, %d24, %d52 ;\
2N/A faligndata %d24, %d26, %d54 ;\
2N/A faligndata %d26, %d28, %d56 ;\
2N/A faligndata %d28, %d30, %d58 ;\
2N/A faligndata %d30, %d0, %d60 ;\
2N/A faligndata %d0, %d2, %d62
2N/A
2N/A
2N/Aseg1:
2N/A FALIGN_D2
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D18
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg1
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D2
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd18
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D18
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd2
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D4 \
2N/A faligndata %d4, %d6, %d48 ;\
2N/A faligndata %d6, %d8, %d50 ;\
2N/A faligndata %d8, %d10, %d52 ;\
2N/A faligndata %d10, %d12, %d54 ;\
2N/A faligndata %d12, %d14, %d56 ;\
2N/A faligndata %d14, %d16, %d58 ;\
2N/A faligndata %d16, %d18, %d60 ;\
2N/A faligndata %d18, %d20, %d62
2N/A
2N/A#define FALIGN_D20 \
2N/A faligndata %d20, %d22, %d48 ;\
2N/A faligndata %d22, %d24, %d50 ;\
2N/A faligndata %d24, %d26, %d52 ;\
2N/A faligndata %d26, %d28, %d54 ;\
2N/A faligndata %d28, %d30, %d56 ;\
2N/A faligndata %d30, %d0, %d58 ;\
2N/A faligndata %d0, %d2, %d60 ;\
2N/A faligndata %d2, %d4, %d62
2N/A
2N/Aseg2:
2N/A FALIGN_D4
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D20
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D4
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd20
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D20
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd4
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D6 \
2N/A faligndata %d6, %d8, %d48 ;\
2N/A faligndata %d8, %d10, %d50 ;\
2N/A faligndata %d10, %d12, %d52 ;\
2N/A faligndata %d12, %d14, %d54 ;\
2N/A faligndata %d14, %d16, %d56 ;\
2N/A faligndata %d16, %d18, %d58 ;\
2N/A faligndata %d18, %d20, %d60 ;\
2N/A faligndata %d20, %d22, %d62
2N/A
2N/A#define FALIGN_D22 \
2N/A faligndata %d22, %d24, %d48 ;\
2N/A faligndata %d24, %d26, %d50 ;\
2N/A faligndata %d26, %d28, %d52 ;\
2N/A faligndata %d28, %d30, %d54 ;\
2N/A faligndata %d30, %d0, %d56 ;\
2N/A faligndata %d0, %d2, %d58 ;\
2N/A faligndata %d2, %d4, %d60 ;\
2N/A faligndata %d4, %d6, %d62
2N/A
2N/A
2N/Aseg3:
2N/A FALIGN_D6
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D22
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg3
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D6
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd22
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D22
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd6
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D8 \
2N/A faligndata %d8, %d10, %d48 ;\
2N/A faligndata %d10, %d12, %d50 ;\
2N/A faligndata %d12, %d14, %d52 ;\
2N/A faligndata %d14, %d16, %d54 ;\
2N/A faligndata %d16, %d18, %d56 ;\
2N/A faligndata %d18, %d20, %d58 ;\
2N/A faligndata %d20, %d22, %d60 ;\
2N/A faligndata %d22, %d24, %d62
2N/A
2N/A#define FALIGN_D24 \
2N/A faligndata %d24, %d26, %d48 ;\
2N/A faligndata %d26, %d28, %d50 ;\
2N/A faligndata %d28, %d30, %d52 ;\
2N/A faligndata %d30, %d0, %d54 ;\
2N/A faligndata %d0, %d2, %d56 ;\
2N/A faligndata %d2, %d4, %d58 ;\
2N/A faligndata %d4, %d6, %d60 ;\
2N/A faligndata %d6, %d8, %d62
2N/A
2N/A
2N/Aseg4:
2N/A FALIGN_D8
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D24
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg4
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D8
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd24
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D24
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd8
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D10 \
2N/A faligndata %d10, %d12, %d48 ;\
2N/A faligndata %d12, %d14, %d50 ;\
2N/A faligndata %d14, %d16, %d52 ;\
2N/A faligndata %d16, %d18, %d54 ;\
2N/A faligndata %d18, %d20, %d56 ;\
2N/A faligndata %d20, %d22, %d58 ;\
2N/A faligndata %d22, %d24, %d60 ;\
2N/A faligndata %d24, %d26, %d62
2N/A
2N/A#define FALIGN_D26 \
2N/A faligndata %d26, %d28, %d48 ;\
2N/A faligndata %d28, %d30, %d50 ;\
2N/A faligndata %d30, %d0, %d52 ;\
2N/A faligndata %d0, %d2, %d54 ;\
2N/A faligndata %d2, %d4, %d56 ;\
2N/A faligndata %d4, %d6, %d58 ;\
2N/A faligndata %d6, %d8, %d60 ;\
2N/A faligndata %d8, %d10, %d62
2N/A
2N/A
2N/Aseg5:
2N/A FALIGN_D10
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D26
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg5
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D10
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd26
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D26
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd10
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D12 \
2N/A faligndata %d12, %d14, %d48 ;\
2N/A faligndata %d14, %d16, %d50 ;\
2N/A faligndata %d16, %d18, %d52 ;\
2N/A faligndata %d18, %d20, %d54 ;\
2N/A faligndata %d20, %d22, %d56 ;\
2N/A faligndata %d22, %d24, %d58 ;\
2N/A faligndata %d24, %d26, %d60 ;\
2N/A faligndata %d26, %d28, %d62
2N/A
2N/A#define FALIGN_D28 \
2N/A faligndata %d28, %d30, %d48 ;\
2N/A faligndata %d30, %d0, %d50 ;\
2N/A faligndata %d0, %d2, %d52 ;\
2N/A faligndata %d2, %d4, %d54 ;\
2N/A faligndata %d4, %d6, %d56 ;\
2N/A faligndata %d6, %d8, %d58 ;\
2N/A faligndata %d8, %d10, %d60 ;\
2N/A faligndata %d10, %d12, %d62
2N/A
2N/A
2N/Aseg6:
2N/A FALIGN_D12
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D28
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg6
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D12
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd28
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D28
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd12
2N/A sub %i2, 64, %i2
2N/A
2N/A#define FALIGN_D14 \
2N/A faligndata %d14, %d16, %d48 ;\
2N/A faligndata %d16, %d18, %d50 ;\
2N/A faligndata %d18, %d20, %d52 ;\
2N/A faligndata %d20, %d22, %d54 ;\
2N/A faligndata %d22, %d24, %d56 ;\
2N/A faligndata %d24, %d26, %d58 ;\
2N/A faligndata %d26, %d28, %d60 ;\
2N/A faligndata %d28, %d30, %d62
2N/A
2N/A#define FALIGN_D30 \
2N/A faligndata %d30, %d0, %d48 ;\
2N/A faligndata %d0, %d2, %d50 ;\
2N/A faligndata %d2, %d4, %d52 ;\
2N/A faligndata %d4, %d6, %d54 ;\
2N/A faligndata %d6, %d8, %d56 ;\
2N/A faligndata %d8, %d10, %d58 ;\
2N/A faligndata %d10, %d12, %d60 ;\
2N/A faligndata %d12, %d14, %d62
2N/A
2N/Aseg7:
2N/A FALIGN_D14
2N/A ldda [%l7]ASI_BLK_P, %d0
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 1f
2N/A sub %i2, 64, %i2
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A FALIGN_D30
2N/A ldda [%l7]ASI_BLK_P, %d16
2N/A add %l7, 64, %l7
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A subcc %i3, 64, %i3
2N/A bz,pn %ncc, 0f
2N/A sub %i2, 64, %i2
2N/A
2N/A ba %ncc, seg7
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A
2N/A0:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D14
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd30
2N/A sub %i2, 64, %i2
2N/A
2N/A1:
2N/A ldda [%i0]ASI_BLK_P, %d32
2N/A membar #Sync
2N/A FALIGN_D30
2N/A FCMPNE32_D32_D48
2N/A add %i0, 64, %i0
2N/A add %i1, 64, %i1
2N/A ba %ncc, blkd14
2N/A sub %i2, 64, %i2
2N/A
2N/A
2N/Ablkd0:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d0, %d2, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd2:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d2, %d4, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd4:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d4, %d6, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd6:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d6, %d8, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd8:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d8, %d10, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd10:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d10, %d12, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd12:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d12, %d14, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd14:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A ba,pt %ncc, blkleft
2N/A fmovd %d14, %d0
2N/A
2N/Ablkd16:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d16, %d18, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd18:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d18, %d20, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd20:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d20, %d22, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd22:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d22, %d24, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd24:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d24, %d26, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd26:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d26, %d28, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd28:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A faligndata %d28, %d30, %d48
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d48, %l1
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A fsrc1 %d32, %d32
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A sub %i2, 8, %i2
2N/A
2N/Ablkd30:
2N/A subcc %i4, 8, %i4
2N/A blu,a,pn %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A fmovd %d30, %d0
2N/A
2N/A ! This loop handles doubles remaining that were not loaded(ldda`ed)
2N/A ! in the Block Compare loop
2N/Ablkleft:
2N/A ldd [%l7], %d2
2N/A add %l7, 8, %l7
2N/A faligndata %d0, %d2, %d8
2N/A ldd [%i0], %d32
2N/A fcmpne32 %d32, %d8, %l1
2N/A fsrc1 %d2, %d0
2N/A fsrc1 %d2, %d0
2N/A fsrc1 %d2, %d0
2N/A brnz,a %l1, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A add %i0, 8, %i0
2N/A add %i1, 8, %i1
2N/A subcc %i4, 8, %i4
2N/A bgeu,pt %ncc, blkleft
2N/A sub %i2, 8, %i2
2N/A
2N/A ba %ncc, .remcmp
2N/A sub %i1, %i0, %i1 ! i1 gets the difference
2N/A
2N/A6: ldub [%i0 + %i1], %i5 ! byte compare loop
2N/A inc %i0
2N/A cmp %i4, %i5
2N/A bne %ncc, .bnoteq
2N/A.remcmp:
2N/A deccc %i2
2N/A bgeu,a %ncc, 6b
2N/A ldub [%i0], %i4
2N/A
2N/Aexit:
2N/A and %l5, 0x4, %l5 ! fprs.du = fprs.dl = 0
2N/A wr %l5, %g0, %fprs ! fprs = l5 - restore fprs
2N/A membar #StoreLoad|#StoreStore
2N/A ret
2N/A restore %g0, %g0, %o0
2N/A
2N/A
2N/A.bnoteq:
2N/A and %l5, 0x4, %l5 ! fprs.du = fprs.dl = 0
2N/A wr %l5, %g0, %fprs ! fprs = l5 - restore fprs
2N/A membar #StoreLoad|#StoreStore
2N/A sub %i4, %i5, %i0 ! return(*s1 - *s2)
2N/A ret ! strings aren't equal
2N/A restore %i0, %g0, %o0
2N/A
2N/A
2N/A
2N/A SET_SIZE(memcmp)