2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License (the "License").
2N/A * You may not use this file except in compliance with the License.
2N/A *
2N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2N/A * or http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When distributing Covered Code, include this CDDL HEADER in each
2N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A
2N/A/*
2N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2N/A * Use is subject to license terms.
2N/A */
2N/A
2N/A/*
2N/A * Copyright (c) 2009, Intel Corporation
2N/A * All rights reserved.
2N/A */
2N/A
2N/A/*
2N/A * Portions Copyright 2009 Advanced Micro Devices, Inc.
2N/A */
2N/A
2N/A/*
2N/A * Assembler support routines to getcpuid information used to set
2N/A * cache size information. Cache information used by memset, strcpy, etc..
2N/A */
2N/A
2N/A#include <sys/asm_linkage.h>
2N/A#include "proc64_id.h"
2N/A
2N/A .global .memops_method
2N/A .global .amd64cache1, .amd64cache1half, .amd64cache2, .amd64cache2half
2N/A .global .largest_level_cache_size
2N/A
2N/A
2N/A/*
2N/A * Defaults for Core 2 Duo and AMD's SledgeHammer
2N/A */
2N/A .data
2N/A .balign 8
2N/A.memops_method:
2N/A .int NO_SSE
2N/A
2N/A .balign 8
2N/A.amd64cache1: .quad AMD_DFLT_L1_CACHE_SIZE
2N/A.amd64cache1half: .quad AMD_DFLT_L1_CACHE_SIZE/2
2N/A.amd64cache2: .quad AMD_DFLT_L2_CACHE_SIZE
2N/A.amd64cache2half: .quad AMD_DFLT_L2_CACHE_SIZE/2
2N/A.largest_level_cache_size:
2N/A .int AMD_DFLT_L2_CACHE_SIZE
2N/A
2N/A/*
2N/A * Get cpuid data.
2N/A * (void)__libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index )
2N/A */
2N/A .text
2N/A
2N/A ENTRY(__libc_get_cpuid)
2N/A # rdi = cpuid function, rsi = out_reg addr, rdx = cache index(fn 4)
2N/A push %rbx
2N/A mov %edx,%ecx
2N/A mov %edi,%eax
2N/A cpuid
2N/A mov %eax,(%rsi)
2N/A mov %ebx,0x4(%rsi)
2N/A mov %ecx,0x8(%rsi)
2N/A mov %edx,0xc(%rsi)
2N/A pop %rbx
2N/A ret
2N/A SET_SIZE(__libc_get_cpuid)
2N/A
2N/A/*
2N/A * Set memops SSE level to use.
2N/A * void __intel_set_memops_method(long sse_level);
2N/A */
2N/A ENTRY(__intel_set_memops_method)
2N/A mov %edi,.memops_method(%rip)
2N/A ret
2N/A SET_SIZE(__intel_set_memops_method)
2N/A
2N/A/*
2N/A * Set cache info global variables used by various libc primitives.
2N/A * __set_cache_sizes(long l1_cache_size, long l2_cache_size,
2N/A * long largest_level_cache);
2N/A */
2N/A ENTRY(__set_cache_sizes)
2N/A # rdi = l1_cache_size, rsi = l2_cache_size, rdx = largest_level_cache
2N/A
2N/A mov %rdi,.amd64cache1(%rip)
2N/A shr $1, %rdi
2N/A mov %rdi,.amd64cache1half(%rip)
2N/A
2N/A mov %rsi,.amd64cache2(%rip)
2N/A shr $1, %rsi
2N/A mov %rsi,.amd64cache2half(%rip)
2N/A
2N/A mov %rdx,.largest_level_cache_size(%rip)
2N/A ret
2N/A SET_SIZE(__set_cache_sizes)