fwstart.S revision 2
2N/A * GRUB -- GRand Unified Bootloader 2N/A * Copyright (C) 2000,2001,2002,2003,2004,2005,2007,2008,2009,2010 Free Software Foundation, Inc. 2N/A * GRUB is free software: you can redistribute it and/or modify 2N/A * it under the terms of the GNU General Public License as published by 2N/A * the Free Software Foundation, either version 3 of the License, or 2N/A * (at your option) any later version. 2N/A * GRUB is distributed in the hope that it will be useful, 2N/A * but WITHOUT ANY WARRANTY; without even the implied warranty of 2N/A * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2N/A * GNU General Public License for more details. 2N/A * You should have received a copy of the GNU General Public License 2N/A /* Put serial init as soon as possible. But on Fuloong2f serial is past 2N/A Geode, so on Fuloong2f we need Geode first. 2N/A /* Find CS5536 controller. */ 2N/A /* $t4 chooses device in priority encoding. */ 2N/A /* Resulting value is kept in GRUB_MACHINE_PCI_CONF_CTRL_REG. 2N/A This way we don't need to sacrifice a register for it. */ 2N/A /* We have only one bus (0). Function is 0. */ 2N/A /* In case of failure try again. CS5536 may be slow to come up. */ 2N/A /* Set GPIO LBAR. */ 2N/A /* Set mask to 0xf and enabled bit to 1. */ 2N/A /* Initialise SMBus controller. */ 2N/A /* Set SMBUS LBAR. */ 2N/A /* Set mask to 0xf and enabled bit to 1. */ 2N/A /* Disable interrupts. */ 2N/A /* Set as master. */ 2N/A /* Launch SMBus controller at slowest speed possible. */ 2N/A /* Yeeloong and Fuloong2f have only one memory slot. */ 2N/A /* Output first byte on serial for debugging. */ 2N/A /* And here is our goal: DDR2 controller initialisation. */ 2N/A /* Use addiu for sign-extension. */ 2N/A /* Same as similarly named C function but in asm since 2N/A we need it early. */ 2N/A /* In: none. Out: none. Clobbered: $t0, $t1, $t2, $a0, $a1, $a2. */ 2N/A /* Turn off the interrupt. */ 2N/A /* Set the baud rate 115200. */ 2N/A /* Set the line status. */ 2N/A /* Enable the FIFO. */ 2N/A /* Turn on DTR and RTS. */ 2N/A /* Let message return to original caller. */ 2N/A /* Print message on serial console. */ 2N/A /* In: $a0 = asciiz message. Out: none. Clobbered: $t0, $t1, $a0. */ 2N/A /* Print 32-bit hexadecimal on serial. 2N/A In: $a0. Out: None. Clobbered: $a0, $t0, $t1, $t2 2N/A /* Write CS5536 MSR. 2N/A In: $a0 address, $a1 lower word, $a2 upper word. 2N/A /* Wait for SMBus data or empty transmitter. */ 2N/A /* In: $a0 = exception handler. Out: none. Clobbered: $t0, $t1 */ 2N/A /* Read SPD byte. In: $a0 byte, $a1 device. Out: $v0 read byte (0x100 on failure). 2N/A Clobbered: $t0, $t1, $t2, $t3, $a0. */ 2N/A /* Send device address. */ 2N/A /* Send byte address. */ 2N/A /* Send device address. */ 2N/A/* Dump of GPIO connections. FIXME: Remove useless and macroify. */ 2N/A .
long 0xffff0000,
0x2eefd110,
0xffff0000,
0xffff0000 2N/A .
long 0x2eefd110,
0xffff0000,
0x1000efff,
0xefff1000 2N/A .
long 0x3df3c20c,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0x7df3820c,
0x3df3c20c,
0xffff0000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0x3de3c21c,
0x3d83c27c 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0xffff0000,
0xffff0000,
0x0000ffff,
0xffff0000 2N/A .
long 0xefff1000,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0xefff1000,
0xefff1000,
0xffff0000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0xefff1000,
0xefff1000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0xffff0000,
0x2ffdd002,
0xffff0000,
0xffff0000 2N/A .
long 0x2fffd000,
0xffff0000,
0x1000efff,
0xefff1000 2N/A .
long 0x3ffbc004,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0x3ffbc004,
0x3ffbc004,
0xffff0000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0x3ffbc004,
0x3f9bc064 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0xffff0000,
0xffff0000,
0x0000ffff,
0xffff0000 2N/A .
long 0xefff1000,
0xffff0000,
0xffff0000,
0xffff0000 2N/A .
long 0xefff1000,
0xefff1000,
0xffff0000,
0x00000000 2N/A .
long 0xffff0000,
0xffff0000,
0xefff1000,
0xffff0000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x00000000,
0x00000000,
0x00000000 2N/A .
long 0x00000000,
0x50000000,
0x00000000,
0x00000000 2N/A /* FIXME: figure termination resistance. */ 2N/A /* $v0 = 15 - $v0. */ 2N/A /* Find the fastest supported CAS latency. */ 2N/A /* $v0 = 15 - ($v0 + 1) = 14 - $v0. */ 2N/A /* Desactivate DDR2 registers. */ 2N/A /* Set line size to 32 bytes and disabled cache. */ 2N/A /* Invalidate all I-cache entries. */ 2N/A /* Invalidate all D-cache entries. */ 2N/A /* All four ways. */ 2N/A /* Invalidate all S-cache entries. */ 2N/A /* All four ways. */ 2N/A /* Finally enable cache. */ 2N/A /* Set ROM delay cycles to 1. */ 2N/A /* Take advantage of cache. */