1N/A/*
1N/A * GRUB -- GRand Unified Bootloader
1N/A * Copyright (C) 1999,2005,2005 Free Software Foundation, Inc.
1N/A *
1N/A * This program is free software; you can redistribute it and/or modify
1N/A * it under the terms of the GNU General Public License as published by
1N/A * the Free Software Foundation; either version 2 of the License, or
1N/A * (at your option) any later version.
1N/A *
1N/A * This program is distributed in the hope that it will be useful,
1N/A * but WITHOUT ANY WARRANTY; without even the implied warranty of
1N/A * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1N/A * GNU General Public License for more details.
1N/A *
1N/A * You should have received a copy of the GNU General Public License
1N/A * along with this program; if not, write to the Free Software
1N/A * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1N/A */
1N/A
1N/A/*
1N/A * <Insert copyright here : it must be BSD-like so anyone can use it>
1N/A *
1N/A * Author: Erich Boleyn <erich@uruk.org> http://www.uruk.org/~erich/
1N/A *
1N/A * Source file implementing Intel MultiProcessor Specification (MPS)
1N/A * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
1N/A * with hooks for running correctly on a standard PC without the hardware.
1N/A *
1N/A * This file was created from information in the Intel MPS version 1.4
1N/A * document, order number 242016-004, which can be ordered from the
1N/A * Intel literature center.
1N/A *
1N/A * General limitations of this code:
1N/A *
1N/A * (1) : This code has never been tested on an MPS-compatible system with
1N/A * 486 CPUs, but is expected to work.
1N/A * (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and
1N/A * that 32-bit pointers and memory addressing is used uniformly.
1N/A */
1N/A
1N/A#define _SMP_IMPS_C
1N/A
1N/A
1N/A/*
1N/A * XXXXX The following absolutely must be defined!!!
1N/A *
1N/A * The "KERNEL_PRINT" could be made a null macro with no danger, of
1N/A * course, but pretty much nothing would work without the other
1N/A * ones defined.
1N/A */
1N/A
1N/A#if 0
1N/A#define KERNEL_PRINT(x) /* some kind of print function */
1N/A#define CMOS_WRITE_BYTE(x,y) /* write unsigned char "y" at CMOS loc "x" */
1N/A#define CMOS_READ_BYTE(x) /* read unsigned char at CMOS loc "x" */
1N/A#define PHYS_TO_VIRTUAL(x) /* convert physical address "x" to virtual */
1N/A#define VIRTUAL_TO_PHYS(x) /* convert virtual address "x" to physical */
1N/A#endif
1N/A
1N/A
1N/A/*
1N/A * This is the Intel MultiProcessor Spec debugging/display code.
1N/A */
1N/A
1N/A#define IMPS_DEBUG
1N/A#define KERNEL_PRINT(x) printf x
1N/A#define CMOS_WRITE_BYTE(x, y) cmos_write_byte(x, y)
1N/A#define CMOS_READ_BYTE(x) cmos_read_byte(x)
1N/A#define PHYS_TO_VIRTUAL(x) (x)
1N/A#define VIRTUAL_TO_PHYS(x) (x)
1N/A
1N/Astatic inline unsigned char
1N/Ainb (unsigned short port)
1N/A{
1N/A unsigned char data;
1N/A
1N/A __asm __volatile ("inb %1,%0" :"=a" (data):"d" (port));
1N/A return data;
1N/A}
1N/A
1N/Astatic inline void
1N/Aoutb (unsigned short port, unsigned char val)
1N/A{
1N/A __asm __volatile ("outb %0,%1"::"a" (val), "d" (port));
1N/A}
1N/A
1N/A
1N/Astatic inline void
1N/Acmos_write_byte (int loc, int val)
1N/A{
1N/A outb (0x70, loc);
1N/A outb (0x71, val);
1N/A}
1N/A
1N/Astatic inline unsigned
1N/Acmos_read_byte (int loc)
1N/A{
1N/A outb (0x70, loc);
1N/A return inb (0x71);
1N/A}
1N/A
1N/A
1N/A/*
1N/A * Includes here
1N/A */
1N/A
1N/A#include "shared.h"
1N/A#include "apic.h"
1N/A#include "smp-imps.h"
1N/A
1N/A
1N/A/*
1N/A * Defines that are here so as not to be in the global header file.
1N/A */
1N/A#define EBDA_SEG_ADDR 0x40E
1N/A#define BIOS_RESET_VECTOR 0x467
1N/A#define LAPIC_ADDR_DEFAULT 0xFEE00000uL
1N/A#define IOAPIC_ADDR_DEFAULT 0xFEC00000uL
1N/A#define CMOS_RESET_CODE 0xF
1N/A#define CMOS_RESET_JUMP 0xa
1N/A#define CMOS_BASE_MEMORY 0x15
1N/A
1N/A
1N/A/*
1N/A * Static defines here for SMP use.
1N/A */
1N/A
1N/A#define DEF_ENTRIES 23
1N/A
1N/Astatic int lapic_dummy = 0;
1N/Astatic struct
1N/A {
1N/A imps_processor proc[2];
1N/A imps_bus bus[2];
1N/A imps_ioapic ioapic;
1N/A imps_interrupt intin[16];
1N/A imps_interrupt lintin[2];
1N/A }
1N/Adefconfig =
1N/A{
1N/A {
1N/A {
1N/A IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0
1N/A }
1N/A }
1N/A ,
1N/A {
1N/A {
1N/A IMPS_BCT_BUS, 0,
1N/A {
1N/A 'E', 'I', 'S', 'A', ' ', ' '
1N/A }
1N/A }
1N/A ,
1N/A {
1N/A 255, 1,
1N/A {
1N/A 'P', 'C', 'I', ' ', ' ', ' '
1N/A }
1N/A }
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT
1N/A }
1N/A ,
1N/A {
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15
1N/A }
1N/A }
1N/A ,
1N/A {
1N/A {
1N/A IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0
1N/A }
1N/A ,
1N/A {
1N/A IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1
1N/A }
1N/A }
1N/A};
1N/A
1N/A/*
1N/A * Exported globals here.
1N/A */
1N/A
1N/A/*
1N/A * "imps_any_new_apics" is non-zero if any of the APICS (local or I/O)
1N/A * are *not* an 82489DX. This is useful to determine if more than 15
1N/A * CPUs can be supported (true if zero).
1N/A */
1N/Astatic int imps_any_new_apics = 0;
1N/A#if 0
1N/Avolatile int imps_release_cpus = 0;
1N/A#endif
1N/A/*
1N/A * "imps_enabled" is non-zero if the probe sequence found IMPS
1N/A * information and was successful.
1N/A */
1N/Astatic int imps_enabled = 0;
1N/A/*
1N/A * This represents the number of CPUs found.
1N/A */
1N/Astatic int imps_num_cpus = 1;
1N/A/*
1N/A * This contains the local APIC hardware address.
1N/A */
1N/Astatic unsigned imps_lapic_addr = ((unsigned) (&lapic_dummy)) - LAPIC_ID;
1N/A/*
1N/A * These map from virtual cpu numbers to APIC id's and back.
1N/A */
1N/Astatic unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
1N/Astatic unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
1N/A
1N/A
1N/A/*
1N/A * MPS checksum function
1N/A *
1N/A * Function finished.
1N/A */
1N/A
1N/Astatic int
1N/Aget_checksum (unsigned start, int length)
1N/A{
1N/A unsigned sum = 0;
1N/A
1N/A while (length-- > 0)
1N/A {
1N/A sum += *((unsigned char *) (start++));
1N/A }
1N/A
1N/A return (sum & 0xFF);
1N/A}
1N/A
1N/A
1N/A/*
1N/A * Primary function for booting individual CPUs.
1N/A *
1N/A * This must be modified to perform whatever OS-specific initialization
1N/A * that is required.
1N/A */
1N/A
1N/Astatic int
1N/Aboot_cpu (imps_processor * proc)
1N/A{
1N/A unsigned bootaddr, accept_status;
1N/A unsigned bios_reset_vector = PHYS_TO_VIRTUAL (BIOS_RESET_VECTOR);
1N/A
1N/A /* %%%%% ESB */
1N/A extern char patch_code[];
1N/A bootaddr = 256 * 1024;
1N/A memmove ((char *) bootaddr, patch_code, 32);
1N/A
1N/A /*
1N/A * Generic CPU startup sequence starts here.
1N/A */
1N/A
1N/A /* set BIOS reset vector */
1N/A CMOS_WRITE_BYTE (CMOS_RESET_CODE, CMOS_RESET_JUMP);
1N/A *((volatile unsigned *) bios_reset_vector) = bootaddr << 12;
1N/A
1N/A /* clear the error register */
1N/A if (proc->apic_ver & 0x10)
1N/A {
1N/A IMPS_LAPIC_WRITE (LAPIC_ESR, 0);
1N/A accept_status = IMPS_LAPIC_READ (LAPIC_ESR);
1N/A }
1N/A
1N/A#if 0
1N/A /* assert INIT IPI */
1N/A cfg = IMPS_LAPIC_READ (LAPIC_ICR + 1);
1N/A cfg &= LAPIC_DEST_MASK;
1N/A IMPS_LAPIC_WRITE (LAPIC_ICR + 1, cfg);
1N/A cfg = IMPS_LAPIC_READ (LAPIC_ACR);
1N/A cfg &=;
1N/A
1N/A /* %%%%% ESB finish adding startup sequence */
1N/A#endif
1N/A
1N/A /* clean up BIOS reset vector */
1N/A CMOS_WRITE_BYTE (CMOS_RESET_CODE, 0);
1N/A *((volatile unsigned *) bios_reset_vector) = 0;
1N/A
1N/A /*
1N/A * Generic CPU startup sequence ends here.
1N/A */
1N/A
1N/A KERNEL_PRINT (("\n"));
1N/A
1N/A return 1;
1N/A
1N/A /* XXXXX add OS-specific initialization here! */
1N/A}
1N/A
1N/A
1N/A/*
1N/A * read bios stuff and fill tables
1N/A */
1N/A
1N/Astatic void
1N/Aadd_processor (imps_processor * proc)
1N/A{
1N/A int apicid = proc->apic_id;
1N/A
1N/A KERNEL_PRINT ((" Processor [APIC id %d ver %d]: ",
1N/A apicid, proc->apic_ver));
1N/A if (!(proc->flags & IMPS_FLAG_ENABLED))
1N/A {
1N/A KERNEL_PRINT (("DISABLED\n"));
1N/A return;
1N/A }
1N/A if (proc->apic_ver > 0xF)
1N/A {
1N/A imps_any_new_apics = 1;
1N/A }
1N/A if (proc->flags & (IMPS_CPUFLAG_BOOT))
1N/A {
1N/A KERNEL_PRINT (("#0 Bootstrap Processor (BSP)\n"));
1N/A return;
1N/A }
1N/A imps_cpu_apic_map[imps_num_cpus] = apicid;
1N/A imps_apic_cpu_map[apicid] = imps_num_cpus;
1N/A if (boot_cpu (proc))
1N/A {
1N/A
1N/A /* XXXXX add OS-specific setup for secondary CPUs here */
1N/A
1N/A imps_num_cpus++;
1N/A }
1N/A}
1N/A
1N/A
1N/Astatic void
1N/Aadd_bus (imps_bus * bus)
1N/A{
1N/A char str[8];
1N/A
1N/A memmove (str, bus->bus_type, 6);
1N/A str[6] = 0;
1N/A KERNEL_PRINT ((" Bus id %d is %s\n", bus->id, str));
1N/A
1N/A /* XXXXX add OS-specific code here */
1N/A}
1N/A
1N/A
1N/Astatic void
1N/Aadd_ioapic (imps_ioapic * ioapic)
1N/A{
1N/A KERNEL_PRINT ((" I/O APIC id %d ver %d, address: 0x%x ",
1N/A ioapic->id, ioapic->ver, ioapic->addr));
1N/A if (!(ioapic->flags & IMPS_FLAG_ENABLED))
1N/A {
1N/A KERNEL_PRINT (("DISABLED\n"));
1N/A return;
1N/A }
1N/A KERNEL_PRINT (("\n"));
1N/A
1N/A /* XXXXX add OS-specific code here */
1N/A}
1N/A
1N/A
1N/Astatic void
1N/Aimps_read_config_table (unsigned start, int count)
1N/A{
1N/A while (count-- > 0)
1N/A {
1N/A switch (*((unsigned char *) start))
1N/A {
1N/A case IMPS_BCT_PROCESSOR:
1N/A add_processor ((imps_processor *) start);
1N/A start += 12; /* 20 total */
1N/A break;
1N/A case IMPS_BCT_BUS:
1N/A add_bus ((imps_bus *) start);
1N/A break;
1N/A case IMPS_BCT_IOAPIC:
1N/A add_ioapic ((imps_ioapic *) start);
1N/A break;
1N/A#if 0 /* XXXXX uncomment this if "add_io_interrupt" is implemented */
1N/A case IMPS_BCT_IO_INTERRUPT:
1N/A add_io_interrupt ((imps_interrupt *) start);
1N/A break;
1N/A#endif
1N/A#if 0 /* XXXXX uncomment this if "add_local_interrupt" is implemented */
1N/A case IMPS_BCT_LOCAL_INTERRUPT:
1N/A add_local_interupt ((imps_interrupt *) start);
1N/A break;
1N/A#endif
1N/A default:
1N/A break;
1N/A }
1N/A start += 8;
1N/A }
1N/A}
1N/A
1N/A
1N/Astatic int
1N/Aimps_bad_bios (imps_fps * fps_ptr)
1N/A{
1N/A int sum;
1N/A imps_cth *local_cth_ptr
1N/A = (imps_cth *) PHYS_TO_VIRTUAL (fps_ptr->cth_ptr);
1N/A
1N/A if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX)
1N/A {
1N/A KERNEL_PRINT ((" Invalid MP System Configuration type %d\n",
1N/A fps_ptr->feature_info[0]));
1N/A return 1;
1N/A }
1N/A
1N/A if (fps_ptr->cth_ptr)
1N/A {
1N/A sum = get_checksum ((unsigned) local_cth_ptr,
1N/A local_cth_ptr->base_length);
1N/A if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum)
1N/A {
1N/A KERNEL_PRINT
1N/A ((" Bad MP Config Table sig 0x%x and/or checksum 0x%x\n",
1N/A (unsigned) (fps_ptr->cth_ptr), sum));
1N/A return 1;
1N/A }
1N/A if (local_cth_ptr->spec_rev != fps_ptr->spec_rev)
1N/A {
1N/A KERNEL_PRINT ((" Bad MP Config Table sub-revision # %d\n", local_cth_ptr->spec_rev));
1N/A return 1;
1N/A }
1N/A if (local_cth_ptr->extended_length)
1N/A {
1N/A sum = (get_checksum (((unsigned) local_cth_ptr)
1N/A + local_cth_ptr->base_length,
1N/A local_cth_ptr->extended_length)
1N/A + local_cth_ptr->extended_checksum) & 0xFF;
1N/A if (sum)
1N/A {
1N/A KERNEL_PRINT
1N/A ((" Bad Extended MP Config Table checksum 0x%x\n", sum));
1N/A return 1;
1N/A }
1N/A }
1N/A }
1N/A else if (!fps_ptr->feature_info[0])
1N/A {
1N/A KERNEL_PRINT ((" Missing configuration information\n"));
1N/A return 1;
1N/A }
1N/A
1N/A return 0;
1N/A}
1N/A
1N/A
1N/Astatic void
1N/Aimps_read_bios (imps_fps * fps_ptr)
1N/A{
1N/A int apicid;
1N/A unsigned cth_start, cth_count;
1N/A imps_cth *local_cth_ptr
1N/A = (imps_cth *) PHYS_TO_VIRTUAL (fps_ptr->cth_ptr);
1N/A char *str_ptr;
1N/A
1N/A KERNEL_PRINT (("Intel MultiProcessor Spec 1.%d BIOS support detected\n",
1N/A fps_ptr->spec_rev));
1N/A
1N/A /*
1N/A * Do all checking of errors which would definitely
1N/A * lead to failure of the SMP boot here.
1N/A */
1N/A
1N/A if (imps_bad_bios (fps_ptr))
1N/A {
1N/A KERNEL_PRINT ((" Disabling MPS support\n"));
1N/A return;
1N/A }
1N/A
1N/A if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT)
1N/A {
1N/A str_ptr = "IMCR and PIC";
1N/A }
1N/A else
1N/A {
1N/A str_ptr = "Virtual Wire";
1N/A }
1N/A if (fps_ptr->cth_ptr)
1N/A {
1N/A imps_lapic_addr = local_cth_ptr->lapic_addr;
1N/A }
1N/A else
1N/A {
1N/A imps_lapic_addr = LAPIC_ADDR_DEFAULT;
1N/A }
1N/A KERNEL_PRINT
1N/A ((" APIC config: \"%s mode\" Local APIC address: 0x%x\n",
1N/A str_ptr, imps_lapic_addr));
1N/A imps_lapic_addr = PHYS_TO_VIRTUAL (imps_lapic_addr);
1N/A
1N/A /*
1N/A * Setup primary CPU.
1N/A */
1N/A apicid = IMPS_LAPIC_READ (LAPIC_SPIV);
1N/A IMPS_LAPIC_WRITE (LAPIC_SPIV, apicid | LAPIC_SPIV_ENABLE_APIC);
1N/A imps_any_new_apics = IMPS_LAPIC_READ (LAPIC_VER) & 0xF0;
1N/A apicid = IMPS_APIC_ID (IMPS_LAPIC_READ (LAPIC_ID));
1N/A imps_cpu_apic_map[0] = apicid;
1N/A imps_apic_cpu_map[apicid] = 0;
1N/A
1N/A if (fps_ptr->cth_ptr)
1N/A {
1N/A char str1[16], str2[16];
1N/A memcpy (str1, local_cth_ptr->oem_id, 8);
1N/A str1[8] = 0;
1N/A memcpy (str2, local_cth_ptr->prod_id, 12);
1N/A str2[12] = 0;
1N/A KERNEL_PRINT ((" OEM id: %s Product id: %s\n", str1, str2));
1N/A cth_start = ((unsigned) local_cth_ptr) + sizeof (imps_cth);
1N/A cth_count = local_cth_ptr->entry_count;
1N/A }
1N/A else
1N/A {
1N/A *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_ID;
1N/A defconfig.ioapic.id
1N/A = IMPS_APIC_ID (*((volatile unsigned *)
1N/A (IOAPIC_ADDR_DEFAULT + IOAPIC_RW)));
1N/A *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_VER;
1N/A defconfig.ioapic.ver
1N/A = APIC_VERSION (*((volatile unsigned *)
1N/A (IOAPIC_ADDR_DEFAULT + IOAPIC_RW)));
1N/A defconfig.proc[apicid].flags
1N/A = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT;
1N/A defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED;
1N/A imps_num_cpus = 2;
1N/A if (fps_ptr->feature_info[0] == 1
1N/A || fps_ptr->feature_info[0] == 5)
1N/A {
1N/A memcpy (defconfig.bus[0].bus_type, "ISA ", 6);
1N/A }
1N/A if (fps_ptr->feature_info[0] == 4
1N/A || fps_ptr->feature_info[0] == 7)
1N/A {
1N/A memcpy (defconfig.bus[0].bus_type, "MCA ", 6);
1N/A }
1N/A if (fps_ptr->feature_info[0] > 4)
1N/A {
1N/A defconfig.proc[0].apic_ver = 0x10;
1N/A defconfig.proc[1].apic_ver = 0x10;
1N/A defconfig.bus[1].type = IMPS_BCT_BUS;
1N/A }
1N/A if (fps_ptr->feature_info[0] == 2)
1N/A {
1N/A defconfig.intin[2].type = 255;
1N/A defconfig.intin[13].type = 255;
1N/A }
1N/A if (fps_ptr->feature_info[0] == 7)
1N/A {
1N/A defconfig.intin[0].type = 255;
1N/A }
1N/A cth_start = (unsigned) &defconfig;
1N/A cth_count = DEF_ENTRIES;
1N/A }
1N/A imps_read_config_table (cth_start, cth_count);
1N/A
1N/A /* %%%%% ESB read extended entries here */
1N/A
1N/A imps_enabled = 1;
1N/A}
1N/A
1N/A
1N/A/*
1N/A * Given a region to check, this actually looks for the "MP Floating
1N/A * Pointer Structure". The return value indicates if the correct
1N/A * signature and checksum for a floating pointer structure of the
1N/A * appropriate spec revision was found. If so, then do not search
1N/A * further.
1N/A *
1N/A * NOTE: The memory scan will always be in the bottom 1 MB.
1N/A *
1N/A * This function presumes that "start" will always be aligned to a 16-bit
1N/A * boundary.
1N/A *
1N/A * Function finished.
1N/A */
1N/A
1N/Astatic int
1N/Aimps_scan (unsigned start, unsigned length)
1N/A{
1N/A IMPS_DEBUG_PRINT (("Scanning from 0x%x for %d bytes\n",
1N/A start, length));
1N/A
1N/A while (length > 0)
1N/A {
1N/A imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL (start);
1N/A
1N/A if (fps_ptr->sig == IMPS_FPS_SIGNATURE
1N/A && fps_ptr->length == 1
1N/A && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4)
1N/A && !get_checksum (start, 16))
1N/A {
1N/A IMPS_DEBUG_PRINT (("Found MP Floating Structure Pointer at %x\n", start));
1N/A imps_read_bios (fps_ptr);
1N/A return 1;
1N/A }
1N/A
1N/A length -= 16;
1N/A start += 16;
1N/A }
1N/A
1N/A return 0;
1N/A}
1N/A
1N/A
1N/A/*
1N/A * This is the primary function for probing for MPS compatible hardware
1N/A * and BIOS information. Call this during the early stages of OS startup,
1N/A * before memory can be messed up.
1N/A *
1N/A * The probe looks for the "MP Floating Pointer Structure" at locations
1N/A * listed at the top of page 4-2 of the spec.
1N/A *
1N/A * Environment requirements from the OS to run:
1N/A *
1N/A * (1) : A non-linear virtual to physical memory mapping is probably OK,
1N/A * as (I think) the structures all fall within page boundaries,
1N/A * but a linear mapping is recommended. Currently assumes that
1N/A * the mapping will remain identical over time (which should be
1N/A * OK since it only accesses memory which shouldn't be munged
1N/A * by the OS anyway).
1N/A * (2) : The OS only consumes memory which the BIOS says is OK to use,
1N/A * and not any of the BIOS standard areas (the areas 0x400 to
1N/A * 0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical
1N/A * RAM). Sometimes a small amount of physical RAM is not
1N/A * reported by the BIOS, to be used to store MPS and other
1N/A * information.
1N/A * (3) : It must be possible to read the CMOS.
1N/A * (4) : There must be between 512K and 640K of lower memory (this is a
1N/A * sanity check).
1N/A *
1N/A * Function finished.
1N/A */
1N/A
1N/Aint
1N/Aimps_probe (void)
1N/A{
1N/A /*
1N/A * Determine possible address of the EBDA
1N/A */
1N/A unsigned ebda_addr = *((unsigned short *)
1N/A PHYS_TO_VIRTUAL (EBDA_SEG_ADDR)) << 4;
1N/A
1N/A /*
1N/A * Determine amount of installed lower memory (not *available*
1N/A * lower memory).
1N/A *
1N/A * NOTE: This should work reliably as long as we verify the
1N/A * machine is at least a system that could possibly have
1N/A * MPS compatibility to begin with.
1N/A */
1N/A unsigned mem_lower = ((CMOS_READ_BYTE (CMOS_BASE_MEMORY + 1) << 8)
1N/A | CMOS_READ_BYTE (CMOS_BASE_MEMORY)) << 10;
1N/A
1N/A#ifdef IMPS_DEBUG
1N/A imps_enabled = 0;
1N/A imps_num_cpus = 1;
1N/A#endif
1N/A
1N/A /*
1N/A * Sanity check : if this isn't reasonable, it is almost impossibly
1N/A * unlikely to be an MPS compatible machine, so return failure.
1N/A */
1N/A if (mem_lower < 512 * 1024 || mem_lower > 640 * 1024)
1N/A {
1N/A return 0;
1N/A }
1N/A
1N/A if (ebda_addr > mem_lower - 1024
1N/A || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL (ebda_addr))
1N/A * 1024 > mem_lower)
1N/A {
1N/A ebda_addr = 0;
1N/A }
1N/A
1N/A if (((ebda_addr && imps_scan (ebda_addr, 1024))
1N/A || (!ebda_addr && imps_scan (mem_lower - 1024, 1024))
1N/A || imps_scan (0xF0000, 0x10000)) && imps_enabled)
1N/A {
1N/A return 1;
1N/A }
1N/A
1N/A /*
1N/A * If no BIOS info on MPS hardware is found, then return failure.
1N/A */
1N/A
1N/A return 0;
1N/A}