1N/A * GRUB -- GRand Unified Bootloader 1N/A * Copyright (C) 2006 Free Software Foundation, Inc. 1N/A * This program is free software; you can redistribute it and/or modify 1N/A * it under the terms of the GNU General Public License as published by 1N/A * the Free Software Foundation; either version 2 of the License, or 1N/A * (at your option) any later version. 1N/A * This program is distributed in the hope that it will be useful, 1N/A * but WITHOUT ANY WARRANTY; without even the implied warranty of 1N/A * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1N/A * GNU General Public License for more details. 1N/A * You should have received a copy of the GNU General Public License 1N/A * along with this program; if not, write to the Free Software 1N/A * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 1N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 1N/A * Use is subject to license terms. 1N/A#
pragma ident "%Z%%M% %I% %E% SMI" 1N/A * This file describes the x86 architecture control registers which 1N/A * are part of the privileged architecture. 1N/A * Many of these definitions are shared between IA-32-style and 1N/A * AMD64-style processors. 1N/A#
define CR0_PG 0x80000000 /* paging enabled */ 1N/A#
define CR0_NW 0x20000000 /* not writethrough */ 1N/A#
define CR0_AM 0x00040000 /* alignment mask */ 1N/A#
define CR0_ET 0x00000010 /* extension type */ 1N/A#
define CR0_MP 0x00000002 /* monitor coprocessor */ 1N/A#
define CR0_PE 0x00000001 /* protection enabled */ 1N/A/* XX64 eliminate these compatibility defines */ 1N/A "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 1N/A#
define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 1N/A#
define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 1N/A#
define CR4_DE 0x0008 /* debugging extensions */ 1N/A#
define CR4_PAE 0x0020 /* physical address extension */ 1N/A#
define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 1N/A "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 1N/A/* Intel's SYSENTER configuration registers */ 1N/A/* AMD's EFER register */ 1N/A "\20\14nxe\13lma\11lme\1sce" 1N/A/* AMD's SYSCFG register */ 1N/A "\20\26tom2\25mvdm\24mfdm\23mfde" 1N/A/* AMD's FS.base and GS.base MSRs */ 1N/A/* AMD's configuration MSRs, weakly documented in the revision guide */ 1N/A/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 1N/A#
endif /* !_SYS_CONTROLREGS_H */