1N/A#if !defined(PCI_H) && defined(CONFIG_PCI)
1N/A#define PCI_H
1N/A
1N/A/*
1N/A** Support for NE2000 PCI clones added David Monro June 1997
1N/A** Generalised for other PCI NICs by Ken Yap July 1997
1N/A**
1N/A** Most of this is taken from:
1N/A**
1N/A** /usr/src/linux/drivers/pci/pci.c
1N/A** /usr/src/linux/include/linux/pci.h
1N/A** /usr/src/linux/arch/i386/bios32.c
1N/A** /usr/src/linux/include/linux/bios32.h
1N/A** /usr/src/linux/drivers/net/ne.c
1N/A*/
1N/A
1N/A/*
1N/A * This program is free software; you can redistribute it and/or
1N/A * modify it under the terms of the GNU General Public License as
1N/A * published by the Free Software Foundation; either version 2, or (at
1N/A * your option) any later version.
1N/A */
1N/A
1N/A#include "pci_ids.h"
1N/A
1N/A#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
1N/A#define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */
1N/A#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
1N/A#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
1N/A#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
1N/A#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
1N/A#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
1N/A#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
1N/A#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
1N/A#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
1N/A#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
1N/A
1N/A#define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
1N/A#define PCIBIOS_PCI_BIOS_PRESENT 0xb101
1N/A#define PCIBIOS_FIND_PCI_DEVICE 0xb102
1N/A#define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
1N/A#define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
1N/A#define PCIBIOS_READ_CONFIG_BYTE 0xb108
1N/A#define PCIBIOS_READ_CONFIG_WORD 0xb109
1N/A#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
1N/A#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
1N/A#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
1N/A#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
1N/A
1N/A#define PCI_VENDOR_ID 0x00 /* 16 bits */
1N/A#define PCI_DEVICE_ID 0x02 /* 16 bits */
1N/A#define PCI_COMMAND 0x04 /* 16 bits */
1N/A
1N/A#define PCI_STATUS 0x06 /* 16 bits */
1N/A#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
1N/A#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
1N/A#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
1N/A#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
1N/A#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
1N/A#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
1N/A#define PCI_STATUS_DEVSEL_FAST 0x000
1N/A#define PCI_STATUS_DEVSEL_MEDIUM 0x200
1N/A#define PCI_STATUS_DEVSEL_SLOW 0x400
1N/A#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
1N/A#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
1N/A#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
1N/A#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
1N/A#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
1N/A
1N/A#define PCI_REVISION 0x08 /* 8 bits */
1N/A#define PCI_REVISION_ID 0x08 /* 8 bits */
1N/A#define PCI_CLASS_REVISION 0x08 /* 32 bits */
1N/A#define PCI_CLASS_CODE 0x0b /* 8 bits */
1N/A#define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
1N/A#define PCI_HEADER_TYPE 0x0e /* 8 bits */
1N/A#define PCI_HEADER_TYPE_NORMAL 0
1N/A#define PCI_HEADER_TYPE_BRIDGE 1
1N/A#define PCI_HEADER_TYPE_CARDBUS 2
1N/A
1N/A
1N/A/* Header type 0 (normal devices) */
1N/A#define PCI_CARDBUS_CIS 0x28
1N/A#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
1N/A#define PCI_SUBSYSTEM_ID 0x2e
1N/A
1N/A#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
1N/A#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
1N/A#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
1N/A#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
1N/A#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
1N/A#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
1N/A
1N/A#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
1N/A#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
1N/A#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
1N/A#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
1N/A
1N/A#ifndef PCI_BASE_ADDRESS_IO_MASK
1N/A#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
1N/A#endif
1N/A#ifndef PCI_BASE_ADDRESS_MEM_MASK
1N/A#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
1N/A#endif
1N/A#define PCI_BASE_ADDRESS_SPACE_IO 0x01
1N/A#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
1N/A#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
1N/A bits 31..11 are address,
1N/A 10..2 are reserved */
1N/A
1N/A#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
1N/A
1N/A#define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */
1N/A#define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */
1N/A
1N/A/* Header type 1 (PCI-to-PCI bridges) */
1N/A#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
1N/A#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
1N/A#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
1N/A#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
1N/A#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
1N/A#define PCI_IO_LIMIT 0x1d
1N/A#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
1N/A#define PCI_IO_RANGE_TYPE_16 0x00
1N/A#define PCI_IO_RANGE_TYPE_32 0x01
1N/A#define PCI_IO_RANGE_MASK ~0x0f
1N/A#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
1N/A#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
1N/A#define PCI_MEMORY_LIMIT 0x22
1N/A#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
1N/A#define PCI_MEMORY_RANGE_MASK ~0x0f
1N/A#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
1N/A#define PCI_PREF_MEMORY_LIMIT 0x26
1N/A#define PCI_PREF_RANGE_TYPE_MASK 0x0f
1N/A#define PCI_PREF_RANGE_TYPE_32 0x00
1N/A#define PCI_PREF_RANGE_TYPE_64 0x01
1N/A#define PCI_PREF_RANGE_MASK ~0x0f
1N/A#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
1N/A#define PCI_PREF_LIMIT_UPPER32 0x2c
1N/A#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
1N/A#define PCI_IO_LIMIT_UPPER16 0x32
1N/A/* 0x34 same as for htype 0 */
1N/A/* 0x35-0x3b is reserved */
1N/A#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
1N/A/* 0x3c-0x3d are same as for htype 0 */
1N/A#define PCI_BRIDGE_CONTROL 0x3e
1N/A#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
1N/A#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
1N/A#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
1N/A#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
1N/A#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
1N/A#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
1N/A#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
1N/A
1N/A#define PCI_CB_CAPABILITY_LIST 0x14
1N/A
1N/A/* Capability lists */
1N/A
1N/A#define PCI_CAP_LIST_ID 0 /* Capability ID */
1N/A#define PCI_CAP_ID_PM 0x01 /* Power Management */
1N/A#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
1N/A#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
1N/A#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
1N/A#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
1N/A#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
1N/A#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
1N/A#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
1N/A#define PCI_CAP_SIZEOF 4
1N/A
1N/A/* Power Management Registers */
1N/A
1N/A#define PCI_PM_PMC 2 /* PM Capabilities Register */
1N/A#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
1N/A#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
1N/A#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
1N/A#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
1N/A#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
1N/A#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
1N/A#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
1N/A#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
1N/A#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
1N/A#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
1N/A#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
1N/A#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
1N/A#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
1N/A#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
1N/A#define PCI_PM_CTRL 4 /* PM control and status register */
1N/A#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
1N/A#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
1N/A#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
1N/A#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
1N/A#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
1N/A#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
1N/A#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
1N/A#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
1N/A#define PCI_PM_DATA_REGISTER 7 /* (??) */
1N/A#define PCI_PM_SIZEOF 8
1N/A
1N/A/* AGP registers */
1N/A
1N/A#define PCI_AGP_VERSION 2 /* BCD version number */
1N/A#define PCI_AGP_RFU 3 /* Rest of capability flags */
1N/A#define PCI_AGP_STATUS 4 /* Status register */
1N/A#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
1N/A#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
1N/A#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
1N/A#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
1N/A#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
1N/A#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
1N/A#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
1N/A#define PCI_AGP_COMMAND 8 /* Control register */
1N/A#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
1N/A#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
1N/A#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
1N/A#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
1N/A#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
1N/A#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
1N/A#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
1N/A#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
1N/A#define PCI_AGP_SIZEOF 12
1N/A
1N/A/* Slot Identification */
1N/A
1N/A#define PCI_SID_ESR 2 /* Expansion Slot Register */
1N/A#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
1N/A#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
1N/A#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
1N/A
1N/A/* Message Signalled Interrupts registers */
1N/A
1N/A#define PCI_MSI_FLAGS 2 /* Various flags */
1N/A#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
1N/A#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
1N/A#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
1N/A#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
1N/A#define PCI_MSI_RFU 3 /* Rest of capability flags */
1N/A#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
1N/A#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
1N/A#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
1N/A#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
1N/A
1N/A#define PCI_SLOT(devfn) ((devfn) >> 3)
1N/A#define PCI_FUNC(devfn) ((devfn) & 0x07)
1N/A
1N/A#define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
1N/A
1N/A/* PCI signature: "PCI " */
1N/A#define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
1N/A
1N/A/* PCI service signature: "$PCI" */
1N/A#define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
1N/A
1N/Aunion bios32 {
1N/A struct {
1N/A unsigned long signature; /* _32_ */
1N/A unsigned long entry; /* 32 bit physical address */
1N/A unsigned char revision; /* Revision level, 0 */
1N/A unsigned char length; /* Length in paragraphs should be 01 */
1N/A unsigned char checksum; /* All bytes must add up to zero */
1N/A unsigned char reserved[5]; /* Must be zero */
1N/A } fields;
1N/A char chars[16];
1N/A};
1N/A
1N/Astruct pci_device;
1N/Astruct dev;
1N/Atypedef int (*pci_probe_t)(struct dev *, struct pci_device *);
1N/A
1N/Astruct pci_device {
1N/A uint32_t class;
1N/A uint16_t vendor, dev_id;
1N/A const char *name;
1N/A /* membase and ioaddr are silly and depricated */
1N/A unsigned int membase;
1N/A unsigned int ioaddr;
1N/A unsigned int romaddr;
1N/A unsigned char irq;
1N/A unsigned char devfn;
1N/A unsigned char bus;
1N/A unsigned char use_specified;
1N/A const struct pci_driver *driver;
1N/A};
1N/A
1N/Aextern void scan_pci_bus(int type, struct pci_device *dev);
1N/Aextern void find_pci(int type, struct pci_device *dev);
1N/A
1N/Aextern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value);
1N/Aextern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value);
1N/Aextern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value);
1N/Aextern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value);
1N/Aextern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value);
1N/Aextern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value);
1N/Aextern unsigned long pcibios_bus_base(unsigned int bus);
1N/Aextern void adjust_pci_device(struct pci_device *p);
1N/A
1N/A
1N/Astatic inline int
1N/Apci_read_config_byte(struct pci_device *dev, unsigned int where, uint8_t *value)
1N/A{
1N/A return pcibios_read_config_byte(dev->bus, dev->devfn, where, value);
1N/A}
1N/Astatic inline int
1N/Apci_write_config_byte(struct pci_device *dev, unsigned int where, uint8_t value)
1N/A{
1N/A return pcibios_write_config_byte(dev->bus, dev->devfn, where, value);
1N/A}
1N/Astatic inline int
1N/Apci_read_config_word(struct pci_device *dev, unsigned int where, uint16_t *value)
1N/A{
1N/A return pcibios_read_config_word(dev->bus, dev->devfn, where, value);
1N/A}
1N/Astatic inline int
1N/Apci_write_config_word(struct pci_device *dev, unsigned int where, uint16_t value)
1N/A{
1N/A return pcibios_write_config_word(dev->bus, dev->devfn, where, value);
1N/A}
1N/Astatic inline int
1N/Apci_read_config_dword(struct pci_device *dev, unsigned int where, uint32_t *value)
1N/A{
1N/A return pcibios_read_config_dword(dev->bus, dev->devfn, where, value);
1N/A}
1N/Astatic inline int
1N/Apci_write_config_dword(struct pci_device *dev, unsigned int where, uint32_t value)
1N/A{
1N/A return pcibios_write_config_dword(dev->bus, dev->devfn, where, value);
1N/A}
1N/A
1N/A/* Helper functions to find the size of a pci bar */
1N/Aextern unsigned long pci_bar_start(struct pci_device *dev, unsigned int bar);
1N/Aextern unsigned long pci_bar_size(struct pci_device *dev, unsigned int bar);
1N/A/* Helper function to find pci capabilities */
1N/Aextern int pci_find_capability(struct pci_device *dev, int cap);
1N/Astruct pci_id {
1N/A unsigned short vendor, dev_id;
1N/A const char *name;
1N/A};
1N/A
1N/Astruct dev;
1N/A/* Most pci drivers will use this */
1N/Astruct pci_driver {
1N/A int type;
1N/A const char *name;
1N/A pci_probe_t probe;
1N/A struct pci_id *ids;
1N/A int id_count;
1N/A
1N/A/* On a few occasions the hardware is standardized enough that
1N/A * we only need to know the class of the device and not the exact
1N/A * type to drive the device correctly. If this is the case
1N/A * set a class value other than 0.
1N/A */
1N/A unsigned short class;
1N/A};
1N/A
1N/A#define PCI_ROM(VENDOR_ID, DEVICE_ID, IMAGE, DESCRIPTION) \
1N/A { VENDOR_ID, DEVICE_ID, IMAGE, }
1N/A
1N/A#endif /* PCI_H */