1N/A/* Offsets to registers (using SMC names). */ 1N/A NVCTL =
0x10,
/* Non Volatile Control */ 1N/A TEST =
0x1C,
/* Test register: marked as reserved (see in source code) */ 1N/A ALICNT =
0x24,
/* Frame Alignment Error Counter */ 1N/A MPCNT =
0x28,
/* Missed Packet Counter */ 1N/A MMCTL =
0x30,
/* MII Management Interface Control */ 1N/A MMDATA =
0x34,
/* MII Management Interface Data */ 1N/A IPG =
0x3C,
/* InterPacket Gap */ 1N/A LAN0 =
0x40,
/* MAC address. (0x40-0x48) */ 1N/A MC0 =
0x50,
/* Multicast filter table. (0x50-0x5c) */ 1N/A PRCDAR =
0x84,
/* PCI Receive Current Descriptor Address */ 1N/A PTCDAR =
0xC4,
/* PCI Transmit Current Descriptor Address */ 1N/A/* Command register (CR_) bits */ 1N/A/* Interrupt register bits. NI means No Interrupt generated */ 1N/A/* General Control (GC_) bits */ 1N/A * Receive FIFO Threshold values 1N/A * Control the level at which the PCI burst state machine 1N/A * begins to empty the receive FIFO. Possible values: 0-3 1N/A * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes. 1N/A/* Memory Read Control (MRC_) values */ 1N/A/* Definitions of the Receive Control (RC_) register bits */ 1N/A/* description of the rx descriptors control bits */ 1N/A/* Definition of the Transmit CONTROL (TC) register bits */ 1N/A/* Loopback Mode (LM_) Select valuesbits */ 1N/A/* Bytes transferred to chip before transmission starts. */ 1N/A/* description of rx descriptors status bits */ 1N/A/* description of tx descriptors status bits */ 1N/A/* description of the tx descriptors control bits */ 1N/A#
define TD_IAF (
0x0004)
/* Generate Interrupt after tx */ 1N/A#
endif /* _EPIC100_H_ */