1N/A * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 1N/A * Redistribution and use in source and binary forms, with or without 1N/A * modification, are permitted provided that the following conditions are 1N/A * met: 1. Redistributions of source code must retain the above copyright 1N/A * notice, this list of conditions and the following disclaimer. 2. The name 1N/A * of the author may not be used to endorse or promote products derived from 1N/A * this software without specific prior written permission 1N/A * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 1N/A * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 1N/A * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 1N/A * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1N/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 1N/A * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 1N/A * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 1N/A * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 1N/A * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 1N/A * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 1N/A Modified by: Andres Vega Garcia 1N/A INRIA - Sophia Antipolis, France 1N/A e-mail: avega@sophia.inria.fr 1N/A finger: avega@pax.inria.fr 1N/A * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the 1N/A * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> 1N/A * Ethernet software status per interface. 1N/A * Some global constants 1N/A * some macros to acces long named fields 1N/A * Commands to read/write EEPROM trough EEPROM command register (Window 0, 1N/A * Some short functions, worth to let them be a macro 1N/A/************************************************************************** 1N/A * These define the EEPROM data structure. They are used in the probe 1N/A * function to verify the existence of the adapter after having sent 1N/A * There are others but only the ones we use are defined here. 1N/A **************************************************************************/ 1N/A/************************************************************************** 1N/A * These are the registers for the 3Com 3c509 and their bit patterns when * 1N/A * applicable. They have been taken out the the "EtherLink III Parallel * 1N/A * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 1N/A **************************************************************************/ 1N/A * Window 0 registers. Setup. 1N/A * Window 1 registers. Operating Set. 1N/A * Window 3 registers. FIFO Management. 1N/A * Window 4 registers. Diagnostics. 1N/A * Window 5 Registers. Results and Internal status. 1N/A * Window 6 registers. Statistics. 1N/A/**************************************** 1N/A * Register definitions. 1N/A ****************************************/ 1N/A * Command register. All windows. 1N/A * 15-11: 5-bit code for command to be executed. 1N/A * 10-0: 11-bit arg if any. For commands with no args; 1N/A * this can be set to anything. 1N/A * this is needed. If 1N/A * before using trans- 1N/A#
define RX_DISABLE (
unsigned short) (
0x3<<
11)
/* state disabled on 1N/A * The following C_* acknowledge the various interrupts. Some of them don't 1N/A * do anything. See the manual. 1N/A * Status register. All windows. 1N/A * 15-13: Window number(0-7). 1N/A * 12: Command_in_progress. 1N/A * 7: Update Statistics. 1N/A * 6: Interrupt Requested. 1N/A * 1: Adapter Failure. 1N/A * 0: Interrupt Latch. 1N/A/* Address Config. Register. 1N/A * FIFO Registers. RX Status. 1N/A * 15: Incomplete or FIFO empty. 1N/A * 14: 1: Error in RX Packet 0: Incomplete or no error. 1N/A * 13-11: Type of error. 1N/A * 1011 = Run Packet Error. 1N/A * 1100 = Alignment Error. 1N/A * 1001 = Oversize Packet Error (>1514 bytes) 1N/A * 0010 = Dribble Bits. 1N/A * (all other error codes, no errors.) 1N/A * 10-0: RX Bytes (0-1514) 1N/A * Reports the transmit status of a completed transmission. Writing this 1N/A * register pops the transmit completion stack. 1N/A * Window 1/Port 0x0b. 1N/A * 6: Interrupt on successful transmission requested. 1N/A * 5: Jabber Error (TP Only, TX Reset required. ) 1N/A * 4: Underrun (TX Reset required. ) 1N/A * 3: Maximum Collisions. 1N/A * 2: TX Status Overflow. 1N/A * FIFO Status (Window 4) 1N/A * Supports FIFO diagnostics 1N/A * Window 4/Port 0x04.1 1N/A * 15: 1=RX receiving (RO). Set when a packet is being received 1N/A * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 1N/A * Requires RX Reset or Global Reset command to recover. 1N/A * It is generated when you read past the end of a packet - 1N/A * reading past what has been received so far will give bad 1N/A * 12: 1=RX status overrun (RO). Set when there are already 8 1N/A * packets in the RX FIFO. While this bit is set, no additional 1N/A * packets are received. Requires no action on the part of 1N/A * the host. The condition is cleared once a packet has been 1N/A * read out of the RX FIFO. 1N/A * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 1N/A * may not be an overrun packet yet). While this bit is set, 1N/A * no additional packets will be received (some additional 1N/A * bytes can still be pending between the wire and the RX 1N/A * FIFO). Requires no action on the part of the host. The 1N/A * condition is cleared once a few bytes have been read out 1N/A * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 1N/A * Requires TX Reset or Global Reset command to recover. 1N/A * Disables Transmitter. 1N/A * 7-0: Built in self test bits for the RX and TX FIFO's. 1N/A * Misc defines for various things.