1631N/A * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 0N/A * This code is free software; you can redistribute it and/or modify it 0N/A * under the terms of the GNU General Public License version 2 only, as 0N/A * published by the Free Software Foundation. 0N/A * This code is distributed in the hope that it will be useful, but WITHOUT 0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 0N/A * version 2 for more details (a copy is included in the LICENSE file that 0N/A * accompanied this code). 0N/A * You should have received a copy of the GNU General Public License version 0N/A * 2 along with this work; if not, write to the Free Software Foundation, 0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 0N/A// Memory Access Ordering Model 0N/A// This interface is based on the JSR-133 Cookbook for Compiler Writers 0N/A// and on the IA64 memory model. It is the dynamic equivalent of the 0N/A// C/C++ volatile specifier. I.e., volatility restricts compile-time 0N/A// memory access reordering in a way similar to what we want to occur 0N/A// In the following, the terms 'previous', 'subsequent', 'before', 605N/A// 'after', 'preceding' and 'succeeding' refer to program order. The 0N/A// terms 'down' and 'below' refer to forward load or store motion 0N/A// relative to program order, while 'up' and 'above' refer to backward 0N/A// We define four primitive memory barrier operations. 0N/A// LoadLoad: Load1(s); LoadLoad; Load2 0N/A// Ensures that Load1 completes (obtains the value it loads from memory) 0N/A// before Load2 and any subsequent load operations. Loads before Load1 0N/A// may *not* float below Load2 and any subsequent load operations. 0N/A// StoreStore: Store1(s); StoreStore; Store2 0N/A// Ensures that Store1 completes (the effect on memory of Store1 is made 0N/A// visible to other processors) before Store2 and any subsequent store 0N/A// operations. Stores before Store1 may *not* float below Store2 and any 0N/A// subsequent store operations. 0N/A// LoadStore: Load1(s); LoadStore; Store2 0N/A// Ensures that Load1 completes before Store2 and any subsequent store 0N/A// operations. Loads before Load1 may *not* float below Store2 and any 0N/A// subseqeuent store operations. 0N/A// StoreLoad: Store1(s); StoreLoad; Load2 0N/A// Ensures that Store1 completes before Load2 and any subsequent load 0N/A// operations. Stores before Store1 may *not* float below Load2 and any 0N/A// subseqeuent load operations. 0N/A// We define two further operations, 'release' and 'acquire'. They are 0N/A// mirror images of each other. 0N/A// Execution by a processor of release makes the effect of all memory 0N/A// accesses issued by it previous to the release visible to all 0N/A// processors *before* the release completes. The effect of subsequent 0N/A// memory accesses issued by it *may* be made visible *before* the 0N/A// release. I.e., subsequent memory accesses may float above the 0N/A// release, but prior ones may not float below it. 0N/A// Execution by a processor of acquire makes the effect of all memory 0N/A// accesses issued by it subsequent to the acquire visible to all 0N/A// processors *after* the acquire completes. The effect of prior memory 0N/A// accesses issued by it *may* be made visible *after* the acquire. 0N/A// I.e., prior memory accesses may float below the acquire, but 0N/A// subsequent ones may not float above it. 0N/A// Finally, we define a 'fence' operation, which conceptually is a 0N/A// release combined with an acquire. In the real world these operations 0N/A// require one or more machine instructions which can float above and 0N/A// below the release or acquire, so we usually can't just issue the 0N/A// release-acquire back-to-back. All machines we know of implement some 0N/A// sort of memory fence instruction. 0N/A// The standalone implementations of release and acquire need an associated 0N/A// dummy volatile store or load respectively. To avoid redundant operations, 0N/A// we can define the composite operators: 'release_store', 'store_fence' and 0N/A// 'load_acquire'. Here's a summary of the machine instructions corresponding 0N/A// to each operation. 0N/A// sparc RMO ia64 x86 0N/A// --------------------------------------------------------------------- 0N/A// fence membar #LoadStore | mf lock addl 0,(sp) 0N/A// release membar #LoadStore | st.rel [sp]=r0 movl $0,<dummy> 0N/A// acquire ld [%sp],%g0 ld.acq <r>=[sp] movl (sp),<r> 0N/A// membar #LoadLoad | 0N/A// release_store membar #LoadStore | st.rel <store> 0N/A// store_fence st st lock xchg 0N/A// load_acquire ld ld.acq <load> 0N/A// membar #LoadLoad | 0N/A// Using only release_store and load_acquire, we can implement the 0N/A// following ordered sequences. 0N/A// 1. load, load == load_acquire, load 0N/A// or load_acquire, load_acquire 0N/A// 2. load, store == load, release_store 0N/A// or load_acquire, store 0N/A// or load_acquire, release_store 0N/A// 3. store, store == store, release_store 0N/A// or release_store, release_store 0N/A// These require no membar instructions for sparc-TSO and no extra 0N/A// instructions for ia64. 0N/A// Ordering a load relative to preceding stores requires a store_fence, 0N/A// which implies a membar #StoreLoad between the store and load under 0N/A// sparc-TSO. A fence is required by ia64. On x86, we use locked xchg. 0N/A// 4. store, load == store_fence, load 0N/A// Use store_fence to make sure all stores done in an 'interesting' 0N/A// region are made visible prior to both subsequent loads and stores. 0N/A// Conventional usage is to issue a load_acquire for ordered loads. Use 0N/A// release_store for ordered stores when you care only that prior stores 0N/A// are visible before the release_store, but don't care exactly when the 0N/A// store associated with the release_store becomes visible. Use 0N/A// release_store_fence to update values like the thread state, where we 0N/A// don't want the current thread to continue until all our prior memory 0N/A// accesses (including the new thread state) are visible to other threads. 0N/A// C++ guarantees ordering at operations termed 'sequence points' (defined 0N/A// to be volatile accesses and calls to library I/O functions). 'Side 0N/A// effects' (defined as volatile accesses, calls to library I/O functions 0N/A// and object modification) previous to a sequence point must be visible 0N/A// at that sequence point. See the C++ standard, section 1.9, titled 0N/A// "Program Execution". This means that all barrier implementations, 0N/A// including standalone loadload, storestore, loadstore, storeload, acquire 0N/A// and release must include a sequence point, usually via a volatile memory 0N/A// access. Other ways to guarantee a sequence point are, e.g., use of 0N/A// indirect calls and linux's __asm__ volatile. 1631N/A// Note: as of 6973570, we have replaced the originally static "dummy" field 1631N/A// (see above) by a volatile store to the stack. All of the versions of the 1631N/A// compilers that we currently use (SunStudio, gcc and VC++) respect the 1631N/A// semantics of volatile here. If you build HotSpot using other 1631N/A// compilers, you may need to verify that no compiler reordering occurs 1631N/A// across the sequence point respresented by the volatile access. 0N/A// os::is_MP Considered Redundant 0N/A// Callers of this interface do not need to test os::is_MP() before 0N/A// issuing an operation. The test is taken care of by the implementation 0N/A// of the interface (depending on the vm version and platform, the test 0N/A// may or may not be actually done by the implementation). 0N/A// A Note on Memory Ordering and Cache Coherency 0N/A// Cache coherency and memory ordering are orthogonal concepts, though they 0N/A// interact. E.g., all existing itanium machines are cache-coherent, but 0N/A// the hardware can freely reorder loads wrt other loads unless it sees a 0N/A// load-acquire instruction. All existing sparc machines are cache-coherent 0N/A// and, unlike itanium, TSO guarantees that the hardware orders loads wrt 0N/A// loads and stores, and stores wrt to each other. 0N/A// Consider the implementation of loadload. *If* your platform *isn't* 0N/A// cache-coherent, then loadload must not only prevent hardware load 0N/A// instruction reordering, but it must *also* ensure that subsequent 0N/A// loads from addresses that could be written by other processors (i.e., 0N/A// that are broadcast by other processors) go all the way to the first 0N/A// level of memory shared by those processors and the one issuing 0N/A// So if we have a MP that has, say, a per-processor D$ that doesn't see 0N/A// writes by other processors, and has a shared E$ that does, the loadload 0N/A// barrier would have to make sure that either 0N/A// 1. cache lines in the issuing processor's D$ that contained data from 0N/A// addresses that could be written by other processors are invalidated, so 0N/A// subsequent loads from those addresses go to the E$, (it could do this 0N/A// by tagging such cache lines as 'shared', though how to tell the hardware 0N/A// to do the tagging is an interesting problem), or 0N/A// 2. there never are such cache lines in the issuing processor's D$, which 0N/A// means all references to shared data (however identified: see above) 0N/A// bypass the D$ (i.e., are satisfied from the E$). 0N/A// If your machine doesn't have an E$, substitute 'main memory' for 'E$'. 0N/A// Either of these alternatives is a pain, so no current machine we know of 0N/A// has incoherent caches. 0N/A// If loadload didn't have these properties, the store-release sequence for 0N/A// publishing a shared data structure wouldn't work, because a processor 0N/A// trying to read data newly published by another processor might go to 0N/A// its own incoherent caches to satisfy the read instead of to the newly 0N/A// written shared memory. 0N/A// A Note on MutexLocker and Friends 0N/A// and friends' constructors do a fence, a lock and an acquire *in that 0N/A// order*. And that their destructors do a release and unlock, in *that* 0N/A// order. If their implementations change such that these assumptions 0N/A// are violated, a whole lot of code will break. 671N/A // This is a helper that invokes the StubRoutines::fence_entry() 671N/A // routine if it exists, It should only be used by platforms that 671N/A // don't another way to do the inline eassembly. 1879N/A#
endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP