0N/A/*
2273N/A * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
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0N/A */
0N/A
1879N/A#ifndef SHARE_VM_OPTO_OUTPUT_HPP
1879N/A#define SHARE_VM_OPTO_OUTPUT_HPP
1879N/A
1879N/A#include "opto/block.hpp"
1879N/A#include "opto/node.hpp"
1879N/A#ifdef TARGET_ARCH_MODEL_x86_32
1879N/A# include "adfiles/ad_x86_32.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_MODEL_x86_64
1879N/A# include "adfiles/ad_x86_64.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_MODEL_sparc
1879N/A# include "adfiles/ad_sparc.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_MODEL_zero
1879N/A# include "adfiles/ad_zero.hpp"
1879N/A#endif
2073N/A#ifdef TARGET_ARCH_MODEL_arm
2073N/A# include "adfiles/ad_arm.hpp"
2073N/A#endif
2073N/A#ifdef TARGET_ARCH_MODEL_ppc
2073N/A# include "adfiles/ad_ppc.hpp"
2073N/A#endif
1879N/A
0N/Aclass Arena;
0N/Aclass Bundle;
0N/Aclass Block;
0N/Aclass Block_Array;
0N/Aclass Node;
0N/Aclass Node_Array;
0N/Aclass Node_List;
0N/Aclass PhaseCFG;
0N/Aclass PhaseChaitin;
0N/Aclass Pipeline_Use_Element;
0N/Aclass Pipeline_Use;
0N/A
0N/A#ifndef PRODUCT
0N/A#define DEBUG_ARG(x) , x
0N/A#else
0N/A#define DEBUG_ARG(x)
0N/A#endif
0N/A
0N/A// Define the initial sizes for allocation of the resizable code buffer
0N/Aenum {
0N/A initial_code_capacity = 16 * 1024,
0N/A initial_stub_capacity = 4 * 1024,
0N/A initial_const_capacity = 4 * 1024,
0N/A initial_locs_capacity = 3 * 1024
0N/A};
0N/A
0N/A//------------------------------Scheduling----------------------------------
0N/A// This class contains all the information necessary to implement instruction
0N/A// scheduling and bundling.
0N/Aclass Scheduling {
0N/A
0N/Aprivate:
0N/A // Arena to use
0N/A Arena *_arena;
0N/A
0N/A // Control-Flow Graph info
0N/A PhaseCFG *_cfg;
0N/A
0N/A // Register Allocation info
0N/A PhaseRegAlloc *_regalloc;
0N/A
0N/A // Number of nodes in the method
0N/A uint _node_bundling_limit;
0N/A
0N/A // List of scheduled nodes. Generated in reverse order
0N/A Node_List _scheduled;
0N/A
0N/A // List of nodes currently available for choosing for scheduling
0N/A Node_List _available;
0N/A
0N/A // Mapping from node (index) to basic block
0N/A Block_Array& _bbs;
0N/A
0N/A // For each instruction beginning a bundle, the number of following
0N/A // nodes to be bundled with it.
0N/A Bundle *_node_bundling_base;
0N/A
0N/A // Mapping from register to Node
0N/A Node_List _reg_node;
0N/A
0N/A // Free list for pinch nodes.
0N/A Node_List _pinch_free_list;
0N/A
0N/A // Latency from the beginning of the containing basic block (base 1)
0N/A // for each node.
0N/A unsigned short *_node_latency;
0N/A
0N/A // Number of uses of this node within the containing basic block.
0N/A short *_uses;
0N/A
0N/A // Schedulable portion of current block. Skips Region/Phi/CreateEx up
0N/A // front, branch+proj at end. Also skips Catch/CProj (same as
0N/A // branch-at-end), plus just-prior exception-throwing call.
0N/A uint _bb_start, _bb_end;
0N/A
0N/A // Latency from the end of the basic block as scheduled
0N/A unsigned short *_current_latency;
0N/A
0N/A // Remember the next node
0N/A Node *_next_node;
0N/A
0N/A // Use this for an unconditional branch delay slot
0N/A Node *_unconditional_delay_slot;
0N/A
0N/A // Pointer to a Nop
0N/A MachNopNode *_nop;
0N/A
0N/A // Length of the current bundle, in instructions
0N/A uint _bundle_instr_count;
0N/A
0N/A // Current Cycle number, for computing latencies and bundling
0N/A uint _bundle_cycle_number;
0N/A
0N/A // Bundle information
0N/A Pipeline_Use_Element _bundle_use_elements[resource_count];
0N/A Pipeline_Use _bundle_use;
0N/A
0N/A // Dump the available list
0N/A void dump_available() const;
0N/A
0N/Apublic:
0N/A Scheduling(Arena *arena, Compile &compile);
0N/A
0N/A // Destructor
0N/A NOT_PRODUCT( ~Scheduling(); )
0N/A
0N/A // Step ahead "i" cycles
0N/A void step(uint i);
0N/A
0N/A // Step ahead 1 cycle, and clear the bundle state (for example,
0N/A // at a branch target)
0N/A void step_and_clear();
0N/A
0N/A Bundle* node_bundling(const Node *n) {
0N/A assert(valid_bundle_info(n), "oob");
0N/A return (&_node_bundling_base[n->_idx]);
0N/A }
0N/A
0N/A bool valid_bundle_info(const Node *n) const {
0N/A return (_node_bundling_limit > n->_idx);
0N/A }
0N/A
0N/A bool starts_bundle(const Node *n) const {
0N/A return (_node_bundling_limit > n->_idx && _node_bundling_base[n->_idx].starts_bundle());
0N/A }
0N/A
0N/A // Do the scheduling
0N/A void DoScheduling();
0N/A
0N/A // Compute the local latencies walking forward over the list of
0N/A // nodes for a basic block
0N/A void ComputeLocalLatenciesForward(const Block *bb);
0N/A
0N/A // Compute the register antidependencies within a basic block
0N/A void ComputeRegisterAntidependencies(Block *bb);
0N/A void verify_do_def( Node *n, OptoReg::Name def, const char *msg );
0N/A void verify_good_schedule( Block *b, const char *msg );
0N/A void anti_do_def( Block *b, Node *def, OptoReg::Name def_reg, int is_def );
0N/A void anti_do_use( Block *b, Node *use, OptoReg::Name use_reg );
0N/A
0N/A // Add a node to the current bundle
0N/A void AddNodeToBundle(Node *n, const Block *bb);
0N/A
0N/A // Add a node to the list of available nodes
0N/A void AddNodeToAvailableList(Node *n);
0N/A
0N/A // Compute the local use count for the nodes in a block, and compute
0N/A // the list of instructions with no uses in the block as available
0N/A void ComputeUseCount(const Block *bb);
0N/A
0N/A // Choose an instruction from the available list to add to the bundle
0N/A Node * ChooseNodeToBundle();
0N/A
0N/A // See if this Node fits into the currently accumulating bundle
0N/A bool NodeFitsInBundle(Node *n);
0N/A
0N/A // Decrement the use count for a node
0N/A void DecrementUseCounts(Node *n, const Block *bb);
0N/A
0N/A // Garbage collect pinch nodes for reuse by other blocks.
0N/A void garbage_collect_pinch_nodes();
0N/A // Clean up a pinch node for reuse (helper for above).
0N/A void cleanup_pinch( Node *pinch );
0N/A
0N/A // Information for statistics gathering
0N/A#ifndef PRODUCT
0N/Aprivate:
0N/A // Gather information on size of nops relative to total
0N/A uint _branches, _unconditional_delays;
0N/A
0N/A static uint _total_nop_size, _total_method_size;
0N/A static uint _total_branches, _total_unconditional_delays;
0N/A static uint _total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+1];
0N/A
0N/Apublic:
0N/A static void print_statistics();
0N/A
0N/A static void increment_instructions_per_bundle(uint i) {
0N/A _total_instructions_per_bundle[i]++;
0N/A }
0N/A
0N/A static void increment_nop_size(uint s) {
0N/A _total_nop_size += s;
0N/A }
0N/A
0N/A static void increment_method_size(uint s) {
0N/A _total_method_size += s;
0N/A }
0N/A#endif
0N/A
0N/A};
1879N/A
1879N/A#endif // SHARE_VM_OPTO_OUTPUT_HPP