matcher.hpp revision 0
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// Map Types to machine register types // Convert ideal machine register to a register mask for spill-loads // Convert machine register number to register mask // Mode bit to tell DFA and expand rules whether we are running after // (or during) register selection. Usually, the matcher runs before, // but it will also get called to generate post-allocation spill code. // In this situation, it is a deadly error to attempt to allocate more // Machine register names // Machine register encodings // Rules that are cheaper to rematerialize than to spill // An array of chars, from 0 to _last_Mach_Reg. // No Save = 'N' (for register windows) // Always Save = 'A' (same as SOE + SOC) // Convert a machine register to a machine register type, so-as to // properly match spill code. // Maps from machine register to boolean; true if machine register can // be holding a call argument in some signature. // Maps from machine register to boolean; true if machine register holds // List of IfFalse or IfTrue Nodes that indicate a taken null test. // List is valid in the post-matching space. // Select instructions for entire method // Transform, then walk. Does implicit DCE while walking. // Name changed from "transform" to avoid it being virtual. // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. // Initialize first stack mask and related masks. // If we should save-on-entry this register // Fixup the save-on-entry registers // --- Frame handling --- // Register number of the stack slot corresponding to the incoming SP. // Per the Big Picture in the AD file, it is: // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. // Register number of the stack slot corresponding to the highest incoming // argument on the stack. Per the Big Picture in the AD file, it is: // _old_SP + out_preserve_stack_slots + incoming argument size. // Register number of the stack slot corresponding to the new SP. // Per the Big Picture in the AD file, it is: // Register number of the stack slot corresponding to the highest outgoing // argument on the stack. Per the Big Picture in the AD file, it is: // _new_SP + max outgoing arguments of all calls // Does matcher support this ideal node? // Used to determine if we have fast l2f conversion // USII has it, USIII doesn't // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). // Depends on the details of 64-bit constant generation on the CPU. // These calls are all generated by the ADLC // TRUE - grows up, FALSE - grows down (Intel) // Java-Java calling convention // (what you use when Java calls Java) // Alignment of stack in bytes, standard Intel word alignment is 4. // Sparc probably wants at least double-word (8). // Alignment of stack, measured in stack slots. // The size of stack slots is defined by VMRegImpl::stack_slot_size. // Array mapping arguments to registers. Argument 0 is usually the 'this' // pointer. Registers can include stack-slots and regular registers. // Convert a sig into a calling convention register layout // and find interesting things about it. // Return address register. On Intel it is a stack-slot. On PowerPC // it is the Link register. On Sparc it is r31? // Return value register. On Intel it is EAX. On Sparc i0/o0. // Register for DIVI projection of divmodI // Register for MODI projection of divmodI // Register for DIVL projection of divmodL // Register for MODL projection of divmodL // Java-Interpreter calling convention // (what you use when calling between compiled-Java and Interpreted-Java // Number of callee-save + always-save registers // Ignores frame pointer and "special" registers // The Method-klass-holder may be passed in the inline_cache_reg // and then expanded into the inline_cache_reg and a method_oop register // Interpreter's Frame Pointer Register // Java-Native calling convention // (what you use when intercalling between Java and C++ code) // Array mapping arguments to registers. Argument 0 is usually the 'this' // pointer. Registers can include stack-slots and regular registers. // Frame pointer. The frame pointer is kept at the base of the stack // and so is probably the stack pointer for most machines. On Intel // it is ESP. On the PowerPC it is R1. On Sparc it is SP. // !!!!! Special stuff for building ScopeDescs // Is this branch offset small enough to be addressed by a short branch? // Anything this size or smaller may get converted to discrete scalar stores. // Should the Matcher clone shifts on addressing modes, expecting them to // be subsumed into complex addressing expressions or compute them into // registers? True for Intel but false for most RISCs // Is it better to copy float constants, or load them directly from memory? // Intel can load a float constant from a direct address, requiring no // extra registers. Most RISCs will have to materialize an address into a // register first, so they may as well materialize the constant immediately. // If CPU can load and store mis-aligned doubles directly then no fixup is // needed. Else we split the double into 2 integer pieces and move it // piece-by-piece. Only happens when passing doubles into C code or when // calling i2c adapters as the Java calling convention forces doubles to be // Perform a platform dependent implicit null fixup. This is needed // on windows95 to take care of some unusual register constraints. // Advertise here if the CPU requires explicit rounding operations // to implement the UseStrictFP mode. // Do floats take an entire double register or just half? // Do ints take an entire long register or just half? // This routine is run whenever a graph fails to match. // If it returns, the compiler should bailout to interpreter without error. // In non-product mode, SoftMatchFailure is false to detect non-canonical // graphs. Print a message and exit. else {
fatal(
"SoftMatchFailure is not allowed except in product"); }
// acting as an Acquire and thus we don't need an Acquire here. We // retain the Node to act as a compiler ordering barrier. // FastUnLock acting as a Release and thus we don't need a Release // here. We retain the Node to act as a compiler ordering barrier. // Check for a following volatile memory barrier without an // intervening load and thus we don't need a barrier here. We // retain the Node to act as a compiler ordering barrier.