3845N/A * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 0N/A * This code is free software; you can redistribute it and/or modify it 0N/A * under the terms of the GNU General Public License version 2 only, as 0N/A * published by the Free Software Foundation. 0N/A * This code is distributed in the hope that it will be useful, but WITHOUT 0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 0N/A * version 2 for more details (a copy is included in the LICENSE file that 0N/A * accompanied this code). 0N/A * You should have received a copy of the GNU General Public License version 0N/A * 2 along with this work; if not, write to the Free Software Foundation, 0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 0N/A//---------------------------Matcher------------------------------------------- 0N/A // Private arena of State objects 0N/A // Used to control the Label pass 0N/A // Private methods which perform the actual matching and reduction 0N/A // Walks the label tree, generating machine nodes 0N/A // If this node already matched using "rule", return the MachNode for it. 0N/A // Convert a dense opcode number to an expanded rule number 0N/A // Map dense opcode number to info on when rule is swallowed constant. 0N/A // Map dense rule number to determine if this is an instruction chain rule 0N/A // We want to clone constants and possible CmpI-variants. 0N/A // If we do not clone CmpI, then we can have many instances of 0N/A // condition codes alive at once. This is OK on some chips and 0N/A // bad on others. Hence the machine-dependent table lookup. 0N/A // Find shared Nodes, or Nodes that otherwise are Matcher roots 0N/A // Debug and profile information for nodes in old space: 0N/A // Node labeling iterator for instruction selection 0N/A // Accessors for the inherited field PhaseTransform::_nodes: 0N/A // Make sure only new nodes are reachable from this node 729N/A // Mach node for ConP #NULL 0N/A static const int base2reg[];
// Map Types to machine register types 0N/A // Convert ideal machine register to a register mask for spill-loads 0N/A // Convert machine register number to register mask 0N/A // Mode bit to tell DFA and expand rules whether we are running after 0N/A // (or during) register selection. Usually, the matcher runs before, 0N/A // but it will also get called to generate post-allocation spill code. 0N/A // In this situation, it is a deadly error to attempt to allocate more 0N/A // temporary registers. 0N/A // Machine register names 0N/A // Machine register encodings 0N/A // Machine Node names 0N/A // Rules that are cheaper to rematerialize than to spill 0N/A // An array of chars, from 0 to _last_Mach_Reg. 0N/A // No Save = 'N' (for register windows) 0N/A // Save on Entry = 'E' 0N/A // Save on Call = 'C' 0N/A // Always Save = 'A' (same as SOE + SOC) 0N/A // Convert a machine register to a machine register type, so-as to 0N/A // properly match spill code. 0N/A // Maps from machine register to boolean; true if machine register can 0N/A // be holding a call argument in some signature. 0N/A // Maps from machine register to boolean; true if machine register holds 0N/A // a spillable argument. 0N/A // List of IfFalse or IfTrue Nodes that indicate a taken null test. 0N/A // List is valid in the post-matching space. 0N/A // Select instructions for entire method 0N/A // Transform, then walk. Does implicit DCE while walking. 0N/A // Name changed from "transform" to avoid it being virtual. 0N/A // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 0N/A // Helper for match_sfpt 0N/A // Initialize first stack mask and related masks. 0N/A // If we should save-on-entry this register 0N/A // Fixup the save-on-entry registers 0N/A // --- Frame handling --- 0N/A // Register number of the stack slot corresponding to the incoming SP. 0N/A // Per the Big Picture in the AD file, it is: 0N/A // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 0N/A // Register number of the stack slot corresponding to the highest incoming 0N/A // argument on the stack. Per the Big Picture in the AD file, it is: 0N/A // _old_SP + out_preserve_stack_slots + incoming argument size. 0N/A // Register number of the stack slot corresponding to the new SP. 0N/A // Per the Big Picture in the AD file, it is: 0N/A // _in_arg_limit + pad0 0N/A // Register number of the stack slot corresponding to the highest outgoing 0N/A // argument on the stack. Per the Big Picture in the AD file, it is: 0N/A // _new_SP + max outgoing arguments of all calls 775N/A // Does matcher have a match rule for this ideal node? 775N/A // Does matcher have a match rule for this ideal node and is the 775N/A // predicate (if there is one) true? 775N/A // NOTE: If this function is used more commonly in the future, ADLC 775N/A // should generate this one. 0N/A // Used to determine if we have fast l2f conversion 0N/A // USII has it, USIII doesn't 0N/A // Vector width in bytes 3845N/A // Limits on vector size (number of elements). 0N/A // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) 0N/A // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). 0N/A // Depends on the details of 64-bit constant generation on the CPU. 0N/A // These calls are all generated by the ADLC 0N/A // TRUE - grows up, FALSE - grows down (Intel) 0N/A // Java-Java calling convention 0N/A // (what you use when Java calls Java) 0N/A // Alignment of stack in bytes, standard Intel word alignment is 4. 0N/A // Sparc probably wants at least double-word (8). 0N/A // Alignment of stack, measured in stack slots. 0N/A // The size of stack slots is defined by VMRegImpl::stack_slot_size. 0N/A // Array mapping arguments to registers. Argument 0 is usually the 'this' 0N/A // pointer. Registers can include stack-slots and regular registers. 0N/A // Convert a sig into a calling convention register layout 0N/A // and find interesting things about it. 0N/A // Return address register. On Intel it is a stack-slot. On PowerPC 0N/A // it is the Link register. On Sparc it is r31? 0N/A // Return value register. On Intel it is EAX. On Sparc i0/o0. 0N/A // Inline Cache Register 0N/A // Register for DIVI projection of divmodI 0N/A // Register for MODI projection of divmodI 0N/A // Register for DIVL projection of divmodL 0N/A // Register for MODL projection of divmodL 1834N/A // Use hardware DIV instruction when it is faster than 1834N/A // a code which use multiply for division by constant. 0N/A // Java-Interpreter calling convention 0N/A // (what you use when calling between compiled-Java and Interpreted-Java 0N/A // Number of callee-save + always-save registers 0N/A // Ignores frame pointer and "special" registers 0N/A // The Method-klass-holder may be passed in the inline_cache_reg 0N/A // and then expanded into the inline_cache_reg and a method_oop register 0N/A // Interpreter's Frame Pointer Register 0N/A // Java-Native calling convention 0N/A // (what you use when intercalling between Java and C++ code) 0N/A // Array mapping arguments to registers. Argument 0 is usually the 'this' 0N/A // pointer. Registers can include stack-slots and regular registers. 0N/A // Frame pointer. The frame pointer is kept at the base of the stack 0N/A // and so is probably the stack pointer for most machines. On Intel 0N/A // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 0N/A // !!!!! Special stuff for building ScopeDescs 0N/A // Is this branch offset small enough to be addressed by a short branch? 0N/A // Anything this size or smaller may get converted to discrete scalar stores. 2885N/A // Some hardware needs 2 CMOV's for longs. 2885N/A // Some hardware have expensive CMOV for float and double. 0N/A // Should the Matcher clone shifts on addressing modes, expecting them to 0N/A // be subsumed into complex addressing expressions or compute them into 0N/A // registers? True for Intel but false for most RISCs 1495N/A // Generate implicit null check for narrow oops if it can fold 1495N/A // into address expression (x64). 1495N/A // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression 1495N/A // NullCheck narrow_oop_reg 1495N/A // When narrow oops can't fold into address expression (Sparc) and 1495N/A // base is not null use decode_not_null and normal implicit null check. 1495N/A // Note, decode_not_null node can be used here since it is referenced 1495N/A // only on non null path but it requires special handling, see 1495N/A // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' 1495N/A // With Zero base and when narrow oops can not fold into address 1495N/A // expression use normal implicit null check since only shift 1495N/A // is needed to decode narrow oop. 1495N/A // decode narrow_oop_reg, oop_reg // only 'shift' 0N/A // Is it better to copy float constants, or load them directly from memory? 0N/A // Intel can load a float constant from a direct address, requiring no 0N/A // extra registers. Most RISCs will have to materialize an address into a 0N/A // register first, so they may as well materialize the constant immediately. 0N/A // If CPU can load and store mis-aligned doubles directly then no fixup is 0N/A // needed. Else we split the double into 2 integer pieces and move it 0N/A // piece-by-piece. Only happens when passing doubles into C code or when 0N/A // calling i2c adapters as the Java calling convention forces doubles to be 0N/A // Perform a platform dependent implicit null fixup. This is needed 0N/A // on windows95 to take care of some unusual register constraints. 0N/A // Advertise here if the CPU requires explicit rounding operations 0N/A // to implement the UseStrictFP mode. 1274N/A // Are floats conerted to double when stored to stack during deoptimization? 0N/A // Do ints take an entire long register or just half? 2248N/A // Do the processor's shift instructions only use the low 5/6 bits 2248N/A // of the count for 32/64 bit ints? If not we need to do the masking 0N/A // This routine is run whenever a graph fails to match. 0N/A // If it returns, the compiler should bailout to interpreter without error. 0N/A // In non-product mode, SoftMatchFailure is false to detect non-canonical 0N/A // graphs. Print a message and exit. 0N/A else {
fatal(
"SoftMatchFailure is not allowed except in product"); }
0N/A // Check for a following volatile memory barrier without an 0N/A // intervening load and thus we don't need a barrier here. We 0N/A // retain the Node to act as a compiler ordering barrier. 1879N/A#
endif // SHARE_VM_OPTO_MATCHER_HPP