0N/A/*
2273N/A * Copyright (c) 2002, 2011, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "compiler/oopMap.hpp"
1879N/A#include "opto/addnode.hpp"
1879N/A#include "opto/callnode.hpp"
1879N/A#include "opto/compile.hpp"
1879N/A#include "opto/machnode.hpp"
1879N/A#include "opto/matcher.hpp"
1879N/A#include "opto/phase.hpp"
1879N/A#include "opto/regalloc.hpp"
1879N/A#include "opto/rootnode.hpp"
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "vmreg_x86.inline.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "vmreg_sparc.inline.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_zero
1879N/A# include "vmreg_zero.inline.hpp"
1879N/A#endif
2073N/A#ifdef TARGET_ARCH_arm
2073N/A# include "vmreg_arm.inline.hpp"
2073N/A#endif
2073N/A#ifdef TARGET_ARCH_ppc
2073N/A# include "vmreg_ppc.inline.hpp"
2073N/A#endif
0N/A
0N/A// The functions in this file builds OopMaps after all scheduling is done.
0N/A//
0N/A// OopMaps contain a list of all registers and stack-slots containing oops (so
0N/A// they can be updated by GC). OopMaps also contain a list of derived-pointer
0N/A// base-pointer pairs. When the base is moved, the derived pointer moves to
0N/A// follow it. Finally, any registers holding callee-save values are also
0N/A// recorded. These might contain oops, but only the caller knows.
0N/A//
0N/A// BuildOopMaps implements a simple forward reaching-defs solution. At each
0N/A// GC point we'll have the reaching-def Nodes. If the reaching Nodes are
0N/A// typed as pointers (no offset), then they are oops. Pointers+offsets are
0N/A// derived pointers, and bases can be found from them. Finally, we'll also
0N/A// track reaching callee-save values. Note that a copy of a callee-save value
0N/A// "kills" it's source, so that only 1 copy of a callee-save value is alive at
0N/A// a time.
0N/A//
0N/A// We run a simple bitvector liveness pass to help trim out dead oops. Due to
0N/A// irreducible loops, we can have a reaching def of an oop that only reaches
0N/A// along one path and no way to know if it's valid or not on the other path.
0N/A// The bitvectors are quite dense and the liveness pass is fast.
0N/A//
0N/A// At GC points, we consult this information to build OopMaps. All reaching
0N/A// defs typed as oops are added to the OopMap. Only 1 instance of a
0N/A// callee-save register can be recorded. For derived pointers, we'll have to
0N/A// find and record the register holding the base.
0N/A//
0N/A// The reaching def's is a simple 1-pass worklist approach. I tried a clever
0N/A// breadth-first approach but it was worse (showed O(n^2) in the
0N/A// pick-next-block code).
0N/A//
605N/A// The relevant data is kept in a struct of arrays (it could just as well be
0N/A// an array of structs, but the struct-of-arrays is generally a little more
0N/A// efficient). The arrays are indexed by register number (including
0N/A// stack-slots as registers) and so is bounded by 200 to 300 elements in
0N/A// practice. One array will map to a reaching def Node (or NULL for
0N/A// conflict/dead). The other array will map to a callee-saved register or
0N/A// OptoReg::Bad for not-callee-saved.
0N/A
0N/A
0N/A//------------------------------OopFlow----------------------------------------
0N/A// Structure to pass around
0N/Astruct OopFlow : public ResourceObj {
0N/A short *_callees; // Array mapping register to callee-saved
0N/A Node **_defs; // array mapping register to reaching def
0N/A // or NULL if dead/conflict
0N/A // OopFlow structs, when not being actively modified, describe the _end_ of
0N/A // this block.
0N/A Block *_b; // Block for this struct
0N/A OopFlow *_next; // Next free OopFlow
833N/A // or NULL if dead/conflict
833N/A Compile* C;
0N/A
833N/A OopFlow( short *callees, Node **defs, Compile* c ) : _callees(callees), _defs(defs),
833N/A _b(NULL), _next(NULL), C(c) { }
0N/A
0N/A // Given reaching-defs for this block start, compute it for this block end
0N/A void compute_reach( PhaseRegAlloc *regalloc, int max_reg, Dict *safehash );
0N/A
0N/A // Merge these two OopFlows into the 'this' pointer.
0N/A void merge( OopFlow *flow, int max_reg );
0N/A
0N/A // Copy a 'flow' over an existing flow
0N/A void clone( OopFlow *flow, int max_size);
0N/A
0N/A // Make a new OopFlow from scratch
833N/A static OopFlow *make( Arena *A, int max_size, Compile* C );
0N/A
0N/A // Build an oopmap from the current flow info
0N/A OopMap *build_oop_map( Node *n, int max_reg, PhaseRegAlloc *regalloc, int* live );
0N/A};
0N/A
0N/A//------------------------------compute_reach----------------------------------
0N/A// Given reaching-defs for this block start, compute it for this block end
0N/Avoid OopFlow::compute_reach( PhaseRegAlloc *regalloc, int max_reg, Dict *safehash ) {
0N/A
0N/A for( uint i=0; i<_b->_nodes.size(); i++ ) {
0N/A Node *n = _b->_nodes[i];
0N/A
0N/A if( n->jvms() ) { // Build an OopMap here?
0N/A JVMState *jvms = n->jvms();
0N/A // no map needed for leaf calls
0N/A if( n->is_MachSafePoint() && !n->is_MachCallLeaf() ) {
0N/A int *live = (int*) (*safehash)[n];
0N/A assert( live, "must find live" );
0N/A n->as_MachSafePoint()->set_oop_map( build_oop_map(n,max_reg,regalloc, live) );
0N/A }
0N/A }
0N/A
0N/A // Assign new reaching def's.
0N/A // Note that I padded the _defs and _callees arrays so it's legal
0N/A // to index at _defs[OptoReg::Bad].
0N/A OptoReg::Name first = regalloc->get_reg_first(n);
0N/A OptoReg::Name second = regalloc->get_reg_second(n);
0N/A _defs[first] = n;
0N/A _defs[second] = n;
0N/A
0N/A // Pass callee-save info around copies
0N/A int idx = n->is_Copy();
0N/A if( idx ) { // Copies move callee-save info
0N/A OptoReg::Name old_first = regalloc->get_reg_first(n->in(idx));
0N/A OptoReg::Name old_second = regalloc->get_reg_second(n->in(idx));
0N/A int tmp_first = _callees[old_first];
0N/A int tmp_second = _callees[old_second];
0N/A _callees[old_first] = OptoReg::Bad; // callee-save is moved, dead in old location
0N/A _callees[old_second] = OptoReg::Bad;
0N/A _callees[first] = tmp_first;
0N/A _callees[second] = tmp_second;
0N/A } else if( n->is_Phi() ) { // Phis do not mod callee-saves
0N/A assert( _callees[first] == _callees[regalloc->get_reg_first(n->in(1))], "" );
0N/A assert( _callees[second] == _callees[regalloc->get_reg_second(n->in(1))], "" );
0N/A assert( _callees[first] == _callees[regalloc->get_reg_first(n->in(n->req()-1))], "" );
0N/A assert( _callees[second] == _callees[regalloc->get_reg_second(n->in(n->req()-1))], "" );
0N/A } else {
0N/A _callees[first] = OptoReg::Bad; // No longer holding a callee-save value
0N/A _callees[second] = OptoReg::Bad;
0N/A
0N/A // Find base case for callee saves
0N/A if( n->is_Proj() && n->in(0)->is_Start() ) {
0N/A if( OptoReg::is_reg(first) &&
0N/A regalloc->_matcher.is_save_on_entry(first) )
0N/A _callees[first] = first;
0N/A if( OptoReg::is_reg(second) &&
0N/A regalloc->_matcher.is_save_on_entry(second) )
0N/A _callees[second] = second;
0N/A }
0N/A }
0N/A }
0N/A}
0N/A
0N/A//------------------------------merge------------------------------------------
0N/A// Merge the given flow into the 'this' flow
0N/Avoid OopFlow::merge( OopFlow *flow, int max_reg ) {
0N/A assert( _b == NULL, "merging into a happy flow" );
0N/A assert( flow->_b, "this flow is still alive" );
0N/A assert( flow != this, "no self flow" );
0N/A
0N/A // Do the merge. If there are any differences, drop to 'bottom' which
0N/A // is OptoReg::Bad or NULL depending.
0N/A for( int i=0; i<max_reg; i++ ) {
0N/A // Merge the callee-save's
0N/A if( _callees[i] != flow->_callees[i] )
0N/A _callees[i] = OptoReg::Bad;
0N/A // Merge the reaching defs
0N/A if( _defs[i] != flow->_defs[i] )
0N/A _defs[i] = NULL;
0N/A }
0N/A
0N/A}
0N/A
0N/A//------------------------------clone------------------------------------------
0N/Avoid OopFlow::clone( OopFlow *flow, int max_size ) {
0N/A _b = flow->_b;
0N/A memcpy( _callees, flow->_callees, sizeof(short)*max_size);
0N/A memcpy( _defs , flow->_defs , sizeof(Node*)*max_size);
0N/A}
0N/A
0N/A//------------------------------make-------------------------------------------
833N/AOopFlow *OopFlow::make( Arena *A, int max_size, Compile* C ) {
0N/A short *callees = NEW_ARENA_ARRAY(A,short,max_size+1);
0N/A Node **defs = NEW_ARENA_ARRAY(A,Node*,max_size+1);
0N/A debug_only( memset(defs,0,(max_size+1)*sizeof(Node*)) );
833N/A OopFlow *flow = new (A) OopFlow(callees+1, defs+1, C);
0N/A assert( &flow->_callees[OptoReg::Bad] == callees, "Ok to index at OptoReg::Bad" );
0N/A assert( &flow->_defs [OptoReg::Bad] == defs , "Ok to index at OptoReg::Bad" );
0N/A return flow;
0N/A}
0N/A
0N/A//------------------------------bit twiddlers----------------------------------
0N/Astatic int get_live_bit( int *live, int reg ) {
0N/A return live[reg>>LogBitsPerInt] & (1<<(reg&(BitsPerInt-1))); }
0N/Astatic void set_live_bit( int *live, int reg ) {
0N/A live[reg>>LogBitsPerInt] |= (1<<(reg&(BitsPerInt-1))); }
0N/Astatic void clr_live_bit( int *live, int reg ) {
0N/A live[reg>>LogBitsPerInt] &= ~(1<<(reg&(BitsPerInt-1))); }
0N/A
0N/A//------------------------------build_oop_map----------------------------------
0N/A// Build an oopmap from the current flow info
0N/AOopMap *OopFlow::build_oop_map( Node *n, int max_reg, PhaseRegAlloc *regalloc, int* live ) {
0N/A int framesize = regalloc->_framesize;
0N/A int max_inarg_slot = OptoReg::reg2stack(regalloc->_matcher._new_SP);
0N/A debug_only( char *dup_check = NEW_RESOURCE_ARRAY(char,OptoReg::stack0());
0N/A memset(dup_check,0,OptoReg::stack0()) );
0N/A
0N/A OopMap *omap = new OopMap( framesize, max_inarg_slot );
0N/A MachCallNode *mcall = n->is_MachCall() ? n->as_MachCall() : NULL;
0N/A JVMState* jvms = n->jvms();
0N/A
0N/A // For all registers do...
0N/A for( int reg=0; reg<max_reg; reg++ ) {
0N/A if( get_live_bit(live,reg) == 0 )
0N/A continue; // Ignore if not live
0N/A
0N/A // %%% C2 can use 2 OptoRegs when the physical register is only one 64bit
0N/A // register in that case we'll get an non-concrete register for the second
0N/A // half. We only need to tell the map the register once!
0N/A //
0N/A // However for the moment we disable this change and leave things as they
0N/A // were.
0N/A
0N/A VMReg r = OptoReg::as_VMReg(OptoReg::Name(reg), framesize, max_inarg_slot);
0N/A
0N/A if (false && r->is_reg() && !r->is_concrete()) {
0N/A continue;
0N/A }
0N/A
0N/A // See if dead (no reaching def).
0N/A Node *def = _defs[reg]; // Get reaching def
0N/A assert( def, "since live better have reaching def" );
0N/A
0N/A // Classify the reaching def as oop, derived, callee-save, dead, or other
0N/A const Type *t = def->bottom_type();
0N/A if( t->isa_oop_ptr() ) { // Oop or derived?
0N/A assert( !OptoReg::is_valid(_callees[reg]), "oop can't be callee save" );
0N/A#ifdef _LP64
0N/A // 64-bit pointers record oop-ishness on 2 aligned adjacent registers.
0N/A // Make sure both are record from the same reaching def, but do not
0N/A // put both into the oopmap.
0N/A if( (reg&1) == 1 ) { // High half of oop-pair?
0N/A assert( _defs[reg-1] == _defs[reg], "both halves from same reaching def" );
0N/A continue; // Do not record high parts in oopmap
0N/A }
0N/A#endif
0N/A
0N/A // Check for a legal reg name in the oopMap and bailout if it is not.
0N/A if (!omap->legal_vm_reg_name(r)) {
0N/A regalloc->C->record_method_not_compilable("illegal oopMap register name");
0N/A continue;
0N/A }
0N/A if( t->is_ptr()->_offset == 0 ) { // Not derived?
0N/A if( mcall ) {
0N/A // Outgoing argument GC mask responsibility belongs to the callee,
0N/A // not the caller. Inspect the inputs to the call, to see if
0N/A // this live-range is one of them.
0N/A uint cnt = mcall->tf()->domain()->cnt();
0N/A uint j;
0N/A for( j = TypeFunc::Parms; j < cnt; j++)
0N/A if( mcall->in(j) == def )
0N/A break; // reaching def is an argument oop
0N/A if( j < cnt ) // arg oops dont go in GC map
0N/A continue; // Continue on to the next register
0N/A }
0N/A omap->set_oop(r);
0N/A } else { // Else it's derived.
0N/A // Find the base of the derived value.
0N/A uint i;
0N/A // Fast, common case, scan
0N/A for( i = jvms->oopoff(); i < n->req(); i+=2 )
0N/A if( n->in(i) == def ) break; // Common case
0N/A if( i == n->req() ) { // Missed, try a more generous scan
0N/A // Scan again, but this time peek through copies
0N/A for( i = jvms->oopoff(); i < n->req(); i+=2 ) {
0N/A Node *m = n->in(i); // Get initial derived value
0N/A while( 1 ) {
0N/A Node *d = def; // Get initial reaching def
0N/A while( 1 ) { // Follow copies of reaching def to end
0N/A if( m == d ) goto found; // breaks 3 loops
0N/A int idx = d->is_Copy();
0N/A if( !idx ) break;
0N/A d = d->in(idx); // Link through copy
0N/A }
0N/A int idx = m->is_Copy();
0N/A if( !idx ) break;
0N/A m = m->in(idx);
0N/A }
0N/A }
833N/A guarantee( 0, "must find derived/base pair" );
0N/A }
0N/A found: ;
0N/A Node *base = n->in(i+1); // Base is other half of pair
0N/A int breg = regalloc->get_reg_first(base);
0N/A VMReg b = OptoReg::as_VMReg(OptoReg::Name(breg), framesize, max_inarg_slot);
0N/A
0N/A // I record liveness at safepoints BEFORE I make the inputs
0N/A // live. This is because argument oops are NOT live at a
0N/A // safepoint (or at least they cannot appear in the oopmap).
0N/A // Thus bases of base/derived pairs might not be in the
0N/A // liveness data but they need to appear in the oopmap.
0N/A if( get_live_bit(live,breg) == 0 ) {// Not live?
0N/A // Flag it, so next derived pointer won't re-insert into oopmap
0N/A set_live_bit(live,breg);
0N/A // Already missed our turn?
0N/A if( breg < reg ) {
0N/A if (b->is_stack() || b->is_concrete() || true ) {
0N/A omap->set_oop( b);
0N/A }
0N/A }
0N/A }
0N/A if (b->is_stack() || b->is_concrete() || true ) {
0N/A omap->set_derived_oop( r, b);
0N/A }
0N/A }
0N/A
113N/A } else if( t->isa_narrowoop() ) {
113N/A assert( !OptoReg::is_valid(_callees[reg]), "oop can't be callee save" );
113N/A // Check for a legal reg name in the oopMap and bailout if it is not.
113N/A if (!omap->legal_vm_reg_name(r)) {
113N/A regalloc->C->record_method_not_compilable("illegal oopMap register name");
113N/A continue;
113N/A }
113N/A if( mcall ) {
113N/A // Outgoing argument GC mask responsibility belongs to the callee,
113N/A // not the caller. Inspect the inputs to the call, to see if
113N/A // this live-range is one of them.
113N/A uint cnt = mcall->tf()->domain()->cnt();
113N/A uint j;
113N/A for( j = TypeFunc::Parms; j < cnt; j++)
113N/A if( mcall->in(j) == def )
113N/A break; // reaching def is an argument oop
113N/A if( j < cnt ) // arg oops dont go in GC map
113N/A continue; // Continue on to the next register
113N/A }
113N/A omap->set_narrowoop(r);
0N/A } else if( OptoReg::is_valid(_callees[reg])) { // callee-save?
0N/A // It's a callee-save value
0N/A assert( dup_check[_callees[reg]]==0, "trying to callee save same reg twice" );
0N/A debug_only( dup_check[_callees[reg]]=1; )
0N/A VMReg callee = OptoReg::as_VMReg(OptoReg::Name(_callees[reg]));
0N/A if ( callee->is_concrete() || true ) {
0N/A omap->set_callee_saved( r, callee);
0N/A }
0N/A
0N/A } else {
0N/A // Other - some reaching non-oop value
0N/A omap->set_value( r);
833N/A#ifdef ASSERT
833N/A if( t->isa_rawptr() && C->cfg()->_raw_oops.member(def) ) {
833N/A def->dump();
833N/A n->dump();
833N/A assert(false, "there should be a oop in OopMap instead of a live raw oop at safepoint");
833N/A }
833N/A#endif
0N/A }
0N/A
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A /* Nice, Intel-only assert
0N/A int cnt_callee_saves=0;
0N/A int reg2 = 0;
0N/A while (OptoReg::is_reg(reg2)) {
0N/A if( dup_check[reg2] != 0) cnt_callee_saves++;
0N/A assert( cnt_callee_saves==3 || cnt_callee_saves==5, "missed some callee-save" );
0N/A reg2++;
0N/A }
0N/A */
0N/A#endif
0N/A
729N/A#ifdef ASSERT
729N/A for( OopMapStream oms1(omap, OopMapValue::derived_oop_value); !oms1.is_done(); oms1.next()) {
729N/A OopMapValue omv1 = oms1.current();
729N/A bool found = false;
729N/A for( OopMapStream oms2(omap,OopMapValue::oop_value); !oms2.is_done(); oms2.next()) {
729N/A if( omv1.content_reg() == oms2.current().reg() ) {
729N/A found = true;
729N/A break;
729N/A }
729N/A }
729N/A assert( found, "derived with no base in oopmap" );
729N/A }
729N/A#endif
729N/A
0N/A return omap;
0N/A}
0N/A
0N/A//------------------------------do_liveness------------------------------------
0N/A// Compute backwards liveness on registers
0N/Astatic void do_liveness( PhaseRegAlloc *regalloc, PhaseCFG *cfg, Block_List *worklist, int max_reg_ints, Arena *A, Dict *safehash ) {
0N/A int *live = NEW_ARENA_ARRAY(A, int, (cfg->_num_blocks+1) * max_reg_ints);
0N/A int *tmp_live = &live[cfg->_num_blocks * max_reg_ints];
0N/A Node *root = cfg->C->root();
0N/A // On CISC platforms, get the node representing the stack pointer that regalloc
0N/A // used for spills
0N/A Node *fp = NodeSentinel;
0N/A if (UseCISCSpill && root->req() > 1) {
0N/A fp = root->in(1)->in(TypeFunc::FramePtr);
0N/A }
0N/A memset( live, 0, cfg->_num_blocks * (max_reg_ints<<LogBytesPerInt) );
0N/A // Push preds onto worklist
0N/A for( uint i=1; i<root->req(); i++ )
0N/A worklist->push(cfg->_bbs[root->in(i)->_idx]);
0N/A
0N/A // ZKM.jar includes tiny infinite loops which are unreached from below.
0N/A // If we missed any blocks, we'll retry here after pushing all missed
0N/A // blocks on the worklist. Normally this outer loop never trips more
0N/A // than once.
0N/A while( 1 ) {
0N/A
0N/A while( worklist->size() ) { // Standard worklist algorithm
0N/A Block *b = worklist->rpop();
0N/A
0N/A // Copy first successor into my tmp_live space
0N/A int s0num = b->_succs[0]->_pre_order;
0N/A int *t = &live[s0num*max_reg_ints];
0N/A for( int i=0; i<max_reg_ints; i++ )
0N/A tmp_live[i] = t[i];
0N/A
0N/A // OR in the remaining live registers
0N/A for( uint j=1; j<b->_num_succs; j++ ) {
0N/A uint sjnum = b->_succs[j]->_pre_order;
0N/A int *t = &live[sjnum*max_reg_ints];
0N/A for( int i=0; i<max_reg_ints; i++ )
0N/A tmp_live[i] |= t[i];
0N/A }
0N/A
0N/A // Now walk tmp_live up the block backwards, computing live
0N/A for( int k=b->_nodes.size()-1; k>=0; k-- ) {
0N/A Node *n = b->_nodes[k];
0N/A // KILL def'd bits
0N/A int first = regalloc->get_reg_first(n);
0N/A int second = regalloc->get_reg_second(n);
0N/A if( OptoReg::is_valid(first) ) clr_live_bit(tmp_live,first);
0N/A if( OptoReg::is_valid(second) ) clr_live_bit(tmp_live,second);
0N/A
0N/A MachNode *m = n->is_Mach() ? n->as_Mach() : NULL;
0N/A
0N/A // Check if m is potentially a CISC alternate instruction (i.e, possibly
0N/A // synthesized by RegAlloc from a conventional instruction and a
0N/A // spilled input)
0N/A bool is_cisc_alternate = false;
0N/A if (UseCISCSpill && m) {
0N/A is_cisc_alternate = m->is_cisc_alternate();
0N/A }
0N/A
0N/A // GEN use'd bits
0N/A for( uint l=1; l<n->req(); l++ ) {
0N/A Node *def = n->in(l);
0N/A assert(def != 0, "input edge required");
0N/A int first = regalloc->get_reg_first(def);
0N/A int second = regalloc->get_reg_second(def);
0N/A if( OptoReg::is_valid(first) ) set_live_bit(tmp_live,first);
0N/A if( OptoReg::is_valid(second) ) set_live_bit(tmp_live,second);
0N/A // If we use the stack pointer in a cisc-alternative instruction,
0N/A // check for use as a memory operand. Then reconstruct the RegName
0N/A // for this stack location, and set the appropriate bit in the
0N/A // live vector 4987749.
0N/A if (is_cisc_alternate && def == fp) {
0N/A const TypePtr *adr_type = NULL;
0N/A intptr_t offset;
0N/A const Node* base = m->get_base_and_disp(offset, adr_type);
0N/A if (base == NodeSentinel) {
0N/A // Machnode has multiple memory inputs. We are unable to reason
0N/A // with these, but are presuming (with trepidation) that not any of
0N/A // them are oops. This can be fixed by making get_base_and_disp()
0N/A // look at a specific input instead of all inputs.
0N/A assert(!def->bottom_type()->isa_oop_ptr(), "expecting non-oop mem input");
0N/A } else if (base != fp || offset == Type::OffsetBot) {
0N/A // Do nothing: the fp operand is either not from a memory use
0N/A // (base == NULL) OR the fp is used in a non-memory context
0N/A // (base is some other register) OR the offset is not constant,
0N/A // so it is not a stack slot.
0N/A } else {
0N/A assert(offset >= 0, "unexpected negative offset");
0N/A offset -= (offset % jintSize); // count the whole word
0N/A int stack_reg = regalloc->offset2reg(offset);
0N/A if (OptoReg::is_stack(stack_reg)) {
0N/A set_live_bit(tmp_live, stack_reg);
0N/A } else {
0N/A assert(false, "stack_reg not on stack?");
0N/A }
0N/A }
0N/A }
0N/A }
0N/A
0N/A if( n->jvms() ) { // Record liveness at safepoint
0N/A
0N/A // This placement of this stanza means inputs to calls are
0N/A // considered live at the callsite's OopMap. Argument oops are
0N/A // hence live, but NOT included in the oopmap. See cutout in
0N/A // build_oop_map. Debug oops are live (and in OopMap).
0N/A int *n_live = NEW_ARENA_ARRAY(A, int, max_reg_ints);
0N/A for( int l=0; l<max_reg_ints; l++ )
0N/A n_live[l] = tmp_live[l];
0N/A safehash->Insert(n,n_live);
0N/A }
0N/A
0N/A }
0N/A
0N/A // Now at block top, see if we have any changes. If so, propagate
0N/A // to prior blocks.
0N/A int *old_live = &live[b->_pre_order*max_reg_ints];
0N/A int l;
0N/A for( l=0; l<max_reg_ints; l++ )
0N/A if( tmp_live[l] != old_live[l] )
0N/A break;
0N/A if( l<max_reg_ints ) { // Change!
0N/A // Copy in new value
0N/A for( l=0; l<max_reg_ints; l++ )
0N/A old_live[l] = tmp_live[l];
0N/A // Push preds onto worklist
0N/A for( l=1; l<(int)b->num_preds(); l++ )
0N/A worklist->push(cfg->_bbs[b->pred(l)->_idx]);
0N/A }
0N/A }
0N/A
0N/A // Scan for any missing safepoints. Happens to infinite loops
0N/A // ala ZKM.jar
0N/A uint i;
0N/A for( i=1; i<cfg->_num_blocks; i++ ) {
0N/A Block *b = cfg->_blocks[i];
0N/A uint j;
0N/A for( j=1; j<b->_nodes.size(); j++ )
0N/A if( b->_nodes[j]->jvms() &&
0N/A (*safehash)[b->_nodes[j]] == NULL )
0N/A break;
0N/A if( j<b->_nodes.size() ) break;
0N/A }
0N/A if( i == cfg->_num_blocks )
0N/A break; // Got 'em all
0N/A#ifndef PRODUCT
0N/A if( PrintOpto && Verbose )
0N/A tty->print_cr("retripping live calc");
0N/A#endif
0N/A // Force the issue (expensively): recheck everybody
0N/A for( i=1; i<cfg->_num_blocks; i++ )
0N/A worklist->push(cfg->_blocks[i]);
0N/A }
0N/A
0N/A}
0N/A
0N/A//------------------------------BuildOopMaps-----------------------------------
0N/A// Collect GC mask info - where are all the OOPs?
0N/Avoid Compile::BuildOopMaps() {
0N/A NOT_PRODUCT( TracePhase t3("bldOopMaps", &_t_buildOopMaps, TimeCompiler); )
0N/A // Can't resource-mark because I need to leave all those OopMaps around,
0N/A // or else I need to resource-mark some arena other than the default.
0N/A // ResourceMark rm; // Reclaim all OopFlows when done
0N/A int max_reg = _regalloc->_max_reg; // Current array extent
0N/A
0N/A Arena *A = Thread::current()->resource_area();
0N/A Block_List worklist; // Worklist of pending blocks
0N/A
0N/A int max_reg_ints = round_to(max_reg, BitsPerInt)>>LogBitsPerInt;
0N/A Dict *safehash = NULL; // Used for assert only
0N/A // Compute a backwards liveness per register. Needs a bitarray of
0N/A // #blocks x (#registers, rounded up to ints)
0N/A safehash = new Dict(cmpkey,hashkey,A);
0N/A do_liveness( _regalloc, _cfg, &worklist, max_reg_ints, A, safehash );
0N/A OopFlow *free_list = NULL; // Free, unused
0N/A
0N/A // Array mapping blocks to completed oopflows
0N/A OopFlow **flows = NEW_ARENA_ARRAY(A, OopFlow*, _cfg->_num_blocks);
0N/A memset( flows, 0, _cfg->_num_blocks*sizeof(OopFlow*) );
0N/A
0N/A
0N/A // Do the first block 'by hand' to prime the worklist
0N/A Block *entry = _cfg->_blocks[1];
833N/A OopFlow *rootflow = OopFlow::make(A,max_reg,this);
0N/A // Initialize to 'bottom' (not 'top')
0N/A memset( rootflow->_callees, OptoReg::Bad, max_reg*sizeof(short) );
0N/A memset( rootflow->_defs , 0, max_reg*sizeof(Node*) );
0N/A flows[entry->_pre_order] = rootflow;
0N/A
0N/A // Do the first block 'by hand' to prime the worklist
0N/A rootflow->_b = entry;
0N/A rootflow->compute_reach( _regalloc, max_reg, safehash );
0N/A for( uint i=0; i<entry->_num_succs; i++ )
0N/A worklist.push(entry->_succs[i]);
0N/A
0N/A // Now worklist contains blocks which have some, but perhaps not all,
0N/A // predecessors visited.
0N/A while( worklist.size() ) {
0N/A // Scan for a block with all predecessors visited, or any randoms slob
0N/A // otherwise. All-preds-visited order allows me to recycle OopFlow
0N/A // structures rapidly and cut down on the memory footprint.
0N/A // Note: not all predecessors might be visited yet (must happen for
0N/A // irreducible loops). This is OK, since every live value must have the
0N/A // SAME reaching def for the block, so any reaching def is OK.
0N/A uint i;
0N/A
0N/A Block *b = worklist.pop();
0N/A // Ignore root block
0N/A if( b == _cfg->_broot ) continue;
0N/A // Block is already done? Happens if block has several predecessors,
0N/A // he can get on the worklist more than once.
0N/A if( flows[b->_pre_order] ) continue;
0N/A
0N/A // If this block has a visited predecessor AND that predecessor has this
0N/A // last block as his only undone child, we can move the OopFlow from the
0N/A // pred to this block. Otherwise we have to grab a new OopFlow.
0N/A OopFlow *flow = NULL; // Flag for finding optimized flow
0N/A Block *pred = (Block*)0xdeadbeef;
0N/A uint j;
0N/A // Scan this block's preds to find a done predecessor
0N/A for( j=1; j<b->num_preds(); j++ ) {
0N/A Block *p = _cfg->_bbs[b->pred(j)->_idx];
0N/A OopFlow *p_flow = flows[p->_pre_order];
0N/A if( p_flow ) { // Predecessor is done
0N/A assert( p_flow->_b == p, "cross check" );
0N/A pred = p; // Record some predecessor
0N/A // If all successors of p are done except for 'b', then we can carry
0N/A // p_flow forward to 'b' without copying, otherwise we have to draw
0N/A // from the free_list and clone data.
0N/A uint k;
0N/A for( k=0; k<p->_num_succs; k++ )
0N/A if( !flows[p->_succs[k]->_pre_order] &&
0N/A p->_succs[k] != b )
0N/A break;
0N/A
0N/A // Either carry-forward the now-unused OopFlow for b's use
0N/A // or draw a new one from the free list
0N/A if( k==p->_num_succs ) {
0N/A flow = p_flow;
0N/A break; // Found an ideal pred, use him
0N/A }
0N/A }
0N/A }
0N/A
0N/A if( flow ) {
0N/A // We have an OopFlow that's the last-use of a predecessor.
0N/A // Carry it forward.
0N/A } else { // Draw a new OopFlow from the freelist
0N/A if( !free_list )
833N/A free_list = OopFlow::make(A,max_reg,C);
0N/A flow = free_list;
0N/A assert( flow->_b == NULL, "oopFlow is not free" );
0N/A free_list = flow->_next;
0N/A flow->_next = NULL;
0N/A
0N/A // Copy/clone over the data
0N/A flow->clone(flows[pred->_pre_order], max_reg);
0N/A }
0N/A
0N/A // Mark flow for block. Blocks can only be flowed over once,
0N/A // because after the first time they are guarded from entering
0N/A // this code again.
0N/A assert( flow->_b == pred, "have some prior flow" );
0N/A flow->_b = NULL;
0N/A
0N/A // Now push flow forward
0N/A flows[b->_pre_order] = flow;// Mark flow for this block
0N/A flow->_b = b;
0N/A flow->compute_reach( _regalloc, max_reg, safehash );
0N/A
0N/A // Now push children onto worklist
0N/A for( i=0; i<b->_num_succs; i++ )
0N/A worklist.push(b->_succs[i]);
0N/A
0N/A }
0N/A}