1472N/A * or visit www.oracle.com if you need additional information or have any
1879N/A#include "c1/c1_FpuStackSim.hpp"
1879N/A#include "c1/c1_FrameMap.hpp"
1879N/A#include "c1/c1_Instruction.hpp"
1879N/A#include "c1/c1_LIR.hpp"
1879N/A#include "c1/c1_LIRGenerator.hpp"
0N/Aclass DebugInfoCache;
0N/Aclass FpuStackAllocator;
0N/Aclass IRScopeDebugInfo;
0N/Aclass IntervalWalker;
0N/Aclass LIRGenerator;
0N/Aclass LinearScan;
0N/Aclass MoveResolver;
0N/A // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form)
0N/A storeAtDefinition, // the interval should be stored immediately after its definition because otherwise
0N/A startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary
0N/A noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized
0N/A for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1))
0N/A friend class IntervalWalker;
0N/A friend class LinearScanWalker;
0N/A friend class FpuStackAllocator;
0N/A friend class MoveResolver;
0N/A friend class LinearScanStatistic;
0N/A friend class LinearScanTimers;
0N/A friend class RegisterVerifier;
0N/A BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged)
0N/A int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals)
0N/A bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary)
0N/A int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value
0N/A IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split
1969N/A bool _needs_full_resort; // set to true if an Interval::from() is changed and _sorted_intervals must be resorted
0N/A BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction
0N/A BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop
0N/A int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); }
0N/A BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); }
0N/A bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); }
0N/A // handling of fpu stack allocation (platform dependent, needed for debug information generation)
0N/A int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; }
0N/A LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); }
0N/A BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); }
0N/A bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); }
0N/A bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); }
0N/A bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); }
0N/A bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); }
0N/A void propagate_spill_slots();
0N/A void eliminate_spill_moves();
0N/A void number_instructions();
0N/A void compute_local_live_sets();
0N/A void compute_global_live_sets();
0N/A void build_intervals();
0N/A void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i));
0N/A void sort_intervals_before_allocation();
0N/A void sort_intervals_after_allocation();
0N/A void allocate_registers();
0N/A void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver);
0N/A void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver);
0N/A void resolve_data_flow();
0N/A void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver);
0N/A void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver);
0N/A void resolve_exception_handlers();
0N/A OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site);
0N/A void init_compute_debug_info();
1739N/A IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state);
0N/A void assign_reg_num();
0N/A void allocate_fpu_stack();
0N/A void verify_intervals();
0N/A void verify_constants();
0N/A void verify_registers();
0N/A void do_linear_scan();
0N/A static void print_statistics();
0N/A int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; }
0N/A void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; }
0N/A void append_insertion_buffer();
0N/A void resolve_mappings();
0N/A void resolve_and_append_moves();
0N/A IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents)
0N/A Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents)
0N/A int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents)
0N/A bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time
0N/A BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; }
0N/A void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; }
0N/A int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; }
0N/A Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; }
0N/A void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; }
0N/A void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; }
0N/A void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; }
0N/A bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; }
0N/A int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register
0N/A int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position
0N/A void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); }
0N/A Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position
0N/A Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position
0N/A void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); }
0N/A Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; }
0N/A Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; }
0N/A Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; }
0N/A void next_interval();
0N/A // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()).
0N/A virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to);
0N/A IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first);
0N/A Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; }
0N/A Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; }
0N/A BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); }
0N/A void free_exclude_active_fixed();
0N/A void free_exclude_active_any();
0N/A void spill_exclude_active_fixed();
0N/A void spill_collect_active_any();
0N/A int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization);
0N/A int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split);
0N/A int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split);
0N/A int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split);
0N/A int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split);
0N/A bool activate_current();
0N/A LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first);
0N/A void init_instructions();
0N/A void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to);
0N/A void end_method(LinearScan* allocator); // called for each method when register allocation completed
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "c1_LinearScan_x86.hpp"
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "c1_LinearScan_sparc.hpp"
2073N/A#ifdef TARGET_ARCH_arm
2073N/A# include "c1_LinearScan_arm.hpp"
2073N/A#ifdef TARGET_ARCH_ppc
2073N/A# include "c1_LinearScan_ppc.hpp"