c1_Defs.hpp revision 2073
0N/A/*
1879N/A * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#ifndef SHARE_VM_C1_C1_DEFS_HPP
1879N/A#define SHARE_VM_C1_C1_DEFS_HPP
1879N/A
1879N/A#include "utilities/globalDefinitions.hpp"
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "register_x86.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "register_sparc.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_zero
1879N/A# include "register_zero.hpp"
1879N/A#endif
2073N/A#ifdef TARGET_ARCH_arm
2073N/A# include "register_arm.hpp"
2073N/A#endif
2073N/A#ifdef TARGET_ARCH_ppc
2073N/A# include "register_ppc.hpp"
2073N/A#endif
1879N/A
0N/A// set frame size and return address offset to these values in blobs
0N/A// (if the compiled frame uses ebp as link pointer on IA; otherwise,
0N/A// the frame size must be fixed)
0N/Aenum {
0N/A no_frame_size = -1
0N/A};
0N/A
0N/A
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "c1_Defs_x86.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "c1_Defs_sparc.hpp"
1879N/A#endif
2073N/A#ifdef TARGET_ARCH_arm
2073N/A# include "c1_Defs_arm.hpp"
2073N/A#endif
2073N/A#ifdef TARGET_ARCH_ppc
2073N/A# include "c1_Defs_ppc.hpp"
2073N/A#endif
1879N/A
0N/A
0N/A// native word offsets from memory address
0N/Aenum {
0N/A lo_word_offset_in_bytes = pd_lo_word_offset_in_bytes,
0N/A hi_word_offset_in_bytes = pd_hi_word_offset_in_bytes
0N/A};
0N/A
0N/A
0N/A// the processor may require explicit rounding operations to implement the strictFP mode
0N/Aenum {
0N/A strict_fp_requires_explicit_rounding = pd_strict_fp_requires_explicit_rounding
0N/A};
0N/A
0N/A
0N/A// for debug info: a float value in a register may be saved in double precision by runtime stubs
0N/Aenum {
0N/A float_saved_as_double = pd_float_saved_as_double
0N/A};
1879N/A
1879N/A#endif // SHARE_VM_C1_C1_DEFS_HPP