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0N/AJavaSoft HotSpot Architecture Description Language Syntax Specification
0N/AVersion 0.4 - September 19, 1997
0N/AThis document specifies the syntax and associated semantics for the JavaSoft
0N/AHotSpot Architecture Description Language. This language is used to describe
0N/Athe architecture of a processor, and is the input to the ADL Compiler. The
0N/AADL Compiler compiles an ADL file into code which is incorporated into the
0N/AOptimizing Just In Time Compiler (OJIT) to generate efficient and correct code
0N/Afor the target architecture. The ADL describes three bassic different types
0N/Aof architectural features. It describes the instruction set (and associated
0N/Aoperands) of the target architecture. It describes the register set of the
0N/Atarget architecture along with relevant information for the register allocator.
0N/AFinally, it describes the architecture's pipeline for scheduling purposes.
0N/AThe ADL is used to create an architecture description file for a target
0N/Aarchitecture. The architecture description file along with some additional
0N/Atarget specific oracles, written in C++, represent the principal effort in
0N/Aporting the OJIT to a new target architecture.
0N/A// Create a cost attribute for all operands, and specify the default value
0N/Aop_attrib op_cost(10);
0N/A// Create a cost attribute for all instruction, and specify a default value
0N/Ains_attrib ins_cost(100);
0N/A// example operand form
0N/Aoperand x_reg(REG_NUM rnum)
0N/A constraint(IS_RCLASS(rnum, RC_X_REG));
0N/A match(VREG) %{ rnum = new_VR(); %} // block after rule is constructor
0N/A encode %{ return rnum; %} // encode rules are required
0N/A // this operand has no op_cost entry because it uses the default value
0N/A// example instruction form
0N/Ainstruct add_accum_reg(x_reg dst, reg src)
0N/A match(SET dst (PLUS dst src)); // no block = use default constructor
0N/A encode // rule is body of a C++ function
0N/A return pentium_encode_add_accum_reg(rnum);
0N/A ins_cost(200); // this instruction is more costly than the default
0N/A 2. Register Set Description Syntax for Allocation
0N/Areg_def AX(SOE, 1); // declare register AX, mark it save on entry with index 0
0N/Areg_def BX(SOC); // declare register BX, and mark it save on call
0N/Areg_class X_REG(AX, BX); // form a matcher register class of X_REG
0N/A // these are used for constraints, etc.
0N/Aalloc_class class1(AX, BX); // form an allocation class of registers
605N/A // used by the register allocator for separate
0N/A // allocation of target register classes
0N/A 3. Pipeline Syntax for Scheduling
0N/A a. instruct - indicates a machine instruction entry
0N/A b. operand - indicates a machine operand entry
0N/A c. opclass - indicates a class of machine operands
0N/A d. source - indicates a block of C++ source code
0N/A e. op_attrib - indicates an optional attribute for all operands
0N/A f. ins_attrib - indicates an optional attribute for all instructions
0N/A *j. constraint - indicates a constraint on the value of an operand
0N/A *k. effect - describes the dataflow effect of an operand which
0N/A is not part of a match rule
0N/A *l. expand - indicates a single instruction for matching which
0N/A expands to multiple instructions for output
0N/A *m. rewrite - indicates a single instruction for matching which
0N/A gets rewritten to one or more instructions after
0N/A allocation depending upon the registers allocated
0N/A o. construct - indicates a default constructor for an operand
0N/A [NOTE: * indicates a feature which will not be in first release ]
0N/A *a. register - indicates an architecture register definition section
0N/A *b. reg_def - indicates a register declaration
0N/A *b. reg_class - indicates a class (list) of registers for matching
0N/A *c. alloc_class - indicates a class (list) of registers for allocation
0N/A *a. pipeline - indicates an architecture pipeline definition section
0N/A *b. resource - indicates a pipeline resource used by instructions
0N/A *c. pipe_desc - indicates the relevant stages of the pipeline
0N/A *d. pipe_class - indicates a description of the pipeline behavior
0N/A for a group of instructions
0N/A *e. ins_pipe - indicates what pipeline class an instruction is in
0N/A a. /* ... */ (like C code)
0N/A b. // ... EOL (like C++ code)
0N/A c. Comments must be preceeded by whitespace
0N/A a. %{ ... %} (% just distinguishes from C++ syntax)
0N/A b. Must be whitespace before and after block delimiters
0N/A a. ; (standard statement terminator)
0N/A b. %} (block terminator)
0N/A c. EOF (file terminator)
605N/A 4. Each statement must start on a separate line
0N/A 5. Identifiers cannot contain: (){}%;,"/\
0N/AE. Instruction Form: instruct instr1(oper1 dst, oper2 src) %{ ... %}
0N/A 1. Identifier (scope of all instruction names is global in ADL file)
0N/A a. Specified in argument style: (<type> <name>, ...)
0N/A b. Type must be the name of an Operand Form
0N/A c. Name is a locally scoped name, used for substitution, etc.
0N/A 3. Match Rule: match(SET dst (PLUS dst src));
0N/A a. Parenthesized Inorder Binary Tree: [lft = left; rgh = right]
0N/A (root root->lft (root->rgh (root->rgh->lft root->rgh->rgh)))
0N/A b. Interior nodes in tree are operators (nodes) in abstract IR
0N/A c. Leaves are operands from instruction operand list
0N/A d. Assignment operation and destination, which are implicit
0N/A in the abstract IR, must be specified in the match rule.
0N/A 4. Encode Rule: encode %{ return CONST; %}
0N/A a. Block form must contain C++ code which constitutes the
0N/A body of a C++ function which takes no arguments, and
0N/A b. Local names (operand names) are can be used as substitution
0N/A symbols in the code.
0N/A 5. Attribute (ins_attrib): ins_cost(37);
0N/A a. Identifier (must be name defined as instruction attribute)
0N/A b. Argument must be a constant value or a C++ expression which
0N/A evaluates to a constant at compile time.
0N/A *6. Effect: effect(src, OP_KILL);
0N/A a. Arguments must be the name of an operand and one of the
0N/A pre-defined effect type symbols:
0N/A OP_DEF, OP_USE, OP_KILL, OP_USE_DEF, OP_DEF_USE, OP_USE_KILL
0N/A a. Parameters for the new instructions must be the name of
0N/A an expand rule temporary operand or must match the local
0N/A operand name in both the instruction being expanded and
0N/A the new instruction being generated.
0N/A instruct convI2B( xRegI dst, eRegI src ) %{
0N/A match(Set dst (Conv2B src));
0N/A // Move zero into a register without setting flags
0N/A instruct loadZero(eRegI dst) %{
0N/A format %{ "MOV $dst,0" %}
0N/A opcode(0xB8); // +rd
0N/A ins_encode( LdI0(dst) );
0N/A 9. Format: format(add_X $src, $dst); | format %{ ... %}
0N/A a. Argument form takes a text string, possibly containing
0N/A some substitution symbols, which will be printed out
0N/A to the assembly language file.
0N/A b. The block form takes valid C++ code which forms the body
0N/A of a function which takes no arguments, and returns a
0N/A pointer to a string to print out to the assembly file.
0N/A Mentions of a literal register r in a or b must be of
0N/A the form r_enc or r_num. The form r_enc refers to the
0N/A encoding of the register in an instruction. The form
0N/A r_num refers to the number of the register. While
0N/A r_num is unique, two different registers may have the
0N/A same r_enc, as, for example, an integer and a floating
0N/AF. Operand Form: operand x_reg(REG_T rall) %{ ... %}
0N/A 1. Identifier (scope of all operand names is global in ADL file)
0N/A a. Specified in argument style: (<type> <name>, ...)
0N/A b. Type must be a predefined Component Type
0N/A c. Name is a locally scoped name, used for substitution, etc.
0N/A a. Parenthesized Inorder Binary Tree: [lft = left; rgh = right]
0N/A (root root->lft (root->rgh (root->rgh->lft root->rgh->rgh)))
0N/A b. Interior nodes in tree are operators (nodes) in abstract IR
0N/A c. Leaves are components from operand component list
0N/A d. Block following tree is the body of a C++ function taking
0N/A no arguments and returning no value, which assigns values
0N/A to the components of the operand at match time.
0N/A 4. Encode: encode %{ return CONST; %}
0N/A a. Block form must contain C++ code which constitutes the
0N/A body of a C++ function which takes no arguments, and
0N/A b. Local names (operand names) are can be used as substitution
0N/A symbols in the code.
0N/A 5. Attribute (op_attrib): op_cost(5);
0N/A a. Identifier (must be name defined as operand attribute)
0N/A b. Argument must be a constant value or a C++ expression which
0N/A evaluates to a constant at compile time.
0N/A 6. Predicate: predicate(0 <= src < 256);
0N/A a. Argument must be a valid C++ expression which evaluates
0N/A to either TRUE of FALSE at run time.
0N/A *7. Constraint: constraint(IS_RCLASS(dst, RC_X_CLASS));
0N/A a. Arguments must contain only predefined constraint
0N/A functions on values defined in the AD file.
0N/A b. Multiple arguments can be chained together logically
0N/A 8. Construct: construct %{ ... %}
0N/A a. Block must be a valid C++ function body which takes no
0N/A arguments, and returns no values.
0N/A b. Purpose of block is to assign values to the elements
0N/A of an operand which is constructed outside the matching
0N/A c. This block is logically identical to the constructor
0N/A block in a match rule.
0N/A 9. Format: format(add_X $src, $dst); | format %{ ... %}
0N/A a. Argument form takes a text string, possibly containing
0N/A some substitution symbols, which will be printed out
0N/A to the assembly language file.
0N/A b. The block form takes valid C++ code which forms the body
0N/A of a function which takes no arguments, and returns a
0N/A pointer to a string to print out to the assembly file.
0N/A Mentions of a literal register r in a or b must be of
0N/A the form r_enc or r_num. The form r_enc refers to the
0N/A encoding of the register in an instruction. The form
0N/A r_num refers to the number of the register. While
0N/A r_num is unique, two different registers may have the
0N/A same r_enc, as, for example, an integer and a floating
0N/AG. Operand Class Form: opclass memory( direct, indirect, ind_offset);
0N/AH. Attribute Form (keywords ins_atrib & op_attrib): ins_attrib ins_cost(10);
0N/A 1. Identifier (scope of all attribute names is global in ADL file)
0N/A 2. Argument must be a valid C++ expression which evaluates to a
0N/A constant at compile time, and specifies the default value of
0N/A this attribute if attribute definition is not included in an
0N/AI. Source Form: source %{ ... %}
0N/A a. All source blocks are delimited by "%{" and "%}".
0N/A b. All source blocks are copied verbatim into the
0N/A C++ output file, and must be valid C++ code.
0N/A Mentions of a literal register r in this code must
0N/A be of the form r_enc or r_num. The form r_enc
0N/A refers to the encoding of the register in an
0N/A instruction. The form r_num refers to the number of
0N/A the register. While r_num is unique, two different
0N/A registers may have the same r_enc, as, for example,
0N/A an integer and a floating point register.
0N/AJ. *Register Form: register %{ ... %}
0N/A 1. Block contains architecture specific information for allocation
0N/A 2. Reg_def: reg_def reg_AX(1);
0N/A a. Identifier is name by which register will be referenced
0N/A throughout the rest of the AD, and the allocator and
0N/A b. Argument is the Save on Entry index (where 0 means that
0N/A the register is Save on Call). This is used by the
0N/A frame management routines for generating register saves
0N/A 3. Reg_class: reg_class x_regs(reg_AX, reg_BX, reg_CX, reg_DX);
0N/A a. Identifier is the name of the class used throughout the
0N/A instruction selector.
0N/A b. Arguments are a list of register names in the class.
0N/A 4. Alloc_class: alloc_class x_alloc(reg_AX, reg_BX, reg_CX, reg_DX);
0N/A a. Identifier is the name of the class used throughout the
0N/A b. Arguments are a list of register names in the class.
0N/AK. *Pipeline Form: pipeline %{ ... %}
0N/A 1. Block contains architecture specific information for scheduling
0N/A 2. Resource: resource(ialu1);
0N/A a. Argument is the name of the resource.
0N/A 3. Pipe_desc: pipe_desc(Address, Access, Read, Execute);
0N/A a. Arguments are names of relevant phases of the pipeline.
0N/A b. If ALL instructions behave identically in a pipeline
0N/A phase, it does not need to be specified. (This is typically
0N/A true for pre-fetch, fetch, and decode pipeline stages.)
0N/A c. There must be one name per cycle consumed in the
0N/A pipeline, even if there is no instruction which has
0N/A significant behavior in that stage (for instance, extra
0N/A stages inserted for load and store instructions which
0N/A are just cycles which pass waiting for the completion
0N/A of the memory operation).
0N/A 4. Pipe_class: pipe_class pipe_normal(dagen; ; membus; ialu1, ialu2);
0N/A a. Identifier names the class for use in ins_pipe statements
0N/A b. Arguments are a list of stages, separated by ;'s which
0N/A contain comma separated lists of resource names.
0N/A c. There must be an entry for each stage defined in the
0N/A pipe_desc statement, (even if it is empty as in the example)
0N/A and entries are associated with stages by the order of
0N/A stage declarations in the pipe_desc statement.