2796N/A/*
2796N/A * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
2796N/A * Copyright 2007, 2008, 2009 Red Hat, Inc.
2796N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
2796N/A *
2796N/A * This code is free software; you can redistribute it and/or modify it
2796N/A * under the terms of the GNU General Public License version 2 only, as
2796N/A * published by the Free Software Foundation.
2796N/A *
2796N/A * This code is distributed in the hope that it will be useful, but WITHOUT
2796N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2796N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2796N/A * version 2 for more details (a copy is included in the LICENSE file that
2796N/A * accompanied this code).
2796N/A *
2796N/A * You should have received a copy of the GNU General Public License version
2796N/A * 2 along with this work; if not, write to the Free Software Foundation,
2796N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
2796N/A *
2796N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
2796N/A * or visit www.oracle.com if you need additional information or have any
2796N/A * questions.
2796N/A *
2796N/A */
2796N/A
2796N/A#ifndef OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP
2796N/A#define OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP
2796N/A
2796N/A#include "runtime/orderAccess.hpp"
2796N/A#include "vm_version_zero.hpp"
2796N/A
2796N/A#ifdef ARM
2796N/A
2796N/A/*
2796N/A * ARM Kernel helper for memory barrier.
2796N/A * Using __asm __volatile ("":::"memory") does not work reliable on ARM
2796N/A * and gcc __sync_synchronize(); implementation does not use the kernel
2796N/A * helper for all gcc versions so it is unreliable to use as well.
2796N/A */
2796N/Atypedef void (__kernel_dmb_t) (void);
2796N/A#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
2796N/A
2796N/A#define FULL_MEM_BARRIER __kernel_dmb()
2796N/A#define READ_MEM_BARRIER __kernel_dmb()
2796N/A#define WRITE_MEM_BARRIER __kernel_dmb()
2796N/A
2796N/A#else // ARM
2796N/A
2796N/A#define FULL_MEM_BARRIER __sync_synchronize()
2796N/A
2796N/A#ifdef PPC
2796N/A
2796N/A#ifdef __NO_LWSYNC__
2796N/A#define READ_MEM_BARRIER __asm __volatile ("sync":::"memory")
2796N/A#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
2796N/A#else
2796N/A#define READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
2796N/A#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
2796N/A#endif
2796N/A
2796N/A#else // PPC
2796N/A
2796N/A#define READ_MEM_BARRIER __asm __volatile ("":::"memory")
2796N/A#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
2796N/A
2796N/A#endif // PPC
2796N/A
2796N/A#endif // ARM
2796N/A
2796N/A
2796N/Ainline void OrderAccess::loadload() { acquire(); }
2796N/Ainline void OrderAccess::storestore() { release(); }
2796N/Ainline void OrderAccess::loadstore() { acquire(); }
2796N/Ainline void OrderAccess::storeload() { fence(); }
2796N/A
2796N/Ainline void OrderAccess::acquire() {
2796N/A READ_MEM_BARRIER;
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::release() {
2796N/A WRITE_MEM_BARRIER;
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::fence() {
2796N/A FULL_MEM_BARRIER;
2796N/A}
2796N/A
2796N/Ainline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; }
2796N/Ainline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; }
2796N/Ainline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; }
2796N/Ainline jlong OrderAccess::load_acquire(volatile jlong* p) {
2796N/A jlong tmp;
2796N/A os::atomic_copy64(p, &tmp);
2796N/A acquire();
2796N/A return tmp;
2796N/A}
2796N/Ainline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; }
2796N/Ainline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; }
2796N/Ainline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; }
2796N/Ainline julong OrderAccess::load_acquire(volatile julong* p) {
2796N/A julong tmp;
2796N/A os::atomic_copy64(p, &tmp);
2796N/A acquire();
2796N/A return tmp;
2796N/A}
2796N/Ainline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; }
2796N/Ainline jdouble OrderAccess::load_acquire(volatile jdouble* p) {
2796N/A jdouble tmp;
2796N/A os::atomic_copy64(p, &tmp);
2796N/A acquire();
2796N/A return tmp;
2796N/A}
2796N/A
2796N/Ainline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) {
2796N/A intptr_t data = *p;
2796N/A acquire();
2796N/A return data;
2796N/A}
2796N/Ainline void* OrderAccess::load_ptr_acquire(volatile void* p) {
2796N/A void *data = *(void* volatile *)p;
2796N/A acquire();
2796N/A return data;
2796N/A}
2796N/Ainline void* OrderAccess::load_ptr_acquire(const volatile void* p) {
2796N/A void *data = *(void* const volatile *)p;
2796N/A acquire();
2796N/A return data;
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jlong* p, jlong v)
2796N/A{ release(); os::atomic_copy64(&v, p); }
2796N/Ainline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile julong* p, julong v)
2796N/A{ release(); os::atomic_copy64(&v, p); }
2796N/Ainline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jdouble* p, jdouble v)
2796N/A{ release(); os::atomic_copy64(&v, p); }
2796N/A
2796N/Ainline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; }
2796N/Ainline void OrderAccess::release_store_ptr(volatile void* p, void* v)
2796N/A{ release(); *(void* volatile *)p = v; }
2796N/A
2796N/Ainline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jlong* p, jlong v) { os::atomic_copy64(&v, p); fence(); }
2796N/Ainline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(julong* p, julong v) { os::atomic_copy64(&v, p); fence(); }
2796N/Ainline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jdouble* p, jdouble v) { os::atomic_copy64(&v, p); fence(); }
2796N/A
2796N/Ainline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
2796N/A
2796N/Ainline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); }
2796N/A
2796N/Ainline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); }
2796N/Ainline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); }
2796N/A
2796N/A#endif // OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP