2796N/A/*
2796N/A * Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
2796N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
2796N/A *
2796N/A * This code is free software; you can redistribute it and/or modify it
2796N/A * under the terms of the GNU General Public License version 2 only, as
2796N/A * published by the Free Software Foundation.
2796N/A *
2796N/A * This code is distributed in the hope that it will be useful, but WITHOUT
2796N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2796N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2796N/A * version 2 for more details (a copy is included in the LICENSE file that
2796N/A * accompanied this code).
2796N/A *
2796N/A * You should have received a copy of the GNU General Public License version
2796N/A * 2 along with this work; if not, write to the Free Software Foundation,
2796N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
2796N/A *
2796N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
2796N/A * or visit www.oracle.com if you need additional information or have any
2796N/A * questions.
2796N/A *
2796N/A */
2796N/A
2796N/A#ifndef OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
2796N/A#define OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
2796N/A
2796N/A#include "runtime/atomic.hpp"
2796N/A#include "runtime/orderAccess.hpp"
2796N/A#include "vm_version_x86.hpp"
2796N/A
2796N/A// Implementation of class OrderAccess.
2796N/A
2796N/Ainline void OrderAccess::loadload() { acquire(); }
2796N/Ainline void OrderAccess::storestore() { release(); }
2796N/Ainline void OrderAccess::loadstore() { acquire(); }
2796N/Ainline void OrderAccess::storeload() { fence(); }
2796N/A
2796N/Ainline void OrderAccess::acquire() {
2796N/A volatile intptr_t local_dummy;
2796N/A#ifdef AMD64
2796N/A __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
2796N/A#else
2796N/A __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::release() {
2796N/A // Avoid hitting the same cache-line from
2796N/A // different threads.
2796N/A volatile jint local_dummy = 0;
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::fence() {
2796N/A if (os::is_MP()) {
2796N/A // always use locked addl since mfence is sometimes expensive
2796N/A#ifdef AMD64
2796N/A __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
2796N/A#else
2796N/A __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
2796N/A#endif
2796N/A }
2796N/A}
2796N/A
2796N/Ainline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
2796N/Ainline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
2796N/Ainline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
2796N/Ainline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
2796N/Ainline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
2796N/Ainline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
2796N/Ainline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
2796N/Ainline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
2796N/Ainline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
2796N/Ainline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
2796N/A
2796N/Ainline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
2796N/Ainline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
2796N/Ainline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
2796N/A
2796N/Ainline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
2796N/Ainline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
2796N/Ainline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
2796N/Ainline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
2796N/A
2796N/Ainline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
2796N/Ainline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
2796N/A
2796N/Ainline void OrderAccess::store_fence(jbyte* p, jbyte v) {
2796N/A __asm__ volatile ( "xchgb (%2),%0"
2796N/A : "=q" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/Ainline void OrderAccess::store_fence(jshort* p, jshort v) {
2796N/A __asm__ volatile ( "xchgw (%2),%0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/Ainline void OrderAccess::store_fence(jint* p, jint v) {
2796N/A __asm__ volatile ( "xchgl (%2),%0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::store_fence(jlong* p, jlong v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ("xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A *p = v; fence();
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/A// AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
2796N/A// compiler does the inlining this is simpler.
2796N/Ainline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
2796N/Ainline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
2796N/Ainline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
2796N/Ainline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
2796N/Ainline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
2796N/A
2796N/Ainline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ("xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A store_fence((jint*)p, (jint)v);
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::store_ptr_fence(void** p, void* v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ("xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A store_fence((jint*)p, (jint)v);
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/A// Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
2796N/Ainline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
2796N/A __asm__ volatile ( "xchgb (%2),%0"
2796N/A : "=q" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/Ainline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
2796N/A __asm__ volatile ( "xchgw (%2),%0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/Ainline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
2796N/A __asm__ volatile ( "xchgl (%2),%0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ( "xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A release_store(p, v); fence();
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/Ainline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
2796N/Ainline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
2796N/Ainline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
2796N/A
2796N/Ainline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
2796N/Ainline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
2796N/A
2796N/Ainline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ( "xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A release_store_fence((volatile jint*)p, (jint)v);
2796N/A#endif // AMD64
2796N/A}
2796N/Ainline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
2796N/A#ifdef AMD64
2796N/A __asm__ __volatile__ ( "xchgq (%2), %0"
2796N/A : "=r" (v)
2796N/A : "0" (v), "r" (p)
2796N/A : "memory");
2796N/A#else
2796N/A release_store_fence((volatile jint*)p, (jint)v);
2796N/A#endif // AMD64
2796N/A}
2796N/A
2796N/A#endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP