1010N/A/*
4155N/A * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
4155N/A * Copyright (c) 2007, 2013, Red Hat, Inc.
1010N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1010N/A *
1010N/A * This code is free software; you can redistribute it and/or modify it
1010N/A * under the terms of the GNU General Public License version 2 only, as
1010N/A * published by the Free Software Foundation.
1010N/A *
1010N/A * This code is distributed in the hope that it will be useful, but WITHOUT
1010N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1010N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1010N/A * version 2 for more details (a copy is included in the LICENSE file that
1010N/A * accompanied this code).
1010N/A *
1010N/A * You should have received a copy of the GNU General Public License version
1010N/A * 2 along with this work; if not, write to the Free Software Foundation,
1010N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1010N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
1010N/A *
1010N/A */
1010N/A
1879N/A#ifndef CPU_ZERO_VM_REGISTER_ZERO_HPP
1879N/A#define CPU_ZERO_VM_REGISTER_ZERO_HPP
1879N/A
1879N/A#include "asm/register.hpp"
1879N/A#include "vm_version_zero.hpp"
1879N/A
1010N/Aclass VMRegImpl;
1010N/Atypedef VMRegImpl* VMReg;
1010N/A
1010N/A// Use Register as shortcut
1010N/Aclass RegisterImpl;
1010N/Atypedef RegisterImpl* Register;
1010N/A
1010N/Ainline Register as_Register(int encoding) {
1010N/A return (Register)(intptr_t) encoding;
1010N/A}
1010N/A
1010N/A// The implementation of integer registers for the zero architecture
1010N/Aclass RegisterImpl : public AbstractRegisterImpl {
1010N/A public:
1010N/A enum {
1010N/A number_of_registers = 0
1010N/A };
1010N/A
1010N/A // construction
1010N/A inline friend Register as_Register(int encoding);
1010N/A VMReg as_VMReg();
1010N/A
1010N/A // derived registers, offsets, and addresses
1010N/A Register successor() const {
1010N/A return as_Register(encoding() + 1);
1010N/A }
1010N/A
1010N/A // accessors
1010N/A int encoding() const {
1010N/A assert(is_valid(), "invalid register");
1010N/A return (intptr_t)this;
1010N/A }
1010N/A bool is_valid() const {
1010N/A return 0 <= (intptr_t) this && (intptr_t)this < number_of_registers;
1010N/A }
1010N/A const char* name() const;
1010N/A};
1010N/A
1010N/A// Use FloatRegister as shortcut
1010N/Aclass FloatRegisterImpl;
1010N/Atypedef FloatRegisterImpl* FloatRegister;
1010N/A
1010N/Ainline FloatRegister as_FloatRegister(int encoding) {
1010N/A return (FloatRegister)(intptr_t) encoding;
1010N/A}
1010N/A
1010N/A// The implementation of floating point registers for the zero architecture
1010N/Aclass FloatRegisterImpl : public AbstractRegisterImpl {
1010N/A public:
1010N/A enum {
1010N/A number_of_registers = 0
1010N/A };
1010N/A
1010N/A // construction
1010N/A inline friend FloatRegister as_FloatRegister(int encoding);
1010N/A VMReg as_VMReg();
1010N/A
1010N/A // derived registers, offsets, and addresses
1010N/A FloatRegister successor() const {
1010N/A return as_FloatRegister(encoding() + 1);
1010N/A }
1010N/A
1010N/A // accessors
1010N/A int encoding() const {
1010N/A assert(is_valid(), "invalid register");
1010N/A return (intptr_t)this;
1010N/A }
1010N/A bool is_valid() const {
1010N/A return 0 <= (intptr_t) this && (intptr_t)this < number_of_registers;
1010N/A }
1010N/A const char* name() const;
1010N/A};
1010N/A
1010N/Aclass ConcreteRegisterImpl : public AbstractRegisterImpl {
1010N/A public:
1010N/A enum {
1010N/A number_of_registers = RegisterImpl::number_of_registers +
1010N/A FloatRegisterImpl::number_of_registers
1010N/A };
1010N/A
1010N/A static const int max_gpr;
1010N/A static const int max_fpr;
1010N/A};
1010N/A
1010N/ACONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
4155N/A#ifndef DONT_USE_REGISTER_DEFINES
4155N/A#define noreg ((Register)(noreg_RegisterEnumValue))
4155N/A#endif
1879N/A
1879N/A#endif // CPU_ZERO_VM_REGISTER_ZERO_HPP