0N/A// Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
0N/A// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A// This code is free software; you can redistribute it
and/or modify it
0N/A// under the terms of the GNU General Public License version 2 only, as
0N/A// published by the Free Software Foundation.
0N/A// This code is distributed in the hope that it will be useful, but WITHOUT
0N/A// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A// version 2 for more details (a copy is included in the LICENSE file that
0N/A// accompanied this code).
0N/A// You should have received a copy of the GNU General Public License version
0N/A// 2 along with this work; if not, write to the Free Software Foundation,
0N/A// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
0N/A// CA 95054 USA or visit
www.sun.com if you need additional information or
0N/A// have any questions.
0N/A// AMD64 Architecture Description File
0N/A//----------REGISTER DEFINITION BLOCK------------------------------------------
0N/A// This information is used by the matcher and the register allocator to
0N/A// describe individual registers and classes of registers within the target
0N/A//----------Architecture Description Register Definitions----------------------
0N/A// "reg_def" name ( register save type, C convention save type,
0N/A// ideal register type, encoding );
0N/A// Register Save Types:
0N/A// NS = No-Save: The register allocator assumes that these registers
0N/A// can be used without saving upon entry to the method, &
0N/A// that they do not need to be saved at call sites.
0N/A// SOC = Save-On-Call: The register allocator assumes that these registers
0N/A// can be used without saving upon entry to the method,
0N/A// but that they must be saved at call sites.
0N/A// SOE = Save-On-Entry: The register allocator assumes that these registers
0N/A// must be saved before using them upon entry to the
0N/A// method, but they do not need to be saved at call
0N/A// AS = Always-Save: The register allocator assumes that these registers
0N/A// must be saved before using them upon entry to the
0N/A// method, & that they must be saved at call sites.
0N/A// Ideal Register Type is used to determine how to save & restore a
0N/A// The encoding number is the actual bit-pattern placed into the opcodes.
0N/A// R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
0N/A// used as byte registers)
0N/A// Previously set RBX, RSI, and RDI as save-on-entry for java code
0N/A// Turn off SOE in java-code due to frequent use of uncommon-traps.
0N/A// Now that allocator is better, turn on RSI and RDI as SOE registers.
0N/Areg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
0N/Areg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
0N/Areg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
0N/Areg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
0N/Areg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
0N/Areg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
0N/Areg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
0N/Areg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
0N/Areg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
0N/Areg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
0N/A// now that adapter frames are gone RBP is always saved and restored by the
prolog/epilog code
0N/Areg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
0N/Areg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
0N/Areg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
0N/Areg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
0N/Areg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
0N/Areg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
0N/Areg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
0N/Areg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
0N/Areg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
0N/Areg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
0N/Areg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
0N/Areg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
0N/Areg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
0N/Areg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
0N/Areg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
0N/Areg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
0N/Areg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
0N/Areg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
0N/Areg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
0N/Areg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
0N/Areg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
0N/Areg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
0N/Areg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
0N/Areg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
0N/Areg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
0N/Areg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
0N/A// Floating Point Registers
0N/A// XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
0N/A// Word a in each register holds a Float, words ab hold a Double. We
0N/A// currently do not use the SIMD capabilities, so registers cd are
0N/A// unused at the moment.
0N/A// XMM8-XMM15 must be encoded with REX.
0N/A// Linux ABI: No register preserved across function calls
0N/A// XMM0-XMM7 might hold parameters
0N/A// Windows ABI: XMM6-XMM15 preserved across function calls
0N/A// XMM0-XMM3 might hold parameters
0N/Areg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
0N/Areg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
0N/Areg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
0N/Areg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
0N/Areg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
0N/Areg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
0N/Areg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
0N/Areg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
0N/Areg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
0N/Areg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
0N/Areg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
0N/Areg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
0N/Areg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
0N/Areg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
0N/Areg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
0N/Areg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
0N/Areg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
0N/Areg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
0N/Areg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
0N/Areg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
0N/Areg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
0N/Areg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
0N/Areg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
0N/Areg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
0N/Areg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
0N/Areg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
0N/Areg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
0N/Areg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
0N/Areg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
0N/Areg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
0N/Areg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
0N/Areg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
0N/Areg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
0N/Areg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
0N/Areg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
0N/Areg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
0N/Areg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
0N/Areg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
0N/Areg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
0N/Areg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
0N/Areg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
0N/Areg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
0N/Areg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
0N/Areg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
0N/Areg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
0N/Areg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
0N/Areg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
0N/Areg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
0N/Areg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
0N/Areg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
0N/Areg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
0N/Areg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
0N/Areg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
0N/A// Specify priority of register selection within phases of register
0N/A// allocation. Highest priority is first. A useful heuristic is to
0N/A// give registers a low priority when they are required by machine
0N/A// instructions, like EAX and EDX on I486, and choose no-save registers
0N/A// before save-on-call, & save-on-call before save-on-entry. Registers
0N/A// which participate in fixed calling sequences should come last.
0N/A// Registers which are used as pairs must fall on an even boundary.
0N/Aalloc_class chunk0(R10, R10_H,
0N/A// XXX probably use 8-15 first on Linux
0N/Aalloc_class chunk1(XMM0, XMM0_H,
0N/Aalloc_class chunk2(RFLAGS);
0N/A//----------Architecture Description Register Classes--------------------------
0N/A// Several register classes are automatically defined based upon information in
0N/A// this architecture description.
0N/A// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
0N/A// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
0N/A// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
0N/A// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
0N/A// Class for all pointer registers (including RSP)
0N/Areg_class any_reg(RAX, RAX_H,
0N/A// Class for all pointer registers except RSP
0N/Areg_class ptr_reg(RAX, RAX_H,
0N/A// Class for all pointer registers except RAX and RSP
0N/Areg_class ptr_no_rax_reg(RDX, RDX_H,
0N/Areg_class ptr_no_rbp_reg(RDX, RDX_H,
0N/A// Class for all pointer registers except RAX, RBX and RSP
0N/Areg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
0N/A// Singleton class for RAX pointer register
0N/Areg_class ptr_rax_reg(RAX, RAX_H);
0N/A// Singleton class for RBX pointer register
0N/Areg_class ptr_rbx_reg(RBX, RBX_H);
0N/A// Singleton class for RSI pointer register
0N/Areg_class ptr_rsi_reg(RSI, RSI_H);
0N/A// Singleton class for RDI pointer register
0N/Areg_class ptr_rdi_reg(RDI, RDI_H);
0N/A// Singleton class for RBP pointer register
0N/Areg_class ptr_rbp_reg(RBP, RBP_H);
0N/A// Singleton class for stack pointer
0N/Areg_class ptr_rsp_reg(RSP, RSP_H);
0N/A// Singleton class for TLS pointer
0N/Areg_class ptr_r15_reg(R15, R15_H);
0N/A// Class for all long registers (except RSP)
0N/Areg_class long_reg(RAX, RAX_H,
0N/A// Class for all long registers except RAX, RDX (and RSP)
0N/Areg_class long_no_rax_rdx_reg(RBP, RBP_H,
0N/A// Class for all long registers except RCX (and RSP)
0N/Areg_class long_no_rcx_reg(RBP, RBP_H,
0N/A// Class for all long registers except RAX (and RSP)
0N/Areg_class long_no_rax_reg(RBP, RBP_H,
0N/A// Singleton class for RAX long register
0N/Areg_class long_rax_reg(RAX, RAX_H);
0N/A// Singleton class for RCX long register
0N/Areg_class long_rcx_reg(RCX, RCX_H);
0N/A// Singleton class for RDX long register
0N/Areg_class long_rdx_reg(RDX, RDX_H);
113N/A// Singleton class for R12 long register
113N/Areg_class long_r12_reg(R12, R12_H);
0N/A// Class for all int registers (except RSP)
0N/Areg_class int_reg(RAX,
0N/A// Class for all int registers except RCX (and RSP)
0N/Areg_class int_no_rcx_reg(RAX,
0N/A// Class for all int registers except RAX, RDX (and RSP)
0N/Areg_class int_no_rax_rdx_reg(RBP,
0N/A// Singleton class for RAX int register
0N/Areg_class int_rax_reg(RAX);
0N/A// Singleton class for RBX int register
0N/Areg_class int_rbx_reg(RBX);
0N/A// Singleton class for RCX int register
0N/Areg_class int_rcx_reg(RCX);
0N/A// Singleton class for RCX int register
0N/Areg_class int_rdx_reg(RDX);
0N/A// Singleton class for RCX int register
0N/Areg_class int_rdi_reg(RDI);
0N/A// Singleton class for instruction pointer
0N/A// reg_class ip_reg(RIP);
0N/A// Singleton class for condition codes
0N/Areg_class int_flags(RFLAGS);
0N/A// Class for all float registers
0N/Areg_class float_reg(XMM0,
0N/A// Class for all double registers
0N/Areg_class double_reg(XMM0, XMM0_H,
0N/A//----------SOURCE BLOCK-------------------------------------------------------
0N/A// This is a block of C++ code which provides values, functions, and
0N/A// definitions necessary in the rest of the architecture description
0N/A#define RELOC_IMM64 Assembler::imm64_operand
0N/A#define RELOC_DISP32 Assembler::disp32_operand
0N/A// !!!!! Special hack to get all types of calls to specify the byte offset
0N/A// from the start of the call to the point where the return address
0N/Aint MachCallStaticJavaNode::ret_addr_offset()
0N/A return 5; // 5 bytes from start of call to where return address points
0N/Aint MachCallDynamicJavaNode::ret_addr_offset()
0N/A return 15; // 15 bytes from start of call to where return address points
0N/A// In os_cpu .ad file
0N/A// int MachCallRuntimeNode::ret_addr_offset()
0N/A// Indicate if the safepoint node needs the polling page as an input.
0N/A// Since amd64 does not have absolute addressing but RIP-relative
0N/A// addressing and the polling page is within 2G, it doesn't.
0N/Abool SafePointNode::needs_polling_address_input()
0N/A// Compute padding required for nodes which need alignment
0N/A// The address of the call instruction needs to be 4-byte aligned to
0N/A// ensure that it does not span a cache line so that it can be patched.
0N/Aint CallStaticJavaDirectNode::compute_padding(int current_offset) const
0N/A current_offset += 1; // skip call opcode byte
0N/A return round_to(current_offset, alignment_required()) - current_offset;
0N/A// The address of the call instruction needs to be 4-byte aligned to
0N/A// ensure that it does not span a cache line so that it can be patched.
0N/Aint CallDynamicJavaDirectNode::compute_padding(int current_offset) const
0N/A current_offset += 11; // skip movq instruction + call opcode byte
0N/A return round_to(current_offset, alignment_required()) - current_offset;
0N/Avoid MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
0N/Avoid emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
0N/A unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
0N/Avoid emit_cc(CodeBuffer &cbuf, int f1, int f2)
0N/A unsigned char c = (unsigned char) (f1 | f2);
0N/Avoid emit_opcode(CodeBuffer &cbuf, int code)
0N/A// EMIT_OPCODE() w/ relocation information
0N/Avoid emit_opcode(CodeBuffer &cbuf,
0N/A int code, relocInfo::relocType reloc, int offset, int format)
0N/A emit_opcode(cbuf, code);
0N/Avoid emit_d8(CodeBuffer &cbuf, int d8)
0N/Avoid emit_d16(CodeBuffer &cbuf, int d16)
0N/Avoid emit_d32(CodeBuffer &cbuf, int d32)
0N/Avoid emit_d64(CodeBuffer &cbuf, int64_t d64)
0N/A// emit 32 bit value and construct relocation entry from relocInfo::relocType
0N/Avoid emit_d32_reloc(CodeBuffer& cbuf,
0N/A relocInfo::relocType reloc,
0N/A assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
0N/A// emit 32 bit value and construct relocation entry from RelocationHolder
0N/Avoid emit_d32_reloc(CodeBuffer& cbuf,
0N/A RelocationHolder const& rspec,
0N/A d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
0N/A assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code");
0N/Avoid emit_d32_reloc(CodeBuffer& cbuf, address addr) {
0N/A emit_d32_reloc(cbuf, (int) (addr - next_ip),
0N/A external_word_Relocation::spec(addr),
0N/A// emit 64 bit value and construct relocation entry from relocInfo::relocType
0N/Avoid emit_d64_reloc(CodeBuffer& cbuf,
0N/A relocInfo::relocType reloc,
0N/A// emit 64 bit value and construct relocation entry from RelocationHolder
0N/Avoid emit_d64_reloc(CodeBuffer& cbuf,
0N/A RelocationHolder const& rspec,
0N/A d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
0N/A assert(oop(d64)->is_oop() && oop(d64)->is_perm(),
0N/A "cannot embed non-perm oops in code");
0N/A// Access stack slot for load or store
0N/Avoid store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
0N/A emit_opcode(cbuf, opcode); // (
e.g., FILD [RSP+src])
0N/A if (-0x80 <= disp && disp < 0x80) {
0N/A emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
0N/A emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
0N/A emit_d8(cbuf, disp); // Displacement // R/M byte
0N/A emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
0N/A emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
0N/A emit_d32(cbuf, disp); // Displacement // R/M byte
0N/A // rRegI ereg, memory mem) %{ // emit_reg_mem
0N/Avoid encode_RegMem(CodeBuffer &cbuf,
0N/A int base, int index, int scale, int disp, bool disp_is_oop)
0N/A assert(!disp_is_oop, "cannot have disp");
0N/A int regenc = reg & 7;
0N/A int baseenc = base & 7;
0N/A int indexenc = index & 7;
0N/A // There is no index & no scale, use form without SIB byte
0N/A if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
0N/A // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
0N/A if (disp == 0 && base != RBP_enc && base != R13_enc) {
0N/A emit_rm(cbuf, 0x0, regenc, baseenc); // *
0N/A } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
0N/A // If 8-bit displacement, mode 0x1
0N/A emit_rm(cbuf, 0x1, regenc, baseenc); // *
0N/A emit_d8(cbuf, disp);
0N/A // If 32-bit displacement
0N/A if (base == -1) { // Special flag for absolute address
0N/A emit_rm(cbuf, 0x0, regenc, 0x5); // *
0N/A emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
0N/A emit_d32(cbuf, disp);
0N/A // Normal base + offset
0N/A emit_rm(cbuf, 0x2, regenc, baseenc); // *
0N/A emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
0N/A emit_d32(cbuf, disp);
0N/A // Else, encode with the SIB byte
0N/A // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
0N/A if (disp == 0 && base != RBP_enc && base != R13_enc) {
0N/A // If no displacement
0N/A emit_rm(cbuf, 0x0, regenc, 0x4); // *
0N/A emit_rm(cbuf, scale, indexenc, baseenc);
0N/A if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
0N/A // If 8-bit displacement, mode 0x1
0N/A emit_rm(cbuf, 0x1, regenc, 0x4); // *
0N/A emit_rm(cbuf, scale, indexenc, baseenc);
0N/A emit_d8(cbuf, disp);
0N/A // If 32-bit displacement
0N/A if (base == 0x04 ) {
0N/A emit_rm(cbuf, 0x2, regenc, 0x4);
0N/A emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
0N/A emit_rm(cbuf, 0x2, regenc, 0x4);
0N/A emit_rm(cbuf, scale, indexenc, baseenc); // *
0N/A emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
0N/A emit_d32(cbuf, disp);
0N/Avoid encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
0N/A if (dstenc != srcenc) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x8B);
0N/A emit_rm(cbuf, 0x3, dstenc, srcenc);
0N/Avoid encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
0N/A if( dst_encoding == src_encoding ) {
0N/A // reg-reg copy, use an empty encoding
0N/A MacroAssembler _masm(&cbuf);
0N/A __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
0N/A//=============================================================================
0N/Avoid MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
0N/A Compile* C = ra_->C;
0N/A int framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
0N/A // Remove wordSize for return adr already pushed
0N/A // and another for the RBP we are going to save
0N/A framesize -= 2*wordSize;
0N/A bool need_nop = true;
0N/A // Calls to C2R adapters often do not accept exceptional returns.
0N/A // We require that their callers must bang for them. But be
0N/A // careful, because some VM calls (such as call site linkage) can
0N/A // use several kilobytes of stack. But the stack safety zone should
0N/A // account for that. See bugs 4446381, 4468289, 4497237.
0N/A if (C->need_stack_bang(framesize)) {
0N/A st->print_cr("# stack bang"); st->print("\t");
0N/A st->print_cr("pushq rbp"); st->print("\t");
0N/A if (VerifyStackAtCalls) {
0N/A // Majik cookie to verify stack depth
0N/A st->print_cr("pushq 0xffffffffbadb100d"
0N/A "\t# Majik cookie for stack depth check");
0N/A framesize -= wordSize; // Remove 2 for cookie
0N/A st->print("subq rsp, #%d\t# Create frame", framesize);
0N/A if (framesize < 0x80 && need_nop) {
0N/A st->print("\n\tnop\t# nop for patch_verified_entry");
0N/Avoid MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
0N/A Compile* C = ra_->C;
0N/A // WARNING: Initial instruction MUST be 5 bytes or longer so that
0N/A // NativeJump::patch_verified_entry will be able to patch out the entry
0N/A // code safely. The fldcw is ok at 6 bytes, the push to verify stack
0N/A // depth is ok at 5 bytes, the frame allocation can be either 3 or
0N/A // 6 bytes. So if we don't do the fldcw or the push then we must
0N/A // use the 6 byte frame allocation even if we have no frame. :-(
0N/A // If method sets FPU control word do it now
0N/A int framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
0N/A // Remove wordSize for return adr already pushed
0N/A // and another for the RBP we are going to save
0N/A framesize -= 2*wordSize;
0N/A bool need_nop = true;
0N/A // Calls to C2R adapters often do not accept exceptional returns.
0N/A // We require that their callers must bang for them. But be
0N/A // careful, because some VM calls (such as call site linkage) can
0N/A // use several kilobytes of stack. But the stack safety zone should
0N/A // account for that. See bugs 4446381, 4468289, 4497237.
0N/A if (C->need_stack_bang(framesize)) {
0N/A MacroAssembler masm(&cbuf);
0N/A // We always push rbp so that on return to interpreter rbp will be
0N/A // restored correctly and we can correct the stack.
0N/A emit_opcode(cbuf, 0x50 | RBP_enc);
0N/A if (VerifyStackAtCalls) {
0N/A // Majik cookie to verify stack depth
0N/A emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
0N/A emit_d32(cbuf, 0xbadb100d);
0N/A framesize -= wordSize; // Remove 2 for cookie
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A if (framesize < 0x80) {
0N/A emit_opcode(cbuf, 0x83); // sub SP,#framesize
0N/A emit_rm(cbuf, 0x3, 0x05, RSP_enc);
0N/A emit_d8(cbuf, framesize);
0N/A emit_opcode(cbuf, 0x90); // nop
0N/A emit_opcode(cbuf, 0x81); // sub SP,#framesize
0N/A emit_rm(cbuf, 0x3, 0x05, RSP_enc);
0N/A emit_d32(cbuf, framesize);
0N/A if (VerifyStackAtCalls) {
0N/A MacroAssembler masm(&cbuf);
0N/Auint MachPrologNode::size(PhaseRegAlloc* ra_) const
0N/A return MachNode::size(ra_); // too many variables; just compute it
0N/Aint MachPrologNode::reloc() const
0N/A return 0; // a large enough number
0N/A//=============================================================================
0N/Avoid MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
0N/A Compile* C = ra_->C;
0N/A int framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
0N/A // Remove word for return adr already pushed
0N/A framesize -= 2*wordSize;
0N/A st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
0N/A st->print_cr("popq\trbp");
0N/A if (do_polling() && C->is_method_compilation()) {
0N/A st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
0N/A "# Safepoint: poll for GC");
0N/Avoid MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
0N/A Compile* C = ra_->C;
0N/A int framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
0N/A // Remove word for return adr already pushed
0N/A framesize -= 2*wordSize;
0N/A // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A if (framesize < 0x80) {
0N/A emit_opcode(cbuf, 0x83); // addq rsp, #framesize
0N/A emit_rm(cbuf, 0x3, 0x00, RSP_enc);
0N/A emit_d8(cbuf, framesize);
0N/A emit_opcode(cbuf, 0x81); // addq rsp, #framesize
0N/A emit_rm(cbuf, 0x3, 0x00, RSP_enc);
0N/A emit_d32(cbuf, framesize);
0N/A emit_opcode(cbuf, 0x58 | RBP_enc);
0N/A if (do_polling() && C->is_method_compilation()) {
0N/A // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x85); // testl
0N/A emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
0N/A emit_d32_reloc(cbuf, os::get_polling_page());
0N/A// relocInfo::poll_return_type,
0N/Auint MachEpilogNode::size(PhaseRegAlloc* ra_) const
0N/A Compile* C = ra_->C;
0N/A int framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
0N/A // Remove word for return adr already pushed
0N/A framesize -= 2*wordSize;
0N/A if (do_polling() && C->is_method_compilation()) {
0N/A if (framesize < 0x80) {
0N/A } else if (framesize) {
0N/Aint MachEpilogNode::reloc() const
0N/A return 2; // a large enough number
0N/Aconst Pipeline* MachEpilogNode::pipeline() const
0N/A return MachNode::pipeline_class();
0N/Aint MachEpilogNode::safepoint_offset() const
0N/A//=============================================================================
0N/Astatic enum RC rc_class(OptoReg::Name reg)
0N/A if( !OptoReg::is_valid(reg) ) return rc_bad;
0N/A if (OptoReg::is_stack(reg)) return rc_stack;
0N/A VMReg r = OptoReg::as_VMReg(reg);
0N/A if (r->is_Register()) return rc_int;
0N/A assert(r->is_XMMRegister(), "must be");
0N/Auint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
0N/A outputStream* st) const
0N/A // Get registers to move
0N/A OptoReg::Name src_second = ra_->get_reg_second(in(1));
0N/A OptoReg::Name src_first = ra_->get_reg_first(in(1));
0N/A OptoReg::Name dst_second = ra_->get_reg_second(this);
0N/A OptoReg::Name dst_first = ra_->get_reg_first(this);
0N/A enum RC src_second_rc = rc_class(src_second);
0N/A enum RC src_first_rc = rc_class(src_first);
0N/A enum RC dst_second_rc = rc_class(dst_second);
0N/A enum RC dst_first_rc = rc_class(dst_first);
0N/A assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
0N/A "must move at least 1 register" );
0N/A if (src_first == dst_first && src_second == dst_second) {
0N/A // Self copy, no move
0N/A } else if (src_first_rc == rc_stack) {
0N/A if (dst_first_rc == rc_stack) {
0N/A assert(src_second != dst_first, "overlap");
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A int src_offset = ra_->reg2offset(src_first);
0N/A int dst_offset = ra_->reg2offset(dst_first);
0N/A emit_opcode(*cbuf, 0xFF);
0N/A encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
0N/A emit_opcode(*cbuf, 0x8F);
0N/A encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
0N/A } else if (!do_size) {
0N/A st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
0N/A 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
0N/A 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A int src_offset = ra_->reg2offset(src_first);
0N/A int dst_offset = ra_->reg2offset(dst_first);
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, 0x89);
0N/A emit_opcode(*cbuf, 0x44);
0N/A emit_opcode(*cbuf, 0x24);
0N/A emit_opcode(*cbuf, 0xF8);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A encode_RegMem(*cbuf,
0N/A RSP_enc, 0x4, 0, src_offset,
0N/A emit_opcode(*cbuf, 0x89);
0N/A encode_RegMem(*cbuf,
0N/A RSP_enc, 0x4, 0, dst_offset,
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A emit_opcode(*cbuf, 0x44);
0N/A emit_opcode(*cbuf, 0x24);
0N/A emit_opcode(*cbuf, 0xF8);
0N/A } else if (!do_size) {
0N/A st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
0N/A "movl rax, [rsp + #%d]\n\t"
0N/A "movl [rsp + #%d], rax\n\t"
0N/A "movq rax, [rsp - #8]",
0N/A 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
0N/A 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
0N/A } else if (dst_first_rc == rc_int) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A int offset = ra_->reg2offset(src_first);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, Assembler::REX_WR);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[dst_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movq %s, [rsp + #%d]\t# spill",
0N/A Matcher::regName[dst_first],
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A int offset = ra_->reg2offset(src_first);
0N/A if (Matcher::_regEncode[dst_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[dst_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movl %s, [rsp + #%d]\t# spill",
0N/A Matcher::regName[dst_first],
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[dst_first] < 8)
0N/A } else if (dst_first_rc == rc_float) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A int offset = ra_->reg2offset(src_first);
0N/A emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
0N/A if (Matcher::_regEncode[dst_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[dst_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("%s %s, [rsp + #%d]\t# spill",
0N/A UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
0N/A Matcher::regName[dst_first],
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[dst_first] < 8)
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A int offset = ra_->reg2offset(src_first);
0N/A emit_opcode(*cbuf, 0xF3);
0N/A if (Matcher::_regEncode[dst_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x10);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[dst_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movss %s, [rsp + #%d]\t# spill",
0N/A Matcher::regName[dst_first],
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[dst_first] < 8)
0N/A } else if (src_first_rc == rc_int) {
0N/A if (dst_first_rc == rc_stack) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A int offset = ra_->reg2offset(dst_first);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, Assembler::REX_WR);
0N/A emit_opcode(*cbuf, 0x89);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[src_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movq [rsp + #%d], %s\t# spill",
0N/A Matcher::regName[src_first]);
0N/A return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A int offset = ra_->reg2offset(dst_first);
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x89);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[src_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movl [rsp + #%d], %s\t# spill",
0N/A Matcher::regName[src_first]);
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[src_first] < 8)
0N/A } else if (dst_first_rc == rc_int) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, Assembler::REX_WB);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_WR);
0N/A emit_opcode(*cbuf, Assembler::REX_WRB);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movq %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_B);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, Assembler::REX_RB);
0N/A emit_opcode(*cbuf, 0x8B);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movl %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
0N/A } else if (dst_first_rc == rc_float) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A emit_opcode(*cbuf, 0x66);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, Assembler::REX_WB);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_WR);
0N/A emit_opcode(*cbuf, Assembler::REX_WRB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x6E);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movdq %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A emit_opcode(*cbuf, 0x66);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_B);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, Assembler::REX_RB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x6E);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movdl %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
0N/A } else if (src_first_rc == rc_float) {
0N/A if (dst_first_rc == rc_stack) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A int offset = ra_->reg2offset(dst_first);
0N/A emit_opcode(*cbuf, 0xF2);
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x11);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[src_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movsd [rsp + #%d], %s\t# spill",
0N/A Matcher::regName[src_first]);
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[src_first] < 8)
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A int offset = ra_->reg2offset(dst_first);
0N/A emit_opcode(*cbuf, 0xF3);
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x11);
0N/A encode_RegMem(*cbuf,
0N/A Matcher::_regEncode[src_first],
0N/A RSP_enc, 0x4, 0, offset,
0N/A } else if (!do_size) {
0N/A st->print("movss [rsp + #%d], %s\t# spill",
0N/A Matcher::regName[src_first]);
0N/A ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
0N/A ((Matcher::_regEncode[src_first] < 8)
0N/A } else if (dst_first_rc == rc_int) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A emit_opcode(*cbuf, 0x66);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_W);
0N/A emit_opcode(*cbuf, Assembler::REX_WR); // attention!
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_WB); // attention!
0N/A emit_opcode(*cbuf, Assembler::REX_WRB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x7E);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movdq %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A emit_opcode(*cbuf, 0x66);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R); // attention!
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_B); // attention!
0N/A emit_opcode(*cbuf, Assembler::REX_RB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, 0x7E);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("movdl %s, %s\t# spill",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
0N/A } else if (dst_first_rc == rc_float) {
0N/A if ((src_first & 1) == 0 && src_first + 1 == src_second &&
0N/A (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
0N/A emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_B);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, Assembler::REX_RB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("%s %s, %s\t# spill",
0N/A UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
0N/A assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
0N/A assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
0N/A if (!UseXmmRegToRegMoveAll)
0N/A emit_opcode(*cbuf, 0xF3);
0N/A if (Matcher::_regEncode[dst_first] < 8) {
0N/A if (Matcher::_regEncode[src_first] >= 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_B);
0N/A if (Matcher::_regEncode[src_first] < 8) {
0N/A emit_opcode(*cbuf, Assembler::REX_R);
0N/A emit_opcode(*cbuf, Assembler::REX_RB);
0N/A emit_opcode(*cbuf, 0x0F);
0N/A emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
0N/A Matcher::_regEncode[dst_first] & 7,
0N/A Matcher::_regEncode[src_first] & 7);
0N/A } else if (!do_size) {
0N/A st->print("%s %s, %s\t# spill",
0N/A UseXmmRegToRegMoveAll ? "movaps" : "movss ",
0N/A Matcher::regName[dst_first],
0N/A Matcher::regName[src_first]);
0N/A (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
0N/A ? (UseXmmRegToRegMoveAll ? 3 : 4)
0N/A : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
0N/Avoid MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
0N/A implementation(NULL, ra_, false, st);
0N/Avoid MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
0N/A implementation(&cbuf, ra_, false, NULL);
0N/Auint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
0N/A return implementation(NULL, ra_, true, NULL);
0N/A//=============================================================================
0N/Avoid MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
0N/A st->print("nop \t# %d bytes pad for loops and calls", _count);
0N/Avoid MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
0N/A MacroAssembler _masm(&cbuf);
0N/Auint MachNopNode::size(PhaseRegAlloc*) const
0N/A//=============================================================================
0N/Avoid BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
0N/A int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
0N/A int reg = ra_->get_reg_first(this);
0N/A st->print("leaq %s, [rsp + #%d]\t# box lock",
0N/A Matcher::regName[reg], offset);
0N/Avoid BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
0N/A int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
0N/A int reg = ra_->get_encode(this);
0N/A if (offset >= 0x80) {
0N/A emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
0N/A emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
0N/A emit_rm(cbuf, 0x2, reg & 7, 0x04);
0N/A emit_rm(cbuf, 0x0, 0x04, RSP_enc);
0N/A emit_d32(cbuf, offset);
0N/A emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
0N/A emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
0N/A emit_rm(cbuf, 0x1, reg & 7, 0x04);
0N/A emit_rm(cbuf, 0x0, 0x04, RSP_enc);
0N/A emit_d8(cbuf, offset);
0N/Auint BoxLockNode::size(PhaseRegAlloc *ra_) const
0N/A int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
0N/A return (offset < 0x80) ? 5 : 8; // REX
0N/A//=============================================================================
0N/A// emit call stub, compiled java to interpreter
0N/Avoid emit_java_to_interp(CodeBuffer& cbuf)
0N/A // Stub is fixed up when the corresponding call is converted from
0N/A // calling compiled code to calling interpreted code.
0N/A // Note that the code buffer's inst_mark is always relative to insts.
0N/A // That's why we must use the macroassembler to generate a stub.
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(Compile::MAX_stubs_size);
0N/A if (base == NULL) return; // CodeBuffer::expand failed
0N/A // static stub relocation stores the instruction address of the call
0N/A __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
0N/A // static stub relocation also tags the methodOop in the code-stream.
0N/A __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
0N/A __ jump(RuntimeAddress(__ pc()));
0N/A // Update current stubs pointer and restore code_end.
0N/A// size of call stub, compiled java to interpretor
0N/Auint size_java_to_interp()
0N/A return 15; // movq (1+1+8); jmp (1+4)
0N/A// relocation entries for call stub, compiled java to interpretor
0N/Auint reloc_java_to_interp()
0N/A return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
0N/A//=============================================================================
0N/Avoid MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
113N/A if (UseCompressedOops) {
113N/A st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
113N/A st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
113N/A st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
113N/A st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
113N/A "# Inline cache check", oopDesc::klass_offset_in_bytes());
0N/A st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
0N/A st->print_cr("\tnop");
0N/A if (!OptoBreakpoint) {
0N/A st->print_cr("\tnop");
0N/Avoid MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
0N/A MacroAssembler masm(&cbuf);
113N/A if (UseCompressedOops) {
0N/A masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A /* WARNING these NOPs are critical so that verified entry point is properly
0N/A aligned for patching by NativeJump::patch_verified_entry() */
0N/A if (!OptoBreakpoint) {
0N/A // Leave space for int3
113N/A if (UseCompressedOops) {
113N/A // ??? divisible by 4 is aligned?
0N/A "checking code size of inline cache node");
0N/Auint MachUEPNode::size(PhaseRegAlloc* ra_) const
113N/A if (UseCompressedOops) {
113N/A return OptoBreakpoint ? 19 : 20;
113N/A return OptoBreakpoint ? 11 : 12;
0N/A//=============================================================================
0N/Auint size_exception_handler()
0N/A // NativeCall instruction size is the same as NativeJump.
0N/A // the size of the code section.
0N/A return NativeJump::instruction_size;
0N/A// Emit exception handler code.
0N/Aint emit_exception_handler(CodeBuffer& cbuf)
0N/A // Note that the code buffer's inst_mark is always relative to insts.
0N/A // That's why we must use the macroassembler to generate a handler.
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(size_exception_handler());
0N/A if (base == NULL) return 0; // CodeBuffer::expand failed
0N/A int offset = __ offset();
0N/A __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
0N/A assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
0N/Auint size_deopt_handler()
0N/A // three 5 byte instructions
0N/A// Emit deopt handler code.
0N/Aint emit_deopt_handler(CodeBuffer& cbuf)
0N/A // Note that the code buffer's inst_mark is always relative to insts.
0N/A // That's why we must use the macroassembler to generate a handler.
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(size_deopt_handler());
0N/A if (base == NULL) return 0; // CodeBuffer::expand failed
0N/A int offset = __ offset();
0N/A address the_pc = (address) __ pc();
0N/A // push a "the_pc" on the stack without destroying any registers
0N/A // as they all may be live.
0N/A // push address of "next"
0N/A __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
0N/A // adjust it so it matches "the_pc"
0N/A __ subq(Address(rsp, 0), __ offset() - offset);
0N/A __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
0N/A assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
0N/Astatic void emit_double_constant(CodeBuffer& cbuf, double x) {
0N/A MacroAssembler _masm(&cbuf);
0N/A address double_address = __ double_constant(x);
0N/A cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
0N/A emit_d32_reloc(cbuf,
0N/A internal_word_Relocation::spec(double_address),
0N/Astatic void emit_float_constant(CodeBuffer& cbuf, float x) {
0N/A MacroAssembler _masm(&cbuf);
0N/A address float_address = __ float_constant(x);
0N/A cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
0N/A emit_d32_reloc(cbuf,
0N/A internal_word_Relocation::spec(float_address),
0N/Aint Matcher::regnum_to_fpu_offset(int regnum)
0N/A return regnum - 32; // The FP registers are in the second chunk
0N/A// This is UltraSparc specific, true just means we have fast l2f conversion
0N/Aconst bool Matcher::convL2FSupported(void) {
0N/A// Vector width in bytes
0N/Aconst uint Matcher::vector_width_in_bytes(void) {
0N/Aconst uint Matcher::vector_ideal_reg(void) {
0N/A// Is this branch offset short enough that a short branch can be used?
0N/A// NOTE: If the platform does not provide any short branch variants, then
0N/A// this method should return false for offset 0.
0N/Abool Matcher::is_short_branch_offset(int offset)
0N/A return -0x80 <= offset && offset < 0x80;
0N/Aconst bool Matcher::isSimpleConstant64(jlong value) {
0N/A // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
0N/A //return value == (int) value; // Cf. storeImmL and immL32.
0N/A // Probably always true, even if a temp register is required.
0N/A// The ecx parameter to rep stosq for the ClearArray node is in words.
0N/Aconst bool Matcher::init_array_count_is_in_bytes = false;
0N/A// Threshold size for cleararray.
0N/Aconst int Matcher::init_array_short_size = 8 * BytesPerLong;
0N/A// Should the Matcher clone shifts on addressing modes, expecting them
0N/A// to be subsumed into complex addressing expressions or compute them
0N/A// into registers? True for Intel but false for most RISCs
0N/Aconst bool Matcher::clone_shift_expressions = true;
0N/A// Is it better to copy float constants, or load them directly from
0N/A// memory? Intel can load a float constant from a direct address,
0N/A// requiring no extra registers. Most RISCs will have to materialize
0N/A// an address into a register first, so they would do better to copy
0N/A// the constant from stack.
0N/Aconst bool Matcher::rematerialize_float_constants = true; // XXX
0N/A// If CPU can load and store mis-aligned doubles directly then no
0N/A// fixup is needed. Else we split the double into 2 integer pieces
0N/A// and move it piece-by-piece. Only happens when passing doubles into
0N/A// C code as the Java calling convention forces doubles to be aligned.
0N/Aconst bool Matcher::misaligned_doubles_ok = true;
0N/Avoid Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
0N/A// Advertise here if the CPU requires explicit rounding operations to
0N/A// implement the UseStrictFP mode.
0N/Aconst bool Matcher::strict_fp_requires_explicit_rounding = true;
0N/A// Do floats take an entire double register or just half?
0N/Aconst bool Matcher::float_in_double = true;
0N/A// Do ints take an entire long register or just half?
0N/Aconst bool Matcher::int_in_long = true;
0N/A// Return whether or not this register is ever used as an argument.
0N/A// This function is used on startup to build the trampoline stubs in
0N/A// generateOptoStub. Registers not mentioned will be killed by the VM
0N/A// call in the trampoline, and arguments in those registers not be
0N/A// available to the callee.
0N/Abool Matcher::can_be_java_arg(int reg)
0N/A reg == RDI_num || reg == RDI_H_num ||
0N/A reg == RSI_num || reg == RSI_H_num ||
0N/A reg == RDX_num || reg == RDX_H_num ||
0N/A reg == RCX_num || reg == RCX_H_num ||
0N/A reg == R8_num || reg == R8_H_num ||
0N/A reg == R9_num || reg == R9_H_num ||
113N/A reg == R12_num || reg == R12_H_num ||
0N/A reg == XMM0_num || reg == XMM0_H_num ||
0N/A reg == XMM1_num || reg == XMM1_H_num ||
0N/A reg == XMM2_num || reg == XMM2_H_num ||
0N/A reg == XMM3_num || reg == XMM3_H_num ||
0N/A reg == XMM4_num || reg == XMM4_H_num ||
0N/A reg == XMM5_num || reg == XMM5_H_num ||
0N/A reg == XMM6_num || reg == XMM6_H_num ||
0N/A reg == XMM7_num || reg == XMM7_H_num;
0N/Abool Matcher::is_spillable_arg(int reg)
0N/A return can_be_java_arg(reg);
0N/A// Register for DIVI projection of divmodI
0N/ARegMask Matcher::divI_proj_mask() {
0N/A return INT_RAX_REG_mask;
0N/A// Register for MODI projection of divmodI
0N/ARegMask Matcher::modI_proj_mask() {
0N/A return INT_RDX_REG_mask;
0N/A// Register for DIVL projection of divmodL
0N/ARegMask Matcher::divL_proj_mask() {
0N/A return LONG_RAX_REG_mask;
0N/A// Register for MODL projection of divmodL
0N/ARegMask Matcher::modL_proj_mask() {
0N/A return LONG_RDX_REG_mask;
113N/Astatic Address build_address(int b, int i, int s, int d) {
113N/A Register index = as_Register(i);
113N/A Address::ScaleFactor scale = (Address::ScaleFactor)s;
113N/A scale = Address::no_scale;
113N/A Address addr(as_Register(b), index, scale, d);
0N/A//----------ENCODING BLOCK-----------------------------------------------------
0N/A// This block specifies the encoding classes used by the compiler to
0N/A// output byte streams. Encoding classes are parameterized macros
0N/A// used by Machine Instruction Nodes in order to generate the bit
0N/A// encoding of the instruction. Operands specify their base encoding
0N/A// interface with the interface keyword. There are currently
0N/A// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
0N/A// COND_INTER. REG_INTER causes an operand to generate a function
0N/A// which returns its register number when queried. CONST_INTER causes
0N/A// an operand to generate a function which returns the value of the
0N/A// constant when queried. MEMORY_INTER causes an operand to generate
0N/A// four functions which return the Base Register, the Index Register,
0N/A// the Scale Value, and the Offset Value of the operand when queried.
0N/A// COND_INTER causes an operand to generate six functions which return
0N/A// the encoding code (ie - encoding bits for the instruction)
0N/A// associated with each basic boolean condition for a conditional
0N/A// Instructions specify two basic values for encoding. Again, a
0N/A// function is available to check if the constant displacement is an
0N/A// oop. They use the ins_encode keyword to specify their encoding
0N/A// classes (which must be a sequence of enc_class names, and their
0N/A// parameters, specified in the encoding block), and they use the
0N/A// opcode keyword to specify, in order, their primary, secondary, and
0N/A// tertiary opcode. Only the opcode sections which a particular
0N/A// instruction needs for encoding need to be specified.
0N/A // Build emit functions for each basic byte or larger field in the
0N/A // intel encoding scheme (opcode, rm, sib, immediate), and call them
0N/A // from C++ code in the enc_class source block. Emit functions will
0N/A // live in the main source block for now. In future, we can
0N/A // generalize this by adding a syntax that specifies the sizes of
0N/A // fields in an order, so that the adlc can build the emit functions
0N/A // Emit primary opcode
0N/A emit_opcode(cbuf, $primary);
0N/A // Emit secondary opcode
0N/A emit_opcode(cbuf, $secondary);
0N/A // Emit tertiary opcode
0N/A emit_opcode(cbuf, $tertiary);
0N/A // Emit opcode directly
0N/A enc_class Opcode(immI d8)
0N/A emit_opcode(cbuf, $d8$$constant);
0N/A enc_class SizePrefix
0N/A emit_opcode(cbuf, 0x66);
0N/A enc_class reg(rRegI reg)
0N/A emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
0N/A enc_class reg_reg(rRegI dst, rRegI src)
0N/A emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
0N/A enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
0N/A emit_opcode(cbuf, $opcode$$constant);
0N/A emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
0N/A enc_class cmpfp_fixup()
0N/A emit_opcode(cbuf, 0x7B);
0N/A emit_d8(cbuf, 0x0A);
0N/A emit_opcode(cbuf, 0x9C);
0N/A // andq $0xffffff2b, (%rsp)
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x81);
0N/A emit_opcode(cbuf, 0x24);
0N/A emit_opcode(cbuf, 0x24);
0N/A emit_d32(cbuf, 0xffffff2b);
0N/A emit_opcode(cbuf, 0x9D);
0N/A // nop (target for branch to avoid branch to branch)
0N/A emit_opcode(cbuf, 0x90);
0N/A enc_class cmpfp3(rRegI dst)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xB8 | (dstenc & 7));
0N/A emit_opcode(cbuf, 0x7A);
0N/A emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
0N/A emit_opcode(cbuf, 0x72);
0N/A emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x95);
0N/A emit_opcode(cbuf, 0xC0 | (dstenc & 7));
0N/A // movzbl $dst, $dst
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0xB6);
0N/A emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
0N/A enc_class cdql_enc(no_rax_rdx_RegI div)
0N/A // Full implementation of Java idiv and irem; checks for
0N/A // special case as described in JVM spec., p.243 & p.271.
0N/A // normal case special case
0N/A // input : rax: dividend min_int
0N/A // output: rax: quotient (= rax idiv reg) min_int
0N/A // rdx: remainder (= rax irem reg) 0
0N/A // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
0N/A // 5: 75 07/08 jne e <normal>
0N/A // 7: 33 d2 xor %edx,%edx
0N/A // [div >= 8 -> offset + 1]
0N/A // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
0N/A // c: 74 03/04 je 11 <done>
0N/A // 000000000000000e <normal>:
0N/A // [div >= 8 -> offset + 1]
0N/A // f: f7 f9 idiv $div
0N/A // 0000000000000011 <done>:
0N/A // cmp $0x80000000,%eax
0N/A emit_opcode(cbuf, 0x3d);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x80);
0N/A emit_opcode(cbuf, 0x75);
0N/A emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
0N/A emit_opcode(cbuf, 0x33);
0N/A emit_d8(cbuf, 0xD2);
0N/A // cmp $0xffffffffffffffff,%ecx
0N/A if ($div$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
0N/A emit_d8(cbuf, 0xFF);
0N/A emit_opcode(cbuf, 0x74);
0N/A emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
0N/A emit_opcode(cbuf, 0x99);
0N/A // idivl (note: must be emitted by the user of this rule)
0N/A enc_class cdqq_enc(no_rax_rdx_RegL div)
0N/A // Full implementation of Java ldiv and lrem; checks for
0N/A // special case as described in JVM spec., p.243 & p.271.
0N/A // normal case special case
0N/A // input : rax: dividend min_long
0N/A // output: rax: quotient (= rax idiv reg) min_long
0N/A // rdx: remainder (= rax irem reg) 0
0N/A // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
0N/A // a: 48 39 d0 cmp %rdx,%rax
0N/A // d: 75 08 jne 17 <normal>
0N/A // f: 33 d2 xor %edx,%edx
0N/A // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
0N/A // 15: 74 05 je 1c <done>
0N/A // 0000000000000017 <normal>:
0N/A // 19: 48 f7 f9 idiv $div
0N/A // 000000000000001c <done>:
0N/A // mov $0x8000000000000000,%rdx
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0xBA);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x00);
0N/A emit_d8(cbuf, 0x80);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x39);
0N/A emit_d8(cbuf, 0xD0);
0N/A emit_opcode(cbuf, 0x75);
0N/A emit_d8(cbuf, 0x08);
0N/A emit_opcode(cbuf, 0x33);
0N/A emit_d8(cbuf, 0xD2);
0N/A // cmp $0xffffffffffffffff,$div
0N/A emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
0N/A emit_d8(cbuf, 0xFF);
0N/A emit_opcode(cbuf, 0x74);
0N/A emit_d8(cbuf, 0x05);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x99);
0N/A // idivq (note: must be emitted by the user of this rule)
0N/A // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
0N/A enc_class OpcSE(immI imm)
0N/A // Emit primary opcode and set sign-extend bit
0N/A // Check for 8-bit immediate, and set sign extend bit in opcode
0N/A if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
0N/A emit_opcode(cbuf, $primary | 0x02);
0N/A emit_opcode(cbuf, $primary);
0N/A enc_class OpcSErm(rRegI dst, immI imm)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A // Emit primary opcode and set sign-extend bit
0N/A // Check for 8-bit immediate, and set sign extend bit in opcode
0N/A if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
0N/A emit_opcode(cbuf, $primary | 0x02);
0N/A emit_opcode(cbuf, $primary);
0N/A // Emit r/m byte with secondary opcode, after primary opcode.
0N/A emit_rm(cbuf, 0x3, $secondary, dstenc);
0N/A enc_class OpcSErm_wide(rRegL dst, immI imm)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A // Emit primary opcode and set sign-extend bit
0N/A // Check for 8-bit immediate, and set sign extend bit in opcode
0N/A if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
0N/A emit_opcode(cbuf, $primary | 0x02);
0N/A emit_opcode(cbuf, $primary);
0N/A // Emit r/m byte with secondary opcode, after primary opcode.
0N/A emit_rm(cbuf, 0x3, $secondary, dstenc);
0N/A enc_class Con8or32(immI imm)
0N/A // Check for 8-bit immediate, and set sign extend bit in opcode
0N/A if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
0N/A $$$emit8$imm$$constant;
0N/A $$$emit32$imm$$constant;
0N/A enc_class Lbl(label labl)
0N/A Label* l = $labl$$label;
0N/A enc_class LblShort(label labl)
0N/A Label* l = $labl$$label;
0N/A assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
0N/A emit_d8(cbuf, disp);
0N/A enc_class opc2_reg(rRegI dst)
0N/A emit_cc(cbuf, $secondary, $dst$$reg);
0N/A enc_class opc3_reg(rRegI dst)
0N/A emit_cc(cbuf, $tertiary, $dst$$reg);
0N/A enc_class reg_opc(rRegI div)
0N/A // INC, DEC, IDIV, IMOD, JMP indirect, ...
0N/A emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
0N/A enc_class Jcc(cmpOp cop, label labl)
0N/A Label* l = $labl$$label;
0N/A emit_cc(cbuf, $secondary, $cop$$cmpcode);
0N/A enc_class JccShort (cmpOp cop, label labl)
0N/A Label *l = $labl$$label;
0N/A emit_cc(cbuf, $primary, $cop$$cmpcode);
0N/A assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
0N/A emit_d8(cbuf, disp);
0N/A enc_class enc_cmov(cmpOp cop)
0N/A emit_cc(cbuf, $secondary, $cop$$cmpcode);
0N/A enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
0N/A // Invert sense of branch from sense of cmov
0N/A emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
0N/A emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
0N/A ? (UseXmmRegToRegMoveAll ? 3 : 4)
0N/A : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
0N/A // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
0N/A if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
0N/A if ($dst$$reg < 8) {
0N/A if ($src$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
0N/A emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
0N/A enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
0N/A // Invert sense of branch from sense of cmov
0N/A emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
0N/A emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
0N/A // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
0N/A emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
0N/A if ($dst$$reg < 8) {
0N/A if ($src$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
0N/A emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
0N/A enc_class enc_PartialSubtypeCheck()
0N/A Register Rrdi = as_Register(RDI_enc); // result register
0N/A Register Rrax = as_Register(RAX_enc); // super class
0N/A Register Rrcx = as_Register(RCX_enc); // killed
0N/A Register Rrsi = as_Register(RSI_enc); // sub class
113N/A Label hit, miss, cmiss;
0N/A MacroAssembler _masm(&cbuf);
0N/A // Compare super with sub directly, since super is not in its own SSA.
0N/A // The compiler used to emit this test, but we fold it in here,
0N/A // to allow platform-specific tweaking on sparc.
0N/A __ cmpq(Rrax, Rrsi);
0N/A __ jcc(Assembler::equal, hit);
0N/A __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
0N/A __ incrementl(Address(Rrcx, 0));
0N/A __ movq(Rrdi, Address(Rrsi,
0N/A Klass::secondary_supers_offset_in_bytes()));
0N/A __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
0N/A __ addq(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
113N/A if (UseCompressedOops) {
113N/A __ encode_heap_oop(Rrax);
113N/A __ jcc(Assembler::notEqual, cmiss);
113N/A __ decode_heap_oop(Rrax);
113N/A Klass::secondary_super_cache_offset_in_bytes()),
113N/A __ decode_heap_oop(Rrax);
113N/A __ jcc(Assembler::notEqual, miss);
113N/A Klass::secondary_super_cache_offset_in_bytes()),
0N/A __ xorq(Rrdi, Rrdi);
0N/A enc_class Java_To_Interpreter(method meth)
0N/A // CALL Java_To_Interpreter
0N/A // This is the instruction starting address for relocation info.
0N/A // CALL directly to the runtime
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A enc_class Java_Static_Call(method meth)
0N/A // CALL to fixup routine. Fixup routine uses ScopeDesc info to
0N/A // determine who we intended to call.
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A } else if (_optimized_virtual) {
0N/A emit_d32_reloc(cbuf,
0N/A opt_virtual_call_Relocation::spec(),
0N/A emit_d32_reloc(cbuf,
0N/A static_call_Relocation::spec(),
0N/A // Emit stub for static call
0N/A emit_java_to_interp(cbuf);
0N/A enc_class Java_Dynamic_Call(method meth)
0N/A // JAVA DYNAMIC CALL
0N/A // Generate "movq rax, -1", placeholder instruction to load oop-info
0N/A // emit_call_dynamic_prologue( cbuf );
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0xB8 | RAX_enc);
0N/A emit_d64_reloc(cbuf,
0N/A (int64_t) Universe::non_oop_word(),
0N/A oop_Relocation::spec_for_immediate(), RELOC_IMM64);
0N/A // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
0N/A // who we intended to call.
0N/A emit_d32_reloc(cbuf,
0N/A virtual_call_Relocation::spec(virtual_call_oop_addr),
0N/A enc_class Java_Compiled_Call(method meth)
0N/A // JAVA COMPILED CALL
0N/A int disp = in_bytes(methodOopDesc:: from_compiled_offset());
0N/A // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
0N/A // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
0N/A // callq *disp(%rax)
0N/A emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
0N/A emit_d8(cbuf, disp); // Displacement
0N/A emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
0N/A emit_d32(cbuf, disp); // Displacement
0N/A enc_class reg_opc_imm(rRegI dst, immI8 shift)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_rm(cbuf, 0x3, $secondary, dstenc);
0N/A $$$emit8$shift$$constant;
0N/A enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_rm(cbuf, 0x3, $secondary, dstenc);
0N/A $$$emit8$shift$$constant;
0N/A enc_class load_immI(rRegI dst, immI src)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xB8 | dstenc);
0N/A $$$emit32$src$$constant;
0N/A enc_class load_immL(rRegL dst, immL src)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, 0xB8 | dstenc);
0N/A emit_d64(cbuf, $src$$constant);
0N/A enc_class load_immUL32(rRegL dst, immUL32 src)
0N/A // same as load_immI, but this time we care about zeroes in the high word
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xB8 | dstenc);
0N/A $$$emit32$src$$constant;
0N/A enc_class load_immL32(rRegL dst, immL32 src)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, 0xC7);
0N/A emit_rm(cbuf, 0x03, 0x00, dstenc);
0N/A $$$emit32$src$$constant;
0N/A enc_class load_immP31(rRegP dst, immP32 src)
0N/A // same as load_immI, but this time we care about zeroes in the high word
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xB8 | dstenc);
0N/A $$$emit32$src$$constant;
0N/A enc_class load_immP(rRegP dst, immP src)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, 0xB8 | dstenc);
0N/A // This next line should be generated from ADLC
0N/A if ($src->constant_is_oop()) {
0N/A emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
0N/A emit_d64(cbuf, $src$$constant);
0N/A enc_class load_immF(regF dst, immF con)
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
0N/A emit_float_constant(cbuf, $con$$constant);
0N/A enc_class load_immD(regD dst, immD con)
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
0N/A emit_double_constant(cbuf, $con$$constant);
0N/A enc_class load_conF (regF dst, immF con) %{ // Load float constant
0N/A emit_opcode(cbuf, 0xF3);
0N/A if ($dst$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x10);
0N/A emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
0N/A emit_float_constant(cbuf, $con$$constant);
0N/A enc_class load_conD (regD dst, immD con) %{ // Load double constant
0N/A // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
0N/A emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
0N/A if ($dst$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
0N/A emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
0N/A emit_double_constant(cbuf, $con$$constant);
0N/A // Encode a reg-reg copy. If it is useless, then empty encoding.
0N/A enc_class enc_copy(rRegI dst, rRegI src)
0N/A encode_copy(cbuf, $dst$$reg, $src$$reg);
0N/A // Encode xmm reg-reg copy. If it is useless, then empty encoding.
0N/A enc_class enc_CopyXD( RegD dst, RegD src ) %{
0N/A encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
0N/A enc_class enc_copy_always(rRegI dst, rRegI src)
0N/A int srcenc = $src$$reg;
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x8B);
0N/A emit_rm(cbuf, 0x3, dstenc, srcenc);
0N/A enc_class enc_copy_wide(rRegL dst, rRegL src)
0N/A int srcenc = $src$$reg;
0N/A int dstenc = $dst$$reg;
0N/A if (dstenc != srcenc) {
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, Assembler::REX_WR);
0N/A emit_opcode(cbuf, Assembler::REX_WRB);
0N/A emit_opcode(cbuf, 0x8B);
0N/A emit_rm(cbuf, 0x3, dstenc, srcenc);
0N/A enc_class Con32(immI src)
0N/A $$$emit32$src$$constant;
0N/A enc_class Con64(immL src)
0N/A emit_d64($src$$constant);
0N/A enc_class Con32F_as_bits(immF src)
0N/A // Output Float immediate bits
0N/A jfloat jf = $src$$constant;
0N/A jint jf_as_bits = jint_cast(jf);
0N/A emit_d32(cbuf, jf_as_bits);
0N/A enc_class Con16(immI src)
0N/A $$$emit16$src$$constant;
0N/A // How is this different from Con32??? XXX
0N/A enc_class Con_d32(immI src)
0N/A emit_d32(cbuf,$src$$constant);
0N/A enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
0N/A // Output immediate memory reference
0N/A emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
0N/A emit_d32(cbuf, 0x00);
0N/A enc_class jump_enc(rRegL switch_val, rRegI dest) %{
0N/A MacroAssembler masm(&cbuf);
0N/A Register switch_reg = as_Register($switch_val$$reg);
0N/A Register dest_reg = as_Register($dest$$reg);
0N/A // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
0N/A // to do that and the compiler is using that register as one it can allocate.
0N/A // So we build it all by hand.
0N/A // Address index(noreg, switch_reg, Address::times_1);
0N/A // ArrayAddress dispatch(table, index);
0N/A Address dispatch(dest_reg, switch_reg, Address::times_1);
0N/A enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
0N/A MacroAssembler masm(&cbuf);
0N/A Register switch_reg = as_Register($switch_val$$reg);
0N/A Register dest_reg = as_Register($dest$$reg);
0N/A // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
0N/A // to do that and the compiler is using that register as one it can allocate.
0N/A // So we build it all by hand.
0N/A // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
0N/A // ArrayAddress dispatch(table, index);
0N/A Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
0N/A enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
0N/A MacroAssembler masm(&cbuf);
0N/A Register switch_reg = as_Register($switch_val$$reg);
0N/A Register dest_reg = as_Register($dest$$reg);
0N/A // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
0N/A // to do that and the compiler is using that register as one it can allocate.
0N/A // So we build it all by hand.
0N/A // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
0N/A // ArrayAddress dispatch(table, index);
0N/A Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
0N/A enc_class lock_prefix()
0N/A emit_opcode(cbuf, 0xF0); // lock
0N/A enc_class REX_mem(memory mem)
0N/A if ($mem$$base >= 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_XB);
0N/A if ($mem$$index >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_X);
0N/A enc_class REX_mem_wide(memory mem)
0N/A if ($mem$$base >= 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, Assembler::REX_WXB);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WX);
0N/A enc_class REX_breg(rRegI reg)
0N/A if ($reg$$reg >= 4) {
0N/A emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
0N/A enc_class REX_reg_breg(rRegI dst, rRegI src)
0N/A if ($dst$$reg < 8) {
0N/A if ($src$$reg >= 4) {
0N/A emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A enc_class REX_breg_mem(rRegI reg, memory mem)
0N/A if ($reg$$reg < 8) {
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_X);
0N/A } else if ($reg$$reg >= 4) {
0N/A emit_opcode(cbuf, Assembler::REX);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_XB);
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RX);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, Assembler::REX_RXB);
0N/A enc_class REX_reg(rRegI reg)
0N/A if ($reg$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A enc_class REX_reg_wide(rRegI reg)
0N/A if ($reg$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A enc_class REX_reg_reg(rRegI dst, rRegI src)
0N/A if ($dst$$reg < 8) {
0N/A if ($src$$reg >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
0N/A if ($dst$$reg < 8) {
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A if ($src$$reg < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_WR);
0N/A emit_opcode(cbuf, Assembler::REX_WRB);
0N/A enc_class REX_reg_mem(rRegI reg, memory mem)
0N/A if ($reg$$reg < 8) {
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index >= 8) {
0N/A emit_opcode(cbuf, Assembler::REX_X);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_XB);
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RX);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, Assembler::REX_RXB);
0N/A enc_class REX_reg_mem_wide(rRegL reg, memory mem)
0N/A if ($reg$$reg < 8) {
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WX);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, Assembler::REX_WXB);
0N/A if ($mem$$base < 8) {
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_WR);
0N/A emit_opcode(cbuf, Assembler::REX_WRX);
0N/A if ($mem$$index < 8) {
0N/A emit_opcode(cbuf, Assembler::REX_WRB);
0N/A emit_opcode(cbuf, Assembler::REX_WRXB);
0N/A enc_class reg_mem(rRegI ereg, memory mem)
0N/A // High registers handle in encode_RegMem
0N/A int reg = $ereg$$reg;
0N/A int base = $mem$$base;
0N/A int index = $mem$$index;
0N/A int scale = $mem$$scale;
0N/A int disp = $mem$$disp;
0N/A bool disp_is_oop = $mem->disp_is_oop();
0N/A encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
0N/A enc_class RM_opc_mem(immI rm_opcode, memory mem)
0N/A int rm_byte_opcode = $rm_opcode$$constant;
0N/A // High registers handle in encode_RegMem
0N/A int base = $mem$$base;
0N/A int index = $mem$$index;
0N/A int scale = $mem$$scale;
0N/A int displace = $mem$$disp;
0N/A bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
0N/A // working with static
0N/A encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
0N/A enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
0N/A int reg_encoding = $dst$$reg;
0N/A int base = $src0$$reg; // 0xFFFFFFFF indicates no base
0N/A int index = 0x04; // 0x04 indicates no index
0N/A int scale = 0x00; // 0x00 indicates no scale
0N/A int displace = $src1$$constant; // 0x00 indicates no displacement
0N/A bool disp_is_oop = false;
0N/A encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
0N/A enc_class neg_reg(rRegI dst)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xF7);
0N/A emit_rm(cbuf, 0x3, 0x03, dstenc);
0N/A enc_class neg_reg_wide(rRegI dst)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, 0xF7);
0N/A emit_rm(cbuf, 0x3, 0x03, dstenc);
0N/A enc_class setLT_reg(rRegI dst)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A } else if (dstenc >= 4) {
0N/A emit_opcode(cbuf, Assembler::REX);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x9C);
0N/A emit_rm(cbuf, 0x3, 0x0, dstenc);
0N/A enc_class setNZ_reg(rRegI dst)
0N/A int dstenc = $dst$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A } else if (dstenc >= 4) {
0N/A emit_opcode(cbuf, Assembler::REX);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x95);
0N/A emit_rm(cbuf, 0x3, 0x0, dstenc);
0N/A enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
0N/A int tmpReg = $tmp$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x2B);
0N/A emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
0N/A emit_opcode(cbuf, 0x1B);
0N/A emit_rm(cbuf, 0x3, tmpReg, tmpReg);
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x23);
0N/A emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x03);
0N/A emit_rm(cbuf, 0x3, penc & 7, tmpReg);
0N/A // Compare the lonogs and set -1, 0, or 1 into dst
0N/A enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
0N/A int src1enc = $src1$$reg;
0N/A int src2enc = $src2$$reg;
0N/A int dstenc = $dst$$reg;
0N/A // cmpq $src1, $src2
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, Assembler::REX_WB);
0N/A emit_opcode(cbuf, Assembler::REX_WR);
0N/A emit_opcode(cbuf, Assembler::REX_WRB);
0N/A emit_opcode(cbuf, 0x3B);
0N/A emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0xB8 | (dstenc & 7));
0N/A emit_opcode(cbuf, 0x7C);
0N/A emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x95);
0N/A emit_opcode(cbuf, 0xC0 | (dstenc & 7));
0N/A // movzbl $dst, $dst
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0xB6);
0N/A emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
0N/A enc_class Push_ResultXD(regD dst) %{
0N/A int dstenc = $dst$$reg;
0N/A store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
0N/A // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
0N/A emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode (cbuf, 0x0F );
0N/A emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
0N/A encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf,0x83);
0N/A emit_rm(cbuf,0x3, 0x0, RSP_enc);
0N/A enc_class Push_SrcXD(regD src) %{
0N/A int srcenc = $src$$reg;
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x5, RSP_enc);
0N/A emit_opcode(cbuf, 0xF2);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x11);
0N/A encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
0N/A emit_opcode(cbuf, 0x66);
0N/A emit_opcode(cbuf, 0xDD);
0N/A encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
0N/A enc_class movq_ld(regD dst, memory mem) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
0N/A __ movq(as_XMMRegister($dst$$reg), madr);
0N/A enc_class movq_st(memory mem, regD src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
0N/A __ movq(madr, as_XMMRegister($src$$reg));
0N/A enc_class pshufd_8x8(regF dst, regF src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
0N/A __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
0N/A __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
0N/A enc_class pshufd_4x16(regF dst, regF src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
0N/A enc_class pshufd(regD dst, regD src, int mode) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
0N/A enc_class pxor(regD dst, regD src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
0N/A enc_class mov_i2x(regD dst, rRegI src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
0N/A // obj: object to lock
0N/A // box: box address (header location) -- killed
0N/A // tmp: rax -- killed
0N/A // scr: rbx -- killed
0N/A // What follows is a direct transliteration of fast_lock() and fast_unlock()
0N/A // TODO: where possible switch from movq (r, 0) to movl(r,0) and
0N/A // use the shorter encoding. (Movl clears the high-order 32-bits).
0N/A enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
0N/A Register objReg = as_Register((int)$obj$$reg);
0N/A Register boxReg = as_Register((int)$box$$reg);
0N/A Register tmpReg = as_Register($tmp$$reg);
0N/A Register scrReg = as_Register($scr$$reg);
0N/A MacroAssembler masm(&cbuf);
0N/A // Verify uniqueness of register assignments -- necessary but not sufficient
0N/A assert (objReg != boxReg && objReg != tmpReg &&
0N/A objReg != scrReg && tmpReg != scrReg, "invariant") ;
0N/A if (_counters != NULL) {
0N/A masm.movptr (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
0N/A if (UseBiasedLocking) {
0N/A // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
0N/A // Recursive locking
0N/A Label DONE_LABEL, IsInflated, Egress;
0N/A masm.testq (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
0N/A // it's stack-locked, biased or neutral
0N/A // TODO: optimize markword triage order to reduce the number of
0N/A // conditional branches in the most common cases.
0N/A // Beware -- there's a subtle invariant that fetch of the markword
0N/A // at [FETCH], below, will never observe a biased encoding (*101b).
0N/A // If this invariant is not held we'll suffer exclusion (safety) failure.
0N/A if (UseBiasedLocking) {
0N/A if (_counters != NULL) {
0N/A ExternalAddress((address) _counters->fast_path_entry_count_addr()));
0N/A // Recursive locking
0N/A if (_counters != NULL) {
0N/A ExternalAddress((address) _counters->fast_path_entry_count_addr()));
0N/A // TODO: someday avoid the ST-before-CAS penalty by
0N/A // relocating (deferring) the following ST.
0N/A // We should also think about trying a CAS without having
0N/A // fetched _owner. If the CAS is successful we may
0N/A // avoid an RTO->RTS upgrade on the $line.
0N/A masm.movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
0N/A masm.movq (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0N/A // It's inflated and appears unlocked
0N/A masm.cmpxchgq(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0N/A // Intentional fall-through into DONE_LABEL ...
0N/A // obj: object to unlock
0N/A // box: box address (displaced header location), killed
0N/A // RBX: killed tmp; cannot be obj nor box
0N/A enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
0N/A Register objReg = as_Register($obj$$reg);
0N/A Register boxReg = as_Register($box$$reg);
0N/A Register tmpReg = as_Register($tmp$$reg);
0N/A MacroAssembler masm(&cbuf);
0N/A if (UseBiasedLocking) {
0N/A // Check whether the displaced header is 0
0N/A //(=> recursive unlock)
0N/A // If not recursive lock, reset the header to displaced header
0N/A Label DONE_LABEL, Stacked, CheckSucc ;
0N/A if (UseBiasedLocking) {
0N/A masm.movq (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0N/A masm.orq (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
0N/A masm.movq (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
0N/A masm.orq (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
0N/A masm.mov64 (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
0N/A if ((EmitSync & 65536) == 0) {
0N/A Label LSuccess, LGoSlowPath ;
0N/A masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
0N/A // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
0N/A // the explicit ST;MEMBAR combination, but masm doesn't currently support
0N/A // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
0N/A // are all faster when the write buffer is populated.
0N/A masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
0N/A masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
0N/A masm.cmpxchgq (r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
0N/A // Intentional fall-through into slow-path
0N/A if (EmitSync & 65536) {
0N/A if (EmitSync & 32768) {
0N/A enc_class enc_String_Compare()
0N/A Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL,
0N/A POP_LABEL, DONE_LABEL, CONT_LABEL,
0N/A MacroAssembler masm(&cbuf);
0N/A // Get the first character position in both strings
0N/A // [8] char array, [12] offset, [16] count
0N/A int value_offset = java_lang_String::value_offset_in_bytes();
0N/A int offset_offset = java_lang_String::offset_offset_in_bytes();
0N/A int count_offset = java_lang_String::count_offset_in_bytes();
0N/A int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
0N/A masm.leaq(rax, Address(rax, rcx, Address::times_2, base_offset));
0N/A masm.leaq(rbx, Address(rbx, rcx, Address::times_2, base_offset));
0N/A // Compute the minimum of the string lengths(rsi) and the
0N/A // difference of the string lengths (stack)
0N/A // Is the minimum length zero?
0N/A // Load first characters
0N/A // Compare first characters
0N/A // Check after comparing first character to see if strings are equivalent
0N/A // Check if the strings start at same location
0N/A // Check if the length difference is zero (from stack)
0N/A // Strings might not be equivalent
0N/A // Shift RAX and RBX to the end of the arrays, negate min
0N/A // Compare the rest of the characters
0N/A // Strings are equal up to min length. Return the length difference.
0N/A // Discard the stored length difference
169N/A enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{
169N/A Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
169N/A MacroAssembler masm(&cbuf);
169N/A Register ary1Reg = as_Register($ary1$$reg);
169N/A Register ary2Reg = as_Register($ary2$$reg);
169N/A Register tmp1Reg = as_Register($tmp1$$reg);
169N/A Register tmp2Reg = as_Register($tmp2$$reg);
169N/A Register resultReg = as_Register($result$$reg);
169N/A int length_offset = arrayOopDesc::length_offset_in_bytes();
169N/A int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
169N/A // Check the input args
169N/A // Get the number of 4 byte vectors to compare
169N/A // Check for odd-length arrays
169N/A // Compare 2-byte "tail" at end of arrays
169N/A // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
169N/A masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
169N/A masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
169N/A // 4-byte-wide compare loop
169N/A masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
169N/A masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
0N/A enc_class enc_rethrow()
0N/A emit_opcode(cbuf, 0xE9); // jmp entry
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A enc_class absF_encoding(regF dst)
0N/A int dstenc = $dst$$reg;
0N/A address signmask_address = (address) StubRoutines::amd64::float_sign_mask();
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x54);
0N/A emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, signmask_address);
0N/A enc_class absD_encoding(regD dst)
0N/A int dstenc = $dst$$reg;
0N/A address signmask_address = (address) StubRoutines::amd64::double_sign_mask();
0N/A emit_opcode(cbuf, 0x66);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x54);
0N/A emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, signmask_address);
0N/A enc_class negF_encoding(regF dst)
0N/A int dstenc = $dst$$reg;
0N/A address signflip_address = (address) StubRoutines::amd64::float_sign_flip();
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x57);
0N/A emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, signflip_address);
0N/A enc_class negD_encoding(regD dst)
0N/A int dstenc = $dst$$reg;
0N/A address signflip_address = (address) StubRoutines::amd64::double_sign_flip();
0N/A emit_opcode(cbuf, 0x66);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x57);
0N/A emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, signflip_address);
0N/A enc_class f2i_fixup(rRegI dst, regF src)
0N/A int dstenc = $dst$$reg;
0N/A int srcenc = $src$$reg;
0N/A // cmpl $dst, #0x80000000
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x81);
0N/A emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
0N/A emit_d32(cbuf, 0x80000000);
0N/A emit_opcode(cbuf, 0x75);
0N/A if (srcenc < 8 && dstenc < 8) {
0N/A } else if (srcenc >= 8 && dstenc >= 8) {
0N/A emit_d8(cbuf, 0x11);
0N/A emit_d8(cbuf, 0x10);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x5, RSP_enc);
0N/A // movss [rsp], $src
0N/A emit_opcode(cbuf, 0xF3);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x11);
0N/A encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
0N/A emit_opcode(cbuf, 0xE8);
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x58 | (dstenc & 7));
0N/A enc_class f2l_fixup(rRegL dst, regF src)
0N/A int dstenc = $dst$$reg;
0N/A int srcenc = $src$$reg;
0N/A address const_address = (address) StubRoutines::amd64::double_sign_flip();
0N/A // cmpq $dst, [0x8000000000000000]
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
0N/A emit_opcode(cbuf, 0x39);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, const_address);
0N/A emit_opcode(cbuf, 0x75);
0N/A if (srcenc < 8 && dstenc < 8) {
0N/A } else if (srcenc >= 8 && dstenc >= 8) {
0N/A emit_d8(cbuf, 0x11);
0N/A emit_d8(cbuf, 0x10);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x5, RSP_enc);
0N/A // movss [rsp], $src
0N/A emit_opcode(cbuf, 0xF3);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x11);
0N/A encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
0N/A emit_opcode(cbuf, 0xE8);
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x58 | (dstenc & 7));
0N/A enc_class d2i_fixup(rRegI dst, regD src)
0N/A int dstenc = $dst$$reg;
0N/A int srcenc = $src$$reg;
0N/A // cmpl $dst, #0x80000000
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x81);
0N/A emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
0N/A emit_d32(cbuf, 0x80000000);
0N/A emit_opcode(cbuf, 0x75);
0N/A if (srcenc < 8 && dstenc < 8) {
0N/A } else if (srcenc >= 8 && dstenc >= 8) {
0N/A emit_d8(cbuf, 0x11);
0N/A emit_d8(cbuf, 0x10);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x5, RSP_enc);
0N/A // movsd [rsp], $src
0N/A emit_opcode(cbuf, 0xF2);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x11);
0N/A encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
0N/A emit_opcode(cbuf, 0xE8);
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x58 | (dstenc & 7));
0N/A enc_class d2l_fixup(rRegL dst, regD src)
0N/A int dstenc = $dst$$reg;
0N/A int srcenc = $src$$reg;
0N/A address const_address = (address) StubRoutines::amd64::double_sign_flip();
0N/A // cmpq $dst, [0x8000000000000000]
0N/A emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
0N/A emit_opcode(cbuf, 0x39);
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
0N/A emit_d32_reloc(cbuf, const_address);
0N/A emit_opcode(cbuf, 0x75);
0N/A if (srcenc < 8 && dstenc < 8) {
0N/A } else if (srcenc >= 8 && dstenc >= 8) {
0N/A emit_d8(cbuf, 0x11);
0N/A emit_d8(cbuf, 0x10);
0N/A emit_opcode(cbuf, Assembler::REX_W);
0N/A emit_opcode(cbuf, 0x83);
0N/A emit_rm(cbuf, 0x3, 0x5, RSP_enc);
0N/A // movsd [rsp], $src
0N/A emit_opcode(cbuf, 0xF2);
0N/A emit_opcode(cbuf, Assembler::REX_R);
0N/A emit_opcode(cbuf, 0x0F);
0N/A emit_opcode(cbuf, 0x11);
0N/A encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
0N/A emit_opcode(cbuf, 0xE8);
0N/A emit_d32_reloc(cbuf,
0N/A runtime_call_Relocation::spec(),
0N/A emit_opcode(cbuf, Assembler::REX_B);
0N/A emit_opcode(cbuf, 0x58 | (dstenc & 7));
0N/A enc_class enc_membar_acquire
0N/A // [jk] not needed currently, if you enable this and it really
0N/A // emits code don't forget to the remove the "size(0)" line in
0N/A // MacroAssembler masm(&cbuf);
0N/A // Assembler::LoadLoad));
0N/A enc_class enc_membar_release
0N/A // [jk] not needed currently, if you enable this and it really
0N/A // emits code don't forget to the remove the "size(0)" line in
0N/A // MacroAssembler masm(&cbuf);
0N/A // Assembler::StoreStore));
0N/A enc_class enc_membar_volatile
0N/A MacroAssembler masm(&cbuf);
0N/A Assembler::StoreStore));
0N/A // Safepoint Poll. This polls the safepoint page, and causes an
0N/A // exception if it is not readable. Unfortunately, it kills
0N/A // RFLAGS in the process.
0N/A enc_class enc_safepoint_poll
0N/A // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
0N/A // XXX reg_mem doesn't support RIP-relative addressing yet
0N/A emit_opcode(cbuf, 0x85); // testl
0N/A emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
0N/A emit_d32_reloc(cbuf, os::get_polling_page());
0N/A// relocInfo::poll_type,
0N/A//----------FRAME--------------------------------------------------------------
0N/A// Definition of frame structure and management information.
0N/A// S T A C K L A Y O U T Allocators stack-slot number
0N/A// | (to get allocators register number
0N/A// G Owned by | | v add OptoReg::stack0())
0N/A// o | +--------+ pad to even-align allocators stack-slot
0N/A// w V | pad0 | numbers; owned by CALLER
0N/A// t -----------+--------+----> Matcher::_in_arg_limit, unaligned
0N/A// | | args | 4 Holes in incoming args owned by SELF
0N/A// V | | old out| Empty on Intel, window on Sparc
0N/A// | old |preserve| Must be even aligned.
0N/A// | SP-+--------+----> Matcher::_old_SP, even aligned
0N/A// | | in | 3 area for Intel ret address
0N/A// Owned by |preserve| Empty on Sparc.
0N/A// | | pad2 | 2 pad to align old SP
0N/A// | +--------+----> OptoReg::stack0(), even aligned
0N/A// | | pad1 | 11 pad to align new SP
0N/A// | | spills | 9 spills
0N/A// V | | 8 (pad0 slot for callee)
0N/A// -----------+--------+----> Matcher::_out_arg_limit, unaligned
0N/A// | | args | 6 Holes in outgoing args owned by CALLEE
0N/A// Owned by +--------+
0N/A// CALLEE | new out| 6 Empty on Intel, window on Sparc
0N/A// | new |preserve| Must be even-aligned.
0N/A// | SP-+--------+----> Matcher::_new_SP, even aligned
0N/A// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
0N/A// known from SELF's arguments and the Java calling convention.
0N/A// Region 6-7 is determined per call site.
0N/A// Note 2: If the calling convention leaves holes in the incoming argument
0N/A// area, those holes are owned by SELF. Holes in the outgoing area
0N/A// are owned by the CALLEE. Holes should not be nessecary in the
0N/A// incoming area, as the Java calling convention is completely under
0N/A// the control of the AD file. Doubles can be sorted and packed to
0N/A// avoid holes. Holes in the outgoing arguments may be nessecary for
0N/A// varargs C calling conventions.
0N/A// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
0N/A// even aligned with pad0 as needed.
0N/A// Region 6 is even aligned. Region 6-7 is NOT even aligned;
0N/A// region 6-11 is even aligned; it may be padded out more so that
0N/A// the region from SP to FP meets the minimum stack alignment.
0N/A// Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
0N/A// alignment. Region 11, pad1, may be dynamically extended so that
0N/A// SP meets the minimum alignment.
0N/A // What direction does stack grow in (assumed to be same for C & Java)
0N/A stack_direction(TOWARDS_LOW);
0N/A // These three registers define part of the calling convention
0N/A // between compiled code and the interpreter.
0N/A inline_cache_reg(RAX); // Inline Cache Register
0N/A interpreter_method_oop_reg(RBX); // Method Oop Register when
0N/A // calling interpreter
0N/A // Optional: name the operand used by cisc-spilling to access
0N/A // [stack_pointer + offset]
0N/A cisc_spilling_operand_name(indOffset32);
0N/A // Number of stack slots consumed by locking an object
0N/A sync_stack_slots(2);
0N/A // Compiled code's Frame Pointer
0N/A // Interpreter stores its frame pointer in a register which is
0N/A // stored to the stack by I2CAdaptors.
0N/A // I2CAdaptors convert from interpreted java to compiled java.
0N/A interpreter_frame_pointer(RBP);
0N/A // Stack alignment requirement
0N/A stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
0N/A // Number of stack slots between incoming argument block and the start of
0N/A // a new frame. The PROLOG must add this many slots to the stack. The
0N/A // EPILOG must remove this many slots. amd64 needs two slots for
0N/A in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
0N/A // Number of outgoing stack slots killed above the out_preserve_stack_slots
0N/A // for calls to C. Supports the var-args backing area for register parms.
0N/A // The after-PROLOG location of the return address. Location of
0N/A // return address specifies a type (REG or STACK) and a number
0N/A // representing the register number (
i.e. - use a register name) or
0N/A // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
0N/A // Otherwise, it is above the locks and verification slot and alignment word
0N/A return_addr(STACK - 2 +
0N/A round_to(2 + 2 * VerifyStackAtCalls +
0N/A Compile::current()->fixed_slots(),
0N/A // Body of function which returns an integer array locating
0N/A // arguments either in registers or in stack slots. Passed an array
0N/A // of ideal registers called "sig" and a "length" count. Stack-slot
0N/A // offsets are based on outgoing arguments,
i.e. a CALLER setting up
0N/A // arguments for a CALLEE. Incoming stack arguments are
0N/A // automatically biased by the preserve_stack_slots field above.
0N/A SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
0N/A c_calling_convention
0N/A // This is obviously always outgoing
0N/A (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
0N/A // Location of compiled Java return values. Same as C for now.
0N/A assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
0N/A "only return normal values");
0N/A static const int lo[Op_RegL + 1] = {
0N/A XMM0_num, // Op_RegF
0N/A XMM0_num, // Op_RegD
0N/A static const int hi[Op_RegL + 1] = {
113N/A OptoReg::Bad, // Op_RegN
0N/A OptoReg::Bad, // Op_RegI
0N/A RAX_H_num, // Op_RegP
0N/A OptoReg::Bad, // Op_RegF
0N/A XMM0_H_num, // Op_RegD
0N/A RAX_H_num // Op_RegL
113N/A assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
0N/A return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
0N/A//----------ATTRIBUTES---------------------------------------------------------
0N/A//----------Operand Attributes-------------------------------------------------
0N/Aop_attrib op_cost(0); // Required cost attribute
0N/A//----------Instruction Attributes---------------------------------------------
0N/Ains_attrib ins_cost(100); // Required cost attribute
0N/Ains_attrib ins_size(8); // Required size attribute (in bits)
0N/Ains_attrib ins_pc_relative(0); // Required PC Relative flag
0N/Ains_attrib ins_short_branch(0); // Required flag: is this instruction
0N/A // a non-matching short branch variant
0N/A // of some long branch?
0N/Ains_attrib ins_alignment(1); // Required alignment attribute (must
0N/A // be a power of 2) specifies the
0N/A // alignment that some part of the
0N/A // instruction (not necessarily the
0N/A // start) requires. If > 1, a
0N/A // compute_padding() function must be
0N/A // provided for the instruction
0N/A//----------OPERANDS-----------------------------------------------------------
0N/A// Operand definitions must precede instruction definitions for correct parsing
0N/A// in the ADLC because operands constitute user defined types which are used in
0N/A// instruction definitions.
0N/A//----------Simple Operands----------------------------------------------------
0N/A// Immediate Operands
0N/A interface(CONST_INTER);
0N/A// Constant for test vs zero
0N/A predicate(n->get_int() == 0);
0N/A interface(CONST_INTER);
0N/A// Constant for increment
0N/A predicate(n->get_int() == 1);
0N/A interface(CONST_INTER);
0N/A// Constant for decrement
0N/A predicate(n->get_int() == -1);
0N/A interface(CONST_INTER);
0N/A// Valid scale values for addressing modes
0N/A predicate(0 <= n->get_int() && (n->get_int() <= 3));
0N/A interface(CONST_INTER);
0N/A predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
0N/A interface(CONST_INTER);
0N/A predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
0N/A interface(CONST_INTER);
0N/A// Constant for long shifts
0N/A predicate( n->get_int() == 32 );
0N/A interface(CONST_INTER);
0N/A// Constant for long shifts
0N/A predicate( n->get_int() == 64 );
0N/A interface(CONST_INTER);
0N/A interface(CONST_INTER);
0N/A// NULL Pointer Immediate
0N/A predicate(n->get_ptr() == 0);
0N/A interface(CONST_INTER);
113N/A interface(CONST_INTER);
113N/A// NULL Pointer Immediate
113N/A predicate(n->get_narrowcon() == 0);
113N/A interface(CONST_INTER);
0N/A predicate(!n->as_Type()->type()->isa_oopptr()
0N/A && (n->get_ptr() >> 31) == 0);
0N/A interface(CONST_INTER);
0N/A interface(CONST_INTER);
0N/A// Long Immediate 8-bit
0N/A predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
0N/A interface(CONST_INTER);
0N/A// Long Immediate 32-bit unsigned
0N/A predicate(n->get_long() == (unsigned int) (n->get_long()));
0N/A interface(CONST_INTER);
0N/A// Long Immediate 32-bit signed
0N/A predicate(n->get_long() == (int) (n->get_long()));
0N/A interface(CONST_INTER);
0N/A// Long Immediate zero
0N/A predicate(n->get_long() == 0L);
0N/A interface(CONST_INTER);
0N/A// Constant for increment
0N/A predicate(n->get_long() == 1);
0N/A interface(CONST_INTER);
0N/A// Constant for decrement
0N/A predicate(n->get_long() == -1);
0N/A interface(CONST_INTER);
0N/A// Long Immediate: the value 10
0N/A predicate(n->get_long() == 10);
0N/A interface(CONST_INTER);
0N/A// Long immediate from 0 to 127.
0N/A// Used for a shorter form of long mul by 10.
0N/A predicate(0 <= n->get_long() && n->get_long() < 0x80);
0N/A interface(CONST_INTER);
0N/A// Long Immediate: low 32-bit mask
0N/Aoperand immL_32bits()
0N/A predicate(n->get_long() == 0xFFFFFFFFL);
0N/A interface(CONST_INTER);
0N/A// Float Immediate zero
0N/A predicate(jint_cast(n->getf()) == 0);
0N/A interface(CONST_INTER);
0N/A interface(CONST_INTER);
0N/A// Double Immediate zero
0N/A predicate(jlong_cast(n->getd()) == 0);
0N/A interface(CONST_INTER);
0N/A interface(CONST_INTER);
0N/A// Immediates for special shifts (sign extend)
0N/A// Constants for increment
0N/A predicate(n->get_int() == 16);
0N/A interface(CONST_INTER);
0N/A predicate(n->get_int() == 24);
0N/A interface(CONST_INTER);
0N/A// Constant for byte-wide masking
0N/A predicate(n->get_int() == 255);
0N/A interface(CONST_INTER);
0N/A// Constant for short-wide masking
0N/A predicate(n->get_int() == 65535);
0N/A interface(CONST_INTER);
0N/A// Constant for byte-wide masking
0N/A predicate(n->get_long() == 255);
0N/A interface(CONST_INTER);
0N/A// Constant for short-wide masking
0N/A predicate(n->get_long() == 65535);
0N/A interface(CONST_INTER);
0N/A constraint(ALLOC_IN_RC(int_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(int_rax_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(int_rbx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(int_rcx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(int_rdx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(int_rdi_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rcx_RegI()
0N/A constraint(ALLOC_IN_RC(int_no_rcx_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rax_rdx_RegI()
0N/A constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(any_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(r15_RegP); // See Q&A below about r15_RegP.
0N/A interface(REG_INTER);
113N/A constraint(ALLOC_IN_RC(long_r12_reg));
113N/A constraint(ALLOC_IN_RC(int_reg));
0N/A// Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
0N/A// Answer: Operand match rules govern the DFA as it processes instruction inputs.
0N/A// It's fine for an instruction input which expects rRegP to match a r15_RegP.
0N/A// The output of an instruction is controlled by the allocator, which respects
0N/A// register class masks, not match rules. Unless an instruction mentions
0N/A// r15_RegP or any_RegP explicitly as its output, r15 will not be considered
0N/A// by the allocator as an input.
0N/Aoperand no_rax_RegP()
0N/A constraint(ALLOC_IN_RC(ptr_no_rax_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rbp_RegP()
0N/A constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rax_rbx_RegP()
0N/A constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
0N/A interface(REG_INTER);
0N/A// Return a pointer value
0N/A constraint(ALLOC_IN_RC(ptr_rax_reg));
0N/A interface(REG_INTER);
113N/A// Return a compressed pointer value
113N/A constraint(ALLOC_IN_RC(int_rax_reg));
0N/A constraint(ALLOC_IN_RC(ptr_rbx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_rsi_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_rdi_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_rbp_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_r15_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(long_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rax_rdx_RegL()
0N/A constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rax_RegL()
0N/A constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
0N/A interface(REG_INTER);
0N/Aoperand no_rcx_RegL()
0N/A constraint(ALLOC_IN_RC(long_no_rcx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(long_rax_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(long_rcx_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(long_rdx_reg));
0N/A interface(REG_INTER);
0N/A// Flags register, used as output of compare instructions
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "RFLAGS" %}
0N/A interface(REG_INTER);
0N/A// Flags register, used as output of FLOATING POINT compare instructions
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "RFLAGS_U" %}
0N/A interface(REG_INTER);
0N/A// Float register operands
0N/A constraint(ALLOC_IN_RC(float_reg));
0N/A interface(REG_INTER);
0N/A// Double register operands
0N/A constraint(ALLOC_IN_RC(double_reg));
0N/A interface(REG_INTER);
0N/A//----------Memory Operands----------------------------------------------------
0N/A// Direct Memory Operand
0N/A// operand direct(immP addr)
0N/A// format %{ "[$addr]" %}
0N/A// interface(MEMORY_INTER) %{
0N/A// Indirect Memory Operand
0N/Aoperand indirect(any_RegP reg)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Plus Short Offset Operand
0N/Aoperand indOffset8(any_RegP reg, immL8 off)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP reg off);
0N/A format %{ "[$reg + $off (8-bit)]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Plus Long Offset Operand
0N/Aoperand indOffset32(any_RegP reg, immL32 off)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP reg off);
0N/A format %{ "[$reg + $off (32-bit)]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Plus Index Register Plus Offset Operand
0N/Aoperand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP (AddP reg lreg) off);
0N/A format %{"[$reg + $off + $lreg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Plus Index Register Plus Offset Operand
0N/Aoperand indIndex(any_RegP reg, rRegL lreg)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP reg lreg);
0N/A format %{"[$reg + $lreg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Times Scale Plus Index Register
0N/Aoperand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP reg (LShiftL lreg scale));
0N/A format %{"[$reg + $lreg << $scale]" %}
0N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
0N/Aoperand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP (AddP reg (LShiftL lreg scale)) off);
0N/A format %{"[$reg + $off + $lreg << $scale]" %}
0N/A interface(MEMORY_INTER) %{
168N/A// Indirect Narrow Oop Plus Offset Operand
168N/Aoperand indNarrowOopOffset(rRegN src, immL32 off) %{
113N/A constraint(ALLOC_IN_RC(ptr_reg));
168N/A match(AddP (DecodeN src) off);
168N/A format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %}
113N/A interface(MEMORY_INTER) %{
0N/A// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
0N/Aoperand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
0N/A match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
0N/A format %{"[$reg + $off + $idx << $scale]" %}
0N/A interface(MEMORY_INTER) %{
0N/A//----------Special Memory Operands--------------------------------------------
0N/A// Stack Slot Operand - This operand is used for loading and storing temporary
0N/A// values on the stack where a match requires a value to
0N/A// flow through memory.
0N/Aoperand stackSlotP(sRegP reg)
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A // No match rule because this operand is only generated in matching
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A index(0x4); // No Index
0N/A scale(0x0); // No Scale
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotI(sRegI reg)
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A // No match rule because this operand is only generated in matching
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A index(0x4); // No Index
0N/A scale(0x0); // No Scale
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotF(sRegF reg)
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A // No match rule because this operand is only generated in matching
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A index(0x4); // No Index
0N/A scale(0x0); // No Scale
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotD(sRegD reg)
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A // No match rule because this operand is only generated in matching
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A index(0x4); // No Index
0N/A scale(0x0); // No Scale
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotL(sRegL reg)
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A // No match rule because this operand is only generated in matching
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A index(0x4); // No Index
0N/A scale(0x0); // No Scale
0N/A disp($reg); // Stack Offset
0N/A//----------Conditional Branch Operands----------------------------------------
0N/A// Comparison Op - This is the operation of the comparison, and is limited to
0N/A// the following set of codes:
0N/A// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
0N/A// Other attributes of the comparison, such as unsignedness, are specified
0N/A// by the comparison instruction that sets a condition code flags register.
0N/A// That result is represented by a flags operand whose subtype is appropriate
0N/A// to the unsignedness (etc.) of the comparison.
0N/A// Later, the instruction which matches both the Comparison Op (a Bool) and
0N/A// the flags (produced by the Cmp) specifies the coding of the comparison op
0N/A// by matching a specific subtype of Bool operand below, such as cmpOpU.
0N/A interface(COND_INTER) %{
0N/A// Comparison Code, unsigned compare. Used by FP also, with
0N/A// C2 (unordered) turned into GT or LT already. The other bits
0N/A// C0 and C3 are turned into Carry & Zero flags.
0N/A interface(COND_INTER) %{
0N/A//----------OPERAND CLASSES----------------------------------------------------
0N/A// Operand Classes are groups of operands that are used as to simplify
0N/A// instruction definitions by not requiring the AD writer to specify seperate
0N/A// instructions for every form of operand when the instruction accepts
0N/A// multiple operand types with the same basic encoding and format. The classic
0N/A// case of this is memory operands.
0N/Aopclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
113N/A indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
0N/A//----------PIPELINE-----------------------------------------------------------
0N/A// Rules which define the behavior of the target architectures pipeline.
0N/A//----------ATTRIBUTES---------------------------------------------------------
0N/A variable_size_instructions; // Fixed size instructions
0N/A max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
0N/A instruction_unit_size = 1; // An instruction is 1 bytes long
0N/A instruction_fetch_unit_size = 16; // The processor fetches one line
0N/A instruction_fetch_units = 1; // of 16 bytes
0N/A // List of nop instructions
0N/A//----------RESOURCES----------------------------------------------------------
0N/A// Resources are the functional units available to the machine
0N/A// 3 decoders, only D0 handles big operands; a "bundle" is the limit of
0N/A// 3 instructions decoded per cycle.
0N/A// 3 ALU op, only ALU0 handles mul instructions.
0N/Aresources( D0, D1, D2, DECODE = D0 | D1 | D2,
0N/A MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
0N/A ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
0N/A//----------PIPELINE DESCRIPTION-----------------------------------------------
0N/A// Pipeline Description specifies the stages in the machine's pipeline
0N/Apipe_desc(S0, S1, S2, S3, S4, S5);
0N/A//----------PIPELINE CLASSES---------------------------------------------------
0N/A// Pipeline Classes describe the stages in which input and output are
0N/A// referenced by the hardware pipeline.
0N/A// Naming convention: ialu or fpu
0N/A// Then: _reg if there is a 2nd register
0N/A// Then: _long if it's a pair of instructions implementing a long
0N/A// Then: _fat if it requires the big decoder
0N/A// Or: _mem if it requires the big decoder and a memory unit.
0N/A// Integer ALU reg operation
0N/Apipe_class ialu_reg(rRegI dst)
0N/A DECODE : S0; // any decoder
0N/A ALU : S3; // any alu
0N/A// Long ALU reg operation
0N/Apipe_class ialu_reg_long(rRegL dst)
0N/A instruction_count(2);
0N/A DECODE : S0(2); // any 2 decoders
0N/A ALU : S3(2); // both alus
0N/A// Integer ALU reg operation using big decoder
0N/Apipe_class ialu_reg_fat(rRegI dst)
0N/A D0 : S0; // big decoder only
0N/A ALU : S3; // any alu
0N/A// Long ALU reg operation using big decoder
0N/Apipe_class ialu_reg_long_fat(rRegL dst)
0N/A instruction_count(2);
0N/A D0 : S0(2); // big decoder only; twice
0N/A ALU : S3(2); // any 2 alus
0N/A// Integer ALU reg-reg operation
0N/Apipe_class ialu_reg_reg(rRegI dst, rRegI src)
0N/A DECODE : S0; // any decoder
0N/A ALU : S3; // any alu
0N/A// Long ALU reg-reg operation
0N/Apipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
0N/A instruction_count(2);
0N/A DECODE : S0(2); // any 2 decoders
0N/A ALU : S3(2); // both alus
0N/A// Integer ALU reg-reg operation
0N/Apipe_class ialu_reg_reg_fat(rRegI dst, memory src)
0N/A D0 : S0; // big decoder only
0N/A ALU : S3; // any alu
0N/A// Long ALU reg-reg operation
0N/Apipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
0N/A instruction_count(2);
0N/A D0 : S0(2); // big decoder only; twice
0N/A ALU : S3(2); // both alus
0N/A// Integer ALU reg-mem operation
0N/Apipe_class ialu_reg_mem(rRegI dst, memory mem)
0N/A D0 : S0; // big decoder only
0N/A ALU : S4; // any alu
0N/A MEM : S3; // any mem
0N/A// Integer mem operation (prefetch)
0N/Apipe_class ialu_mem(memory mem)
0N/A D0 : S0; // big decoder only
0N/A MEM : S3; // any mem
0N/A// Integer Store to Memory
0N/Apipe_class ialu_mem_reg(memory mem, rRegI src)
0N/A D0 : S0; // big decoder only
0N/A ALU : S4; // any alu
0N/A// // Long Store to Memory
0N/A// pipe_class ialu_mem_long_reg(memory mem, rRegL src)
0N/A// instruction_count(2);
0N/A// D0 : S0(2); // big decoder only; twice
0N/A// ALU : S4(2); // any 2 alus
0N/A// MEM : S3(2); // Both mems
0N/A// Integer Store to Memory
0N/Apipe_class ialu_mem_imm(memory mem)
0N/A D0 : S0; // big decoder only
0N/A ALU : S4; // any alu
0N/A// Integer ALU0 reg-reg operation
0N/Apipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
0N/A D0 : S0; // Big decoder only
0N/A ALU0 : S3; // only alu0
0N/A// Integer ALU0 reg-mem operation
0N/Apipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
0N/A D0 : S0; // big decoder only
0N/A ALU0 : S4; // ALU0 only
0N/A MEM : S3; // any mem
0N/A// Integer ALU reg-reg operation
0N/Apipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
0N/A DECODE : S0; // any decoder
0N/A ALU : S3; // any alu
0N/A// Integer ALU reg-imm operation
0N/Apipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
0N/A DECODE : S0; // any decoder
0N/A ALU : S3; // any alu
0N/A// Integer ALU reg-mem operation
0N/Apipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
0N/A D0 : S0; // big decoder only
0N/A ALU : S4; // any alu
0N/A// Conditional move reg-reg
0N/Apipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
0N/A instruction_count(4);
0N/A DECODE : S0(4); // any decoder
0N/A// Conditional move reg-reg
0N/Apipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
0N/A DECODE : S0; // any decoder
0N/A// Conditional move reg-mem
0N/Apipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
0N/A DECODE : S0; // any decoder
0N/A// Conditional move reg-reg long
0N/Apipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
0N/A DECODE : S0(2); // any 2 decoders
0N/A// // Conditional move double reg-reg
0N/A// pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
0N/A// single_instruction;
0N/A// DECODE : S0; // any decoder
0N/A// Float reg-reg operation
0N/Apipe_class fpu_reg(regD dst)
0N/A instruction_count(2);
0N/A DECODE : S0(2); // any 2 decoders
0N/A// Float reg-reg operation
0N/Apipe_class fpu_reg_reg(regD dst, regD src)
0N/A instruction_count(2);
0N/A DECODE : S0(2); // any 2 decoders
0N/A// Float reg-reg operation
0N/Apipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
0N/A instruction_count(3);
0N/A DECODE : S0(3); // any 3 decoders
0N/A// Float reg-reg operation
0N/Apipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
0N/A instruction_count(4);
0N/A DECODE : S0(4); // any 3 decoders
0N/A// Float reg-reg operation
0N/Apipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
0N/A instruction_count(4);
0N/A DECODE : S1(3); // any 3 decoders
0N/A D0 : S0; // Big decoder only
0N/A// Float reg-mem operation
0N/Apipe_class fpu_reg_mem(regD dst, memory mem)
0N/A instruction_count(2);
0N/A D0 : S0; // big decoder only
0N/A DECODE : S1; // any decoder for FPU POP
0N/A MEM : S3; // any mem
0N/A// Float reg-mem operation
0N/Apipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
0N/A instruction_count(3);
0N/A D0 : S0; // big decoder only
0N/A DECODE : S1(2); // any decoder for FPU POP
0N/A MEM : S3; // any mem
0N/A// Float mem-reg operation
0N/Apipe_class fpu_mem_reg(memory mem, regD src)
0N/A instruction_count(2);
0N/A DECODE : S0; // any decoder for FPU PUSH
0N/A D0 : S1; // big decoder only
0N/A MEM : S3; // any mem
0N/Apipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
0N/A instruction_count(3);
0N/A DECODE : S0(2); // any decoder for FPU PUSH
0N/A D0 : S1; // big decoder only
0N/A MEM : S3; // any mem
0N/Apipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
0N/A instruction_count(3);
0N/A DECODE : S0; // any decoder for FPU PUSH
0N/A D0 : S0(2); // big decoder only
0N/A MEM : S3(2); // any mem
0N/Apipe_class fpu_mem_mem(memory dst, memory src1)
0N/A instruction_count(2);
0N/A D0 : S0(2); // big decoder only
0N/A MEM : S3(2); // any mem
0N/Apipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
0N/A instruction_count(3);
0N/A D0 : S0(3); // big decoder only
0N/A MEM : S3(3); // any mem
0N/Apipe_class fpu_mem_reg_con(memory mem, regD src1)
0N/A instruction_count(3);
0N/A DECODE : S0; // any decoder for FPU PUSH
0N/A D0 : S0(2); // big decoder only
0N/A MEM : S3(2); // any mem
0N/A// Float load constant
0N/Apipe_class fpu_reg_con(regD dst)
0N/A instruction_count(2);
0N/A D0 : S0; // big decoder only for the load
0N/A DECODE : S1; // any decoder for FPU POP
0N/A MEM : S3; // any mem
0N/A// Float load constant
0N/Apipe_class fpu_reg_reg_con(regD dst, regD src)
0N/A instruction_count(3);
0N/A D0 : S0; // big decoder only for the load
0N/A DECODE : S1(2); // any decoder for FPU POP
0N/A MEM : S3; // any mem
0N/A// UnConditional branch
0N/Apipe_class pipe_jmp(label labl)
0N/A// Conditional branch
0N/Apipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
0N/Apipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
0N/A instruction_count(1); force_serialization;
0N/A heap_ptr : S3(read);
0N/Apipe_class pipe_slow()
0N/A instruction_count(10); multiple_bundles; force_serialization;
0N/A// The real do-nothing guy
0N/A instruction_count(0);
0N/A// Define the class for the Nop node
0N/A//----------INSTRUCTIONS-------------------------------------------------------
0N/A// match -- States which machine-independent subtree may be replaced
0N/A// by this instruction.
0N/A// ins_cost -- The estimated cost of this instruction is used by instruction
0N/A// selection to identify a minimum cost tree of machine
0N/A// instructions that matches a tree of machine-independent
0N/A// format -- A string providing the disassembly for this instruction.
0N/A// The value of an instruction's operand may be inserted
0N/A// by referring to it with a '$' prefix.
0N/A// opcode -- Three instruction opcodes may be provided. These are referred
0N/A// to within an encode class as $primary, $secondary, and $tertiary
0N/A// rrspectively. The primary opcode is commonly used to
0N/A// indicate the type of machine instruction, while secondary
0N/A// and tertiary are often used for prefix options or addressing
0N/A// ins_encode -- A list of encode classes with parameters. The encode class
0N/A// name must have been defined in an 'enc_class' specification
0N/A// in the encode section of the architecture description.
0N/A//----------Load
/Store/Move Instructions---------------------------------------
0N/A//----------Load Instructions--------------------------------------------------
0N/A// Load Byte (8 bit signed)
0N/Ainstruct loadB(rRegI dst, memory mem)
0N/A match(Set dst (LoadB mem));
0N/A format %{ "movsbl $dst, $mem\t# byte" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Load Byte (8 bit signed) into long
0N/A// instruct loadB2L(rRegL dst, memory mem)
0N/A// match(Set dst (ConvI2L (LoadB mem)));
0N/A// format %{ "movsbq $dst, $mem\t# byte -> long" %}
0N/A// opcode(0x0F, 0xBE);
0N/A// ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A// ins_pipe(ialu_reg_mem);
0N/A// Load Byte (8 bit UNsigned)
0N/Ainstruct loadUB(rRegI dst, memory mem, immI_255 bytemask)
0N/A match(Set dst (AndI (LoadB mem) bytemask));
0N/A format %{ "movzbl $dst, $mem\t# ubyte" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Load Byte (8 bit UNsigned) into long
0N/A// instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask)
0N/A// match(Set dst (ConvI2L (AndI (LoadB mem) bytemask)));
0N/A// format %{ "movzbl $dst, $mem\t# ubyte -> long" %}
0N/A// opcode(0x0F, 0xB6);
0N/A// ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A// ins_pipe(ialu_reg_mem);
0N/A// Load Short (16 bit signed)
0N/Ainstruct loadS(rRegI dst, memory mem)
0N/A match(Set dst (LoadS mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movswl $dst, $mem\t# short" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Load Short (16 bit signed) into long
0N/A// instruct loadS2L(rRegL dst, memory mem)
0N/A// match(Set dst (ConvI2L (LoadS mem)));
0N/A// ins_cost(125); // XXX
0N/A// format %{ "movswq $dst, $mem\t# short -> long" %}
0N/A// opcode(0x0F, 0xBF);
0N/A// ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A// ins_pipe(ialu_reg_mem);
0N/A// Load Char (16 bit UNsigned)
0N/Ainstruct loadC(rRegI dst, memory mem)
0N/A match(Set dst (LoadC mem));
0N/A format %{ "movzwl $dst, $mem\t# char" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Load Char (16 bit UNsigned) into long
0N/A// instruct loadC2L(rRegL dst, memory mem)
0N/A// match(Set dst (ConvI2L (LoadC mem)));
0N/A// format %{ "movzwl $dst, $mem\t# char -> long" %}
0N/A// opcode(0x0F, 0xB7);
0N/A// ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
0N/A// ins_pipe(ialu_reg_mem);
0N/Ainstruct loadI(rRegI dst, memory mem)
0N/A match(Set dst (LoadI mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movl $dst, $mem\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct loadL(rRegL dst, memory mem)
0N/A match(Set dst (LoadL mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $dst, $mem\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem); // XXX
0N/Ainstruct loadRange(rRegI dst, memory mem)
0N/A match(Set dst (LoadRange mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movl $dst, $mem\t# range" %}
0N/A ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct loadP(rRegP dst, memory mem)
0N/A match(Set dst (LoadP mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $dst, $mem\t# ptr" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem); // XXX
113N/A// Load Compressed Pointer
163N/Ainstruct loadN(rRegN dst, memory mem)
113N/A match(Set dst (LoadN mem));
113N/A format %{ "movl $dst, $mem\t# compressed ptr" %}
113N/A Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
113N/A Register dst = as_Register($dst$$reg);
113N/A ins_pipe(ialu_reg_mem); // XXX
0N/A// Load Klass Pointer
0N/Ainstruct loadKlass(rRegP dst, memory mem)
0N/A match(Set dst (LoadKlass mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $dst, $mem\t# class" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem); // XXX
164N/A// Load narrow Klass Pointer
164N/Ainstruct loadNKlass(rRegN dst, memory mem)
164N/A match(Set dst (LoadNKlass mem));
182N/A format %{ "movl $dst, $mem\t# compressed klass ptr" %}
113N/A Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
113N/A Register dst = as_Register($dst$$reg);
113N/A ins_pipe(ialu_reg_mem); // XXX
0N/Ainstruct loadF(regF dst, memory mem)
0N/A match(Set dst (LoadF mem));
0N/A ins_cost(145); // XXX
0N/A format %{ "movss $dst, $mem\t# float" %}
0N/A opcode(0xF3, 0x0F, 0x10);
0N/A ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct loadD_partial(regD dst, memory mem)
0N/A predicate(!UseXmmLoadAndClearUpper);
0N/A match(Set dst (LoadD mem));
0N/A ins_cost(145); // XXX
0N/A format %{ "movlpd $dst, $mem\t# double" %}
0N/A opcode(0x66, 0x0F, 0x12);
0N/A ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct loadD(regD dst, memory mem)
0N/A predicate(UseXmmLoadAndClearUpper);
0N/A match(Set dst (LoadD mem));
0N/A ins_cost(145); // XXX
0N/A format %{ "movsd $dst, $mem\t# double" %}
0N/A opcode(0xF2, 0x0F, 0x10);
0N/A ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Load Aligned Packed Byte to XMM register
0N/Ainstruct loadA8B(regD dst, memory mem) %{
0N/A match(Set dst (Load8B mem));
0N/A format %{ "MOVQ $dst,$mem\t! packed8B" %}
0N/A ins_encode( movq_ld(dst, mem));
0N/A ins_pipe( pipe_slow );
0N/A// Load Aligned Packed Short to XMM register
0N/Ainstruct loadA4S(regD dst, memory mem) %{
0N/A match(Set dst (Load4S mem));
0N/A format %{ "MOVQ $dst,$mem\t! packed4S" %}
0N/A ins_encode( movq_ld(dst, mem));
0N/A ins_pipe( pipe_slow );
0N/A// Load Aligned Packed Char to XMM register
0N/Ainstruct loadA4C(regD dst, memory mem) %{
0N/A match(Set dst (Load4C mem));
0N/A format %{ "MOVQ $dst,$mem\t! packed4C" %}
0N/A ins_encode( movq_ld(dst, mem));
0N/A ins_pipe( pipe_slow );
0N/A// Load Aligned Packed Integer to XMM register
0N/Ainstruct load2IU(regD dst, memory mem) %{
0N/A match(Set dst (Load2I mem));
0N/A format %{ "MOVQ $dst,$mem\t! packed2I" %}
0N/A ins_encode( movq_ld(dst, mem));
0N/A ins_pipe( pipe_slow );
0N/A// Load Aligned Packed Single to XMM
0N/Ainstruct loadA2F(regD dst, memory mem) %{
0N/A match(Set dst (Load2F mem));
0N/A format %{ "MOVQ $dst,$mem\t! packed2F" %}
0N/A ins_encode( movq_ld(dst, mem));
0N/A ins_pipe( pipe_slow );
0N/A// Load Effective Address
0N/Ainstruct leaP8(rRegP dst, indOffset8 mem)
0N/A ins_cost(110); // XXX
0N/A format %{ "leaq $dst, $mem\t# ptr 8" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_reg_fat);
0N/Ainstruct leaP32(rRegP dst, indOffset32 mem)
0N/A format %{ "leaq $dst, $mem\t# ptr 32" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_reg_fat);
0N/A// instruct leaPIdx(rRegP dst, indIndex mem)
0N/A// match(Set dst mem);
0N/A// format %{ "leaq $dst, $mem\t# ptr idx" %}
0N/A// ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A// ins_pipe(ialu_reg_reg_fat);
0N/Ainstruct leaPIdxOff(rRegP dst, indIndexOffset mem)
0N/A format %{ "leaq $dst, $mem\t# ptr idxoff" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_reg_fat);
0N/Ainstruct leaPIdxScale(rRegP dst, indIndexScale mem)
0N/A format %{ "leaq $dst, $mem\t# ptr idxscale" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_reg_fat);
0N/Ainstruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
0N/A format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_reg_fat);
0N/Ainstruct loadConI(rRegI dst, immI src)
0N/A format %{ "movl $dst, $src\t# int" %}
0N/A ins_encode(load_immI(dst, src));
0N/A ins_pipe(ialu_reg_fat); // XXX
0N/Ainstruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
0N/A format %{ "xorl $dst, $dst\t# int" %}
0N/A opcode(0x33); /* + rd */
0N/A ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
0N/Ainstruct loadConL(rRegL dst, immL src)
0N/A format %{ "movq $dst, $src\t# long" %}
0N/A ins_encode(load_immL(dst, src));
0N/Ainstruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
0N/A format %{ "xorl $dst, $dst\t# long" %}
0N/A opcode(0x33); /* + rd */
0N/A ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
0N/A ins_pipe(ialu_reg); // XXX
0N/Ainstruct loadConUL32(rRegL dst, immUL32 src)
0N/A format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
0N/A ins_encode(load_immUL32(dst, src));
0N/Ainstruct loadConL32(rRegL dst, immL32 src)
0N/A format %{ "movq $dst, $src\t# long (32-bit)" %}
0N/A ins_encode(load_immL32(dst, src));
0N/Ainstruct loadConP(rRegP dst, immP src)
0N/A format %{ "movq $dst, $src\t# ptr" %}
0N/A ins_encode(load_immP(dst, src));
0N/A ins_pipe(ialu_reg_fat); // XXX
0N/Ainstruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
0N/A format %{ "xorl $dst, $dst\t# ptr" %}
0N/A opcode(0x33); /* + rd */
0N/A ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
0N/Ainstruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
0N/A format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
0N/A ins_encode(load_immP31(dst, src));
0N/Ainstruct loadConF(regF dst, immF src)
0N/A format %{ "movss $dst, [$src]" %}
0N/A ins_encode(load_conF(dst, src));
0N/A ins_pipe(pipe_slow);
113N/Ainstruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
124N/A format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
113N/A Register dst = $dst$$Register;
164N/Ainstruct loadConN(rRegN dst, immN src) %{
164N/A format %{ "movl $dst, $src\t# compressed ptr" %}
113N/A address con = (address)$src$$constant;
113N/A Register dst = $dst$$Register;
164N/A __ set_narrow_oop(dst, (jobject)$src$$constant);
113N/A ins_pipe(ialu_reg_fat); // XXX
0N/Ainstruct loadConF0(regF dst, immF0 src)
0N/A format %{ "xorps $dst, $dst\t# float 0.0" %}
0N/A ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
0N/A ins_pipe(pipe_slow);
0N/A// Use the same format since predicate() can not be used here.
0N/Ainstruct loadConD(regD dst, immD src)
0N/A format %{ "movsd $dst, [$src]" %}
0N/A ins_encode(load_conD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct loadConD0(regD dst, immD0 src)
0N/A format %{ "xorpd $dst, $dst\t# double 0.0" %}
0N/A opcode(0x66, 0x0F, 0x57);
0N/A ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct loadSSI(rRegI dst, stackSlotI src)
0N/A format %{ "movl $dst, $src\t# int stk" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct loadSSL(rRegL dst, stackSlotL src)
0N/A format %{ "movq $dst, $src\t# long stk" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct loadSSP(rRegP dst, stackSlotP src)
0N/A format %{ "movq $dst, $src\t# ptr stk" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct loadSSF(regF dst, stackSlotF src)
0N/A format %{ "movss $dst, $src\t# float stk" %}
0N/A opcode(0xF3, 0x0F, 0x10);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Use the same format since predicate() can not be used here.
0N/Ainstruct loadSSD(regD dst, stackSlotD src)
0N/A format %{ "movsd $dst, $src\t# double stk" %}
0N/A __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Prefetch instructions.
0N/A// Must be safe to execute with invalid address (cannot fault).
0N/Ainstruct prefetchr( memory mem ) %{
0N/A predicate(ReadPrefetchInstr==3);
0N/A match(PrefetchRead mem);
0N/A format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
0N/A opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
0N/Ainstruct prefetchrNTA( memory mem ) %{
0N/A predicate(ReadPrefetchInstr==0);
0N/A match(PrefetchRead mem);
0N/A format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
0N/Ainstruct prefetchrT0( memory mem ) %{
0N/A predicate(ReadPrefetchInstr==1);
0N/A match(PrefetchRead mem);
0N/A format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
0N/Ainstruct prefetchrT2( memory mem ) %{
0N/A predicate(ReadPrefetchInstr==2);
0N/A match(PrefetchRead mem);
0N/A format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
0N/Ainstruct prefetchw( memory mem ) %{
0N/A predicate(AllocatePrefetchInstr==3);
0N/A match(PrefetchWrite mem);
0N/A format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
0N/A opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
0N/Ainstruct prefetchwNTA( memory mem ) %{
0N/A predicate(AllocatePrefetchInstr==0);
0N/A match(PrefetchWrite mem);
0N/A format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
0N/Ainstruct prefetchwT0( memory mem ) %{
0N/A predicate(AllocatePrefetchInstr==1);
0N/A match(PrefetchWrite mem);
0N/A format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
0N/Ainstruct prefetchwT2( memory mem ) %{
0N/A predicate(AllocatePrefetchInstr==2);
0N/A match(PrefetchWrite mem);
0N/A format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
0N/A opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
0N/A ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
0N/A//----------Store Instructions-------------------------------------------------
0N/Ainstruct storeB(memory mem, rRegI src)
0N/A match(Set mem (StoreB mem src));
0N/A ins_cost(125); // XXX
0N/A format %{ "movb $mem, $src\t# byte" %}
0N/A ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct storeC(memory mem, rRegI src)
0N/A match(Set mem (StoreC mem src));
0N/A ins_cost(125); // XXX
0N/A ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct storeI(memory mem, rRegI src)
0N/A match(Set mem (StoreI mem src));
0N/A ins_cost(125); // XXX
0N/A format %{ "movl $mem, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct storeL(memory mem, rRegL src)
0N/A match(Set mem (StoreL mem src));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $mem, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_mem_reg); // XXX
0N/Ainstruct storeP(memory mem, any_RegP src)
0N/A match(Set mem (StoreP mem src));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $mem, $src\t# ptr" %}
0N/A ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Store NULL Pointer, mark word, or other simple pointer constant.
0N/Ainstruct storeImmP(memory mem, immP31 src)
0N/A match(Set mem (StoreP mem src));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $mem, $src\t# ptr" %}
0N/A opcode(0xC7); /* C7 /0 */
0N/A ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
0N/A ins_pipe(ialu_mem_imm);
113N/A// Store Compressed Pointer
163N/Ainstruct storeN(memory mem, rRegN src)
113N/A match(Set mem (StoreN mem src));
164N/A format %{ "movl $mem, $src\t# compressed ptr" %}
113N/A Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
113N/A Register src = as_Register($src$$reg);
113N/A ins_pipe(ialu_mem_reg);
0N/A// Store Integer Immediate
0N/Ainstruct storeImmI(memory mem, immI src)
0N/A match(Set mem (StoreI mem src));
0N/A format %{ "movl $mem, $src\t# int" %}
0N/A opcode(0xC7); /* C7 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Store Long Immediate
0N/Ainstruct storeImmL(memory mem, immL32 src)
0N/A match(Set mem (StoreL mem src));
0N/A format %{ "movq $mem, $src\t# long" %}
0N/A opcode(0xC7); /* C7 /0 */
0N/A ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct storeImmI16(memory mem, immI16 src)
0N/A predicate(UseStoreImmI16);
0N/A match(Set mem (StoreC mem src));
0N/A opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
0N/A ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Store Byte Immediate
0N/Ainstruct storeImmB(memory mem, immI8 src)
0N/A match(Set mem (StoreB mem src));
0N/A ins_cost(150); // XXX
0N/A format %{ "movb $mem, $src\t# byte" %}
0N/A opcode(0xC6); /* C6 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Store Aligned Packed Byte XMM register to memory
0N/Ainstruct storeA8B(memory mem, regD src) %{
0N/A match(Set mem (Store8B mem src));
0N/A format %{ "MOVQ $mem,$src\t! packed8B" %}
0N/A ins_encode( movq_st(mem, src));
0N/A ins_pipe( pipe_slow );
0N/Ainstruct storeA4C(memory mem, regD src) %{
0N/A match(Set mem (Store4C mem src));
0N/A format %{ "MOVQ $mem,$src\t! packed4C" %}
0N/A ins_encode( movq_st(mem, src));
0N/A ins_pipe( pipe_slow );
0N/A// Store Aligned Packed Integer XMM register to memory
0N/Ainstruct storeA2I(memory mem, regD src) %{
0N/A match(Set mem (Store2I mem src));
0N/A format %{ "MOVQ $mem,$src\t! packed2I" %}
0N/A ins_encode( movq_st(mem, src));
0N/A ins_pipe( pipe_slow );
0N/A// Store CMS card-mark Immediate
0N/Ainstruct storeImmCM0(memory mem, immI0 src)
0N/A match(Set mem (StoreCM mem src));
0N/A ins_cost(150); // XXX
0N/A format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
0N/A opcode(0xC6); /* C6 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Store Aligned Packed Single Float XMM register to memory
0N/Ainstruct storeA2F(memory mem, regD src) %{
0N/A match(Set mem (Store2F mem src));
0N/A format %{ "MOVQ $mem,$src\t! packed2F" %}
0N/A ins_encode( movq_st(mem, src));
0N/A ins_pipe( pipe_slow );
0N/Ainstruct storeF(memory mem, regF src)
0N/A match(Set mem (StoreF mem src));
0N/A ins_cost(95); // XXX
0N/A format %{ "movss $mem, $src\t# float" %}
0N/A opcode(0xF3, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Store immediate Float value (it is faster than store from XMM register)
0N/Ainstruct storeF_imm(memory mem, immF src)
0N/A match(Set mem (StoreF mem src));
0N/A format %{ "movl $mem, $src\t# float" %}
0N/A opcode(0xC7); /* C7 /0 */
0N/A ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct storeD(memory mem, regD src)
0N/A match(Set mem (StoreD mem src));
0N/A ins_cost(95); // XXX
0N/A format %{ "movsd $mem, $src\t# double" %}
0N/A opcode(0xF2, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Store immediate double 0.0 (it is faster than store from XMM register)
0N/Ainstruct storeD0_imm(memory mem, immD0 src)
0N/A match(Set mem (StoreD mem src));
0N/A format %{ "movq $mem, $src\t# double 0." %}
0N/A opcode(0xC7); /* C7 /0 */
0N/A ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct storeSSI(stackSlotI dst, rRegI src)
0N/A format %{ "movl $dst, $src\t# int stk" %}
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe( ialu_mem_reg );
0N/Ainstruct storeSSL(stackSlotL dst, rRegL src)
0N/A format %{ "movq $dst, $src\t# long stk" %}
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct storeSSP(stackSlotP dst, rRegP src)
0N/A format %{ "movq $dst, $src\t# ptr stk" %}
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct storeSSF(stackSlotF dst, regF src)
0N/A ins_cost(95); // XXX
0N/A format %{ "movss $dst, $src\t# float stk" %}
0N/A opcode(0xF3, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct storeSSD(stackSlotD dst, regD src)
0N/A ins_cost(95); // XXX
0N/A format %{ "movsd $dst, $src\t# double stk" %}
0N/A opcode(0xF2, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
0N/A ins_pipe(pipe_slow); // XXX
0N/A//----------BSWAP Instructions-------------------------------------------------
0N/Ainstruct bytes_reverse_int(rRegI dst) %{
0N/A match(Set dst (ReverseBytesI dst));
0N/A format %{ "bswapl $dst" %}
0N/A opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
0N/A ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
0N/A ins_pipe( ialu_reg );
0N/Ainstruct bytes_reverse_long(rRegL dst) %{
0N/A match(Set dst (ReverseBytesL dst));
0N/A format %{ "bswapq $dst" %}
0N/A opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
0N/A ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
0N/A ins_pipe( ialu_reg);
0N/Ainstruct loadI_reversed(rRegI dst, memory src) %{
0N/A match(Set dst (ReverseBytesI (LoadI src)));
0N/A format %{ "bswap_movl $dst, $src" %}
0N/A opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
0N/A ins_pipe( ialu_reg_mem );
0N/Ainstruct loadL_reversed(rRegL dst, memory src) %{
0N/A match(Set dst (ReverseBytesL (LoadL src)));
0N/A format %{ "bswap_movq $dst, $src" %}
0N/A opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
0N/A ins_pipe( ialu_reg_mem );
0N/Ainstruct storeI_reversed(memory dst, rRegI src) %{
0N/A match(Set dst (StoreI dst (ReverseBytesI src)));
0N/A format %{ "movl_bswap $dst, $src" %}
0N/A opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
0N/A ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
0N/A ins_pipe( ialu_mem_reg );
0N/Ainstruct storeL_reversed(memory dst, rRegL src) %{
0N/A match(Set dst (StoreL dst (ReverseBytesL src)));
0N/A format %{ "movq_bswap $dst, $src" %}
0N/A opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
0N/A ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
0N/A ins_pipe( ialu_mem_reg );
0N/A//----------MemBar Instructions-----------------------------------------------
0N/A// Memory barrier flavors
0N/Ainstruct membar_acquire()
0N/A match(MemBarAcquire);
0N/A format %{ "MEMBAR-acquire" %}
0N/Ainstruct membar_acquire_lock()
0N/A match(MemBarAcquire);
0N/A predicate(Matcher::prior_fast_lock(n));
0N/A format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
0N/Ainstruct membar_release()
0N/A match(MemBarRelease);
0N/A format %{ "MEMBAR-release" %}
0N/Ainstruct membar_release_lock()
0N/A match(MemBarRelease);
0N/A predicate(Matcher::post_fast_unlock(n));
0N/A format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
0N/Ainstruct membar_volatile()
0N/A match(MemBarVolatile);
0N/A format %{ "MEMBAR-volatile" %}
0N/A ins_encode(enc_membar_volatile);
0N/A ins_pipe(pipe_slow);
0N/Ainstruct unnecessary_membar_volatile()
0N/A match(MemBarVolatile);
0N/A predicate(Matcher::post_store_load_barrier(n));
0N/A format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
0N/A//----------Move Instructions--------------------------------------------------
0N/Ainstruct castX2P(rRegP dst, rRegL src)
0N/A match(Set dst (CastX2P src));
0N/A format %{ "movq $dst, $src\t# long->ptr" %}
0N/A ins_encode(enc_copy_wide(dst, src));
0N/A ins_pipe(ialu_reg_reg); // XXX
0N/Ainstruct castP2X(rRegL dst, rRegP src)
0N/A match(Set dst (CastP2X src));
0N/A format %{ "movq $dst, $src\t# ptr -> long" %}
0N/A ins_encode(enc_copy_wide(dst, src));
0N/A ins_pipe(ialu_reg_reg); // XXX
113N/A// Convert oop pointer into compressed form
113N/Ainstruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
221N/A predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113N/A match(Set dst (EncodeP src));
113N/A format %{ "encode_heap_oop $dst,$src" %}
113N/A Register s = $src$$Register;
113N/A Register d = $dst$$Register;
113N/A ins_pipe(ialu_reg_long);
124N/Ainstruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
221N/A predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124N/A match(Set dst (EncodeP src));
124N/A format %{ "encode_heap_oop_not_null $dst,$src" %}
124N/A Register s = $src$$Register;
124N/A Register d = $dst$$Register;
124N/A __ encode_heap_oop_not_null(d, s);
124N/A ins_pipe(ialu_reg_long);
113N/Ainstruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
182N/A predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
182N/A n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
113N/A match(Set dst (DecodeN src));
113N/A format %{ "decode_heap_oop $dst,$src" %}
113N/A Register s = $src$$Register;
113N/A Register d = $dst$$Register;
113N/A ins_pipe(ialu_reg_long);
124N/Ainstruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
182N/A predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
182N/A n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
124N/A match(Set dst (DecodeN src));
124N/A format %{ "decode_heap_oop_not_null $dst,$src" %}
124N/A Register s = $src$$Register;
124N/A Register d = $dst$$Register;
124N/A __ decode_heap_oop_not_null(d, s);
124N/A ins_pipe(ialu_reg_long);
0N/A//----------Conditional Move---------------------------------------------------
0N/A// dummy instruction for generating temp registers
0N/Ainstruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
0N/A match(Jump (LShiftL switch_val shift));
0N/A format %{ "leaq $dest, table_base\n\t"
0N/A "jmp [$dest + $switch_val << $shift]\n\t" %}
0N/A ins_encode(jump_enc_offset(switch_val, shift, dest));
0N/Ainstruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
0N/A match(Jump (AddL (LShiftL switch_val shift) offset));
0N/A format %{ "leaq $dest, table_base\n\t"
0N/A "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
0N/A ins_encode(jump_enc_addr(switch_val, shift, offset, dest));
0N/Ainstruct jumpXtnd(rRegL switch_val, rRegI dest) %{
0N/A match(Jump switch_val);
0N/A format %{ "leaq $dest, table_base\n\t"
0N/A "jmp [$dest + $switch_val]\n\t" %}
0N/A ins_encode(jump_enc(switch_val, dest));
0N/Ainstruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
0N/A match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovl$cop $dst, $src\t# signed, int" %}
0N/A ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg);
0N/Ainstruct cmovI_regU(rRegI dst, rRegI src, rFlagsRegU cr, cmpOpU cop)
0N/A match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
0N/A ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg);
0N/Ainstruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src)
0N/A match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
0N/A ins_cost(250); // XXX
0N/A format %{ "cmovl$cop $dst, $src\t# signed, int" %}
0N/A ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
0N/A ins_pipe(pipe_cmov_mem);
0N/Ainstruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
0N/A match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
0N/A ins_cost(250); // XXX
0N/A format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
0N/A ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
0N/A ins_pipe(pipe_cmov_mem);
164N/Ainstruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
164N/A match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
164N/A format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
164N/A ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
164N/A ins_pipe(pipe_cmov_reg);
164N/Ainstruct cmovN_regU(rRegN dst, rRegN src, rFlagsRegU cr, cmpOpU cop)
164N/A match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
164N/A format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
164N/A ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
164N/A ins_pipe(pipe_cmov_reg);
0N/Ainstruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
0N/A match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg); // XXX
0N/Ainstruct cmovP_regU(rRegP dst, rRegP src, rFlagsRegU cr, cmpOpU cop)
0N/A match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg); // XXX
0N/A// DISABLED: Requires the ADLC to emit a bottom_type call that
0N/A// correctly meets the two pointer arguments; one is an incoming
0N/A// register but the other is a memory operand. ALSO appears to
0N/A// be buggy with implicit null checks.
0N/A//// Conditional move
0N/A//instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
0N/A// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
0N/A// format %{ "CMOV$cop $dst,$src\t# ptr" %}
0N/A// opcode(0x0F,0x40);
0N/A// ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
0N/A// ins_pipe( pipe_cmov_mem );
0N/A//// Conditional move
0N/A//instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
0N/A// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
0N/A// format %{ "CMOV$cop $dst,$src\t# ptr" %}
0N/A// opcode(0x0F,0x40);
0N/A// ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
0N/A// ins_pipe( pipe_cmov_mem );
0N/Ainstruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
0N/A match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# signed, long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg); // XXX
0N/Ainstruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
0N/A match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# signed, long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
0N/A ins_pipe(pipe_cmov_mem); // XXX
0N/Ainstruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
0N/A match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg); // XXX
0N/Ainstruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
0N/A match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
0N/A ins_cost(200); // XXX
0N/A format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
0N/A ins_pipe(pipe_cmov_mem); // XXX
0N/Ainstruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
0N/A match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "jn$cop skip\t# signed cmove float\n\t"
0N/A "movss $dst, $src\n"
0N/A ins_encode(enc_cmovf_branch(cop, dst, src));
0N/A ins_pipe(pipe_slow);
0N/A// instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
0N/A// match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
0N/A// ins_cost(200); // XXX
0N/A// format %{ "jn$cop skip\t# signed cmove float\n\t"
0N/A// "movss $dst, $src\n"
0N/A// ins_encode(enc_cmovf_mem_branch(cop, dst, src));
0N/A// ins_pipe(pipe_slow);
0N/Ainstruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
0N/A match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "jn$cop skip\t# unsigned cmove float\n\t"
0N/A "movss $dst, $src\n"
0N/A ins_encode(enc_cmovf_branch(cop, dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
0N/A match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "jn$cop skip\t# signed cmove double\n\t"
0N/A "movsd $dst, $src\n"
0N/A ins_encode(enc_cmovd_branch(cop, dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
0N/A match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
0N/A ins_cost(200); // XXX
0N/A format %{ "jn$cop skip\t# unsigned cmove double\n\t"
0N/A "movsd $dst, $src\n"
0N/A ins_encode(enc_cmovd_branch(cop, dst, src));
0N/A ins_pipe(pipe_slow);
0N/A//----------Arithmetic Instructions--------------------------------------------
0N/A//----------Addition Instructions----------------------------------------------
0N/Ainstruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (AddI dst src));
0N/A format %{ "addl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
0N/A match(Set dst (AddI dst src));
0N/A format %{ "addl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x00); /* /0 id */
0N/A ins_encode(OpcSErm(dst, src), Con8or32(src));
0N/A ins_pipe( ialu_reg );
0N/Ainstruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (AddI dst (LoadI src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "addl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (AddI (LoadI dst) src)));
0N/A ins_cost(150); // XXX
0N/A format %{ "addl $dst, $src\t# int" %}
0N/A opcode(0x01); /* Opcode 01 /r */
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (AddI (LoadI dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "addl $dst, $src\t# int" %}
0N/A opcode(0x81); /* Opcode 81 /0 id */
0N/A ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (AddI dst src));
0N/A format %{ "incl $dst\t# int" %}
0N/A opcode(0xFF, 0x00); // FF /0
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/Ainstruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (StoreI dst (AddI (LoadI dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "incl $dst\t# int" %}
0N/A opcode(0xFF); /* Opcode FF /0 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// XXX why does that use AddI
0N/Ainstruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (AddI dst src));
0N/A format %{ "decl $dst\t# int" %}
0N/A opcode(0xFF, 0x01); // FF /1
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A// XXX why does that use AddI
0N/Ainstruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (StoreI dst (AddI (LoadI dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "decl $dst\t# int" %}
0N/A opcode(0xFF); /* Opcode FF /1 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
0N/A match(Set dst (AddI src0 src1));
0N/A format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
0N/A opcode(0x8D); /* 0x8D /r */
0N/A ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (AddL dst src));
0N/A format %{ "addq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (AddL dst src));
0N/A format %{ "addq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x00); /* /0 id */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/A ins_pipe( ialu_reg );
0N/Ainstruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (AddL dst (LoadL src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "addq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (AddL (LoadL dst) src)));
0N/A ins_cost(150); // XXX
0N/A format %{ "addq $dst, $src\t# long" %}
0N/A opcode(0x01); /* Opcode 01 /r */
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (AddL (LoadL dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "addq $dst, $src\t# long" %}
0N/A opcode(0x81); /* Opcode 81 /0 id */
0N/A ins_encode(REX_mem_wide(dst),
0N/A OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (AddL dst src));
0N/A format %{ "incq $dst\t# long" %}
0N/A opcode(0xFF, 0x00); // FF /0
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/Ainstruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (StoreL dst (AddL (LoadL dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "incq $dst\t# long" %}
0N/A opcode(0xFF); /* Opcode FF /0 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// XXX why does that use AddL
0N/Ainstruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (AddL dst src));
0N/A format %{ "decq $dst\t# long" %}
0N/A opcode(0xFF, 0x01); // FF /1
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A// XXX why does that use AddL
0N/Ainstruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
0N/A predicate(UseIncDec);
0N/A match(Set dst (StoreL dst (AddL (LoadL dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "decq $dst\t# long" %}
0N/A opcode(0xFF); /* Opcode FF /1 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
0N/A match(Set dst (AddL src0 src1));
0N/A format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
0N/A opcode(0x8D); /* 0x8D /r */
0N/A ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (AddP dst src));
0N/A format %{ "addq $dst, $src\t# ptr" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (AddP dst src));
0N/A format %{ "addq $dst, $src\t# ptr" %}
0N/A opcode(0x81, 0x00); /* /0 id */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/A ins_pipe( ialu_reg );
0N/A// XXX addP mem ops ????
0N/Ainstruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
0N/A match(Set dst (AddP src0 src1));
0N/A format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
0N/A opcode(0x8D); /* 0x8D /r */
0N/A ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct checkCastPP(rRegP dst)
0N/A match(Set dst (CheckCastPP dst));
0N/A format %{ "# checkcastPP of $dst" %}
0N/A ins_encode(/* empty encoding */);
0N/Ainstruct castPP(rRegP dst)
0N/A match(Set dst (CastPP dst));
0N/A format %{ "# castPP of $dst" %}
0N/A ins_encode(/* empty encoding */);
0N/Ainstruct castII(rRegI dst)
0N/A match(Set dst (CastII dst));
0N/A format %{ "# castII of $dst" %}
0N/A ins_encode(/* empty encoding */);
0N/A// LoadP-locked same as a regular LoadP when used with compare-swap
0N/Ainstruct loadPLocked(rRegP dst, memory mem)
0N/A match(Set dst (LoadPLocked mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $dst, $mem\t# ptr locked" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem); // XXX
0N/A// LoadL-locked - same as a regular LoadL when used with compare-swap
0N/Ainstruct loadLLocked(rRegL dst, memory mem)
0N/A match(Set dst (LoadLLocked mem));
0N/A ins_cost(125); // XXX
0N/A format %{ "movq $dst, $mem\t# long locked" %}
0N/A ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
0N/A ins_pipe(ialu_reg_mem); // XXX
0N/A// Conditional-store of the updated heap-top.
0N/A// Used during allocation of the shared heap.
0N/A// Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
0N/Ainstruct storePConditional(memory heap_top_ptr,
0N/A rax_RegP oldval, rRegP newval,
0N/A match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
0N/A format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
0N/A "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem_wide(newval, heap_top_ptr),
0N/A reg_mem(newval, heap_top_ptr));
0N/A ins_pipe(pipe_cmpxchg);
0N/A// Conditional-store of a long value
0N/A// Returns a boolean value (0/1) on success. Implemented with a
0N/A// CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
0N/Ainstruct storeLConditional(rRegI res,
0N/A rax_RegL oldval, rRegL newval,
0N/A match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
0N/A format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
0N/A "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
0N/A "movzbl $res, $res" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem_wide(newval, mem_ptr),
0N/A reg_mem(newval, mem_ptr),
0N/A REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
0N/A REX_reg_breg(res, res), // movzbl
0N/A Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
0N/A ins_pipe(pipe_cmpxchg);
0N/A// Conditional-store of a long value
0N/A// ZF flag is set on success, reset otherwise. Implemented with a
0N/A// CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
0N/Ainstruct storeLConditional_flags(memory mem_ptr,
0N/A rax_RegL oldval, rRegL newval,
0N/A match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
0N/A format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
0N/A "If rax == $mem_ptr then store $newval into $mem_ptr" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem_wide(newval, mem_ptr),
0N/A reg_mem(newval, mem_ptr));
0N/A ins_pipe(pipe_cmpxchg);
0N/Ainstruct compareAndSwapP(rRegI res,
0N/A rax_RegP oldval, rRegP newval,
0N/A match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
0N/A effect(KILL cr, KILL oldval);
0N/A format %{ "cmpxchgq $mem_ptr,$newval\t# "
0N/A "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
0N/A "movzbl $res, $res" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem_wide(newval, mem_ptr),
0N/A reg_mem(newval, mem_ptr),
0N/A REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
0N/A REX_reg_breg(res, res), // movzbl
0N/A Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
0N/A ins_pipe( pipe_cmpxchg );
0N/A// XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
0N/Ainstruct compareAndSwapL(rRegI res,
0N/A rax_RegL oldval, rRegL newval,
0N/A match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
0N/A effect(KILL cr, KILL oldval);
0N/A format %{ "cmpxchgq $mem_ptr,$newval\t# "
0N/A "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
0N/A "movzbl $res, $res" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem_wide(newval, mem_ptr),
0N/A reg_mem(newval, mem_ptr),
0N/A REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
0N/A REX_reg_breg(res, res), // movzbl
0N/A Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
0N/A ins_pipe( pipe_cmpxchg );
0N/Ainstruct compareAndSwapI(rRegI res,
0N/A rax_RegI oldval, rRegI newval,
0N/A match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
0N/A effect(KILL cr, KILL oldval);
0N/A format %{ "cmpxchgl $mem_ptr,$newval\t# "
0N/A "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
0N/A "movzbl $res, $res" %}
0N/A ins_encode(lock_prefix,
0N/A REX_reg_mem(newval, mem_ptr),
0N/A reg_mem(newval, mem_ptr),
0N/A REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
0N/A REX_reg_breg(res, res), // movzbl
0N/A Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
0N/A ins_pipe( pipe_cmpxchg );
113N/Ainstruct compareAndSwapN(rRegI res,
113N/A rax_RegN oldval, rRegN newval,
113N/A match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
113N/A effect(KILL cr, KILL oldval);
113N/A format %{ "cmpxchgl $mem_ptr,$newval\t# "
113N/A "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
113N/A ins_encode(lock_prefix,
113N/A REX_reg_mem(newval, mem_ptr),
113N/A reg_mem(newval, mem_ptr),
113N/A REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
113N/A REX_reg_breg(res, res), // movzbl
113N/A Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
113N/A ins_pipe( pipe_cmpxchg );
0N/A//----------Subtraction Instructions-------------------------------------------
0N/A// Integer Subtraction Instructions
0N/Ainstruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (SubI dst src));
0N/A format %{ "subl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
0N/A match(Set dst (SubI dst src));
0N/A format %{ "subl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x05); /* Opcode 81 /5 */
0N/A ins_encode(OpcSErm(dst, src), Con8or32(src));
0N/Ainstruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (SubI dst (LoadI src)));
0N/A format %{ "subl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (SubI (LoadI dst) src)));
0N/A format %{ "subl $dst, $src\t# int" %}
0N/A opcode(0x29); /* Opcode 29 /r */
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (SubI (LoadI dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "subl $dst, $src\t# int" %}
0N/A opcode(0x81); /* Opcode 81 /5 id */
0N/A ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/Ainstruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (SubL dst src));
0N/A format %{ "subq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (SubL dst src));
0N/A format %{ "subq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x05); /* Opcode 81 /5 */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/Ainstruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (SubL dst (LoadL src)));
0N/A format %{ "subq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (SubL (LoadL dst) src)));
0N/A format %{ "subq $dst, $src\t# long" %}
0N/A opcode(0x29); /* Opcode 29 /r */
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (SubL (LoadL dst) src)));
0N/A ins_cost(125); // XXX
0N/A format %{ "subq $dst, $src\t# long" %}
0N/A opcode(0x81); /* Opcode 81 /5 id */
0N/A ins_encode(REX_mem_wide(dst),
0N/A OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Subtract from a pointer
0N/Ainstruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (AddP dst (SubI zero src)));
0N/A format %{ "subq $dst, $src\t# ptr - int" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (SubI zero dst));
0N/A format %{ "negl $dst\t# int" %}
0N/A opcode(0xF7, 0x03); // Opcode F7 /3
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/Ainstruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (SubI zero (LoadI dst))));
0N/A format %{ "negl $dst\t# int" %}
0N/A opcode(0xF7, 0x03); // Opcode F7 /3
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/Ainstruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
0N/A match(Set dst (SubL zero dst));
0N/A format %{ "negq $dst\t# long" %}
0N/A opcode(0xF7, 0x03); // Opcode F7 /3
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/Ainstruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (SubL zero (LoadL dst))));
0N/A format %{ "negq $dst\t# long" %}
0N/A opcode(0xF7, 0x03); // Opcode F7 /3
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A//----------Multiplication/Division Instructions-------------------------------
0N/A// Integer Multiplication Instructions
0N/Ainstruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (MulI dst src));
0N/A format %{ "imull $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
0N/A match(Set dst (MulI src imm));
0N/A format %{ "imull $dst, $src, $imm\t# int" %}
0N/A opcode(0x69); /* 69 /r id */
0N/A ins_encode(REX_reg_reg(dst, src),
0N/A OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (MulI dst (LoadI src)));
0N/A format %{ "imull $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem_alu0);
0N/Ainstruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
0N/A match(Set dst (MulI (LoadI src) imm));
0N/A format %{ "imull $dst, $src, $imm\t# int" %}
0N/A opcode(0x69); /* 69 /r id */
0N/A ins_encode(REX_reg_mem(dst, src),
0N/A OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
0N/A ins_pipe(ialu_reg_mem_alu0);
0N/Ainstruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (MulL dst src));
0N/A format %{ "imulq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
0N/A match(Set dst (MulL src imm));
0N/A format %{ "imulq $dst, $src, $imm\t# long" %}
0N/A opcode(0x69); /* 69 /r id */
0N/A ins_encode(REX_reg_reg_wide(dst, src),
0N/A OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (MulL dst (LoadL src)));
0N/A format %{ "imulq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem_alu0);
0N/Ainstruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
0N/A match(Set dst (MulL (LoadL src) imm));
0N/A format %{ "imulq $dst, $src, $imm\t# long" %}
0N/A opcode(0x69); /* 69 /r id */
0N/A ins_encode(REX_reg_mem_wide(dst, src),
0N/A OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
0N/A ins_pipe(ialu_reg_mem_alu0);
145N/Ainstruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
145N/A match(Set dst (MulHiL src rax));
145N/A effect(USE_KILL rax, KILL cr);
145N/A format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
145N/A opcode(0xF7, 0x5); /* Opcode F7 /5 */
145N/A ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
145N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
0N/A match(Set rax (DivI rax div));
0N/A effect(KILL rdx, KILL cr);
0N/A ins_cost(30*100+10*100); // XXX
0N/A format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
0N/A match(Set rax (DivL rax div));
0N/A effect(KILL rdx, KILL cr);
0N/A ins_cost(30*100+10*100); // XXX
0N/A format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/A// Integer DIVMOD with Register, both quotient and mod results
0N/Ainstruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
0N/A match(DivModI rax div);
0N/A ins_cost(30*100+10*100); // XXX
0N/A format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
0N/A ins_pipe(pipe_slow);
0N/A// Long DIVMOD with Register, both quotient and mod results
0N/Ainstruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
0N/A match(DivModL rax div);
0N/A ins_cost(30*100+10*100); // XXX
0N/A format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
0N/A ins_pipe(pipe_slow);
0N/A//----------- DivL-By-Constant-Expansions--------------------------------------
0N/A// DivI cases are handled by the compiler
0N/A// Magic constant, reciprical of 10
0N/Ainstruct loadConL_0x6666666666666667(rRegL dst)
0N/A format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
0N/A ins_encode(load_immL(dst, 0x6666666666666667));
0N/Ainstruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
0N/A effect(DEF dst, USE src, USE_KILL rax, KILL cr);
0N/A format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
0N/A opcode(0xF7, 0x5); /* Opcode F7 /5 */
0N/A ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
0N/A effect(USE_DEF dst, KILL cr);
0N/A format %{ "sarq $dst, #63\t# Used in div-by-10" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, 0x3F));
0N/Ainstruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
0N/A effect(USE_DEF dst, KILL cr);
0N/A format %{ "sarq $dst, #2\t# Used in div-by-10" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, 0x2));
0N/Ainstruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
0N/A match(Set dst (DivL src div));
0N/A ins_cost((5+8)*100);
0N/A rax_RegL rax; // Killed temp
0N/A rFlagsReg cr; // Killed
0N/A loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
0N/A mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
0N/A sarL_rReg_63(src, cr); // sarq src, 63
0N/A sarL_rReg_2(dst, cr); // sarq rdx, 2
0N/A subL_rReg(dst, src, cr); // subl rdx, src
0N/A//-----------------------------------------------------------------------------
0N/Ainstruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
0N/A match(Set rdx (ModI rax div));
0N/A effect(KILL rax, KILL cr);
0N/A ins_cost(300); // XXX
0N/A format %{ "cmpl rax, 0x80000000\t# irem\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/Ainstruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
0N/A match(Set rdx (ModL rax div));
0N/A effect(KILL rax, KILL cr);
0N/A ins_cost(300); // XXX
0N/A format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
0N/A opcode(0xF7, 0x7); /* Opcode F7 /7 */
0N/A ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
0N/A ins_pipe(ialu_reg_reg_alu0);
0N/A// Integer Shift Instructions
0N/Ainstruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (LShiftI dst shift));
0N/A format %{ "sall $dst, $shift" %}
0N/A opcode(0xD1, 0x4); /* D1 /4 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/Ainstruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
0N/A format %{ "sall $dst, $shift\t" %}
0N/A opcode(0xD1, 0x4); /* D1 /4 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Shift Left by 8-bit immediate
0N/Ainstruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (LShiftI dst shift));
0N/A format %{ "sall $dst, $shift" %}
0N/A opcode(0xC1, 0x4); /* C1 /4 ib */
0N/A ins_encode(reg_opc_imm(dst, shift));
0N/A// Shift Left by 8-bit immediate
0N/Ainstruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
0N/A format %{ "sall $dst, $shift" %}
0N/A opcode(0xC1, 0x4); /* C1 /4 ib */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Shift Left by variable
0N/Ainstruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (LShiftI dst shift));
0N/A format %{ "sall $dst, $shift" %}
0N/A opcode(0xD3, 0x4); /* D3 /4 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Shift Left by variable
0N/Ainstruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
0N/A format %{ "sall $dst, $shift" %}
0N/A opcode(0xD3, 0x4); /* D3 /4 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Arithmetic shift right by one
0N/Ainstruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (RShiftI dst shift));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xD1, 0x7); /* D1 /7 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A// Arithmetic shift right by one
0N/Ainstruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xD1, 0x7); /* D1 /7 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by 8-bit immediate
0N/Ainstruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (RShiftI dst shift));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(reg_opc_imm(dst, shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by 8-bit immediate
0N/Ainstruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by variable
0N/Ainstruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (RShiftI dst shift));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xD3, 0x7); /* D3 /7 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Arithmetic Shift Right by variable
0N/Ainstruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
0N/A format %{ "sarl $dst, $shift" %}
0N/A opcode(0xD3, 0x7); /* D3 /7 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Logical shift right by one
0N/Ainstruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (URShiftI dst shift));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xD1, 0x5); /* D1 /5 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A// Logical shift right by one
0N/Ainstruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xD1, 0x5); /* D1 /5 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Logical Shift Right by 8-bit immediate
0N/Ainstruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (URShiftI dst shift));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xC1, 0x5); /* C1 /5 ib */
0N/A ins_encode(reg_opc_imm(dst, shift));
0N/A// Logical Shift Right by 8-bit immediate
0N/Ainstruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xC1, 0x5); /* C1 /5 ib */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Logical Shift Right by variable
0N/Ainstruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (URShiftI dst shift));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xD3, 0x5); /* D3 /5 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Logical Shift Right by variable
0N/Ainstruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
0N/A format %{ "shrl $dst, $shift" %}
0N/A opcode(0xD3, 0x5); /* D3 /5 */
0N/A ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Long Shift Instructions
0N/Ainstruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (LShiftL dst shift));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xD1, 0x4); /* D1 /4 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/Ainstruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xD1, 0x4); /* D1 /4 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Shift Left by 8-bit immediate
0N/Ainstruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (LShiftL dst shift));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xC1, 0x4); /* C1 /4 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, shift));
0N/A// Shift Left by 8-bit immediate
0N/Ainstruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xC1, 0x4); /* C1 /4 ib */
0N/A ins_encode(REX_mem_wide(dst), OpcP,
0N/A RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Shift Left by variable
0N/Ainstruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (LShiftL dst shift));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xD3, 0x4); /* D3 /4 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Shift Left by variable
0N/Ainstruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
0N/A format %{ "salq $dst, $shift" %}
0N/A opcode(0xD3, 0x4); /* D3 /4 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Arithmetic shift right by one
0N/Ainstruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (RShiftL dst shift));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xD1, 0x7); /* D1 /7 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A// Arithmetic shift right by one
0N/Ainstruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xD1, 0x7); /* D1 /7 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by 8-bit immediate
0N/Ainstruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (RShiftL dst shift));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by 8-bit immediate
0N/Ainstruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(REX_mem_wide(dst), OpcP,
0N/A RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Arithmetic Shift Right by variable
0N/Ainstruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (RShiftL dst shift));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xD3, 0x7); /* D3 /7 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Arithmetic Shift Right by variable
0N/Ainstruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
0N/A format %{ "sarq $dst, $shift" %}
0N/A opcode(0xD3, 0x7); /* D3 /7 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Logical shift right by one
0N/Ainstruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (URShiftL dst shift));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xD1, 0x5); /* D1 /5 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
0N/A// Logical shift right by one
0N/Ainstruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xD1, 0x5); /* D1 /5 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Logical Shift Right by 8-bit immediate
0N/Ainstruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (URShiftL dst shift));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xC1, 0x5); /* C1 /5 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, shift));
0N/A// Logical Shift Right by 8-bit immediate
0N/Ainstruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xC1, 0x5); /* C1 /5 ib */
0N/A ins_encode(REX_mem_wide(dst), OpcP,
0N/A RM_opc_mem(secondary, dst), Con8or32(shift));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Logical Shift Right by variable
0N/Ainstruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (URShiftL dst shift));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xD3, 0x5); /* D3 /5 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Logical Shift Right by variable
0N/Ainstruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
0N/A format %{ "shrq $dst, $shift" %}
0N/A opcode(0xD3, 0x5); /* D3 /5 */
0N/A ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
0N/A// This idiom is used by the compiler for the i2b bytecode.
0N/Ainstruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
0N/A match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
0N/A format %{ "movsbl $dst, $src\t# i2b" %}
0N/A ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
0N/A// This idiom is used by the compiler the i2s bytecode.
0N/Ainstruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
0N/A match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
0N/A format %{ "movswl $dst, $src\t# i2s" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
0N/A effect(KILL cr, USE_DEF dst);
0N/A format %{ "roll $dst" %}
0N/A opcode(0xD1, 0x0); /* Opcode D1 /0 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/Ainstruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "roll $dst, $shift" %}
0N/A opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
0N/A ins_encode( reg_opc_imm(dst, shift) );
0N/Ainstruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "roll $dst, $shift" %}
0N/A opcode(0xD3, 0x0); /* Opcode D3 /0 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Rotate Left by one
0N/Ainstruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
0N/A match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
0N/A rolI_rReg_imm1(dst, cr);
0N/A// Rotate Left by 8-bit immediate
0N/Ainstruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
0N/A predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
0N/A match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
0N/A rolI_rReg_imm8(dst, lshift, cr);
0N/A// Rotate Left by variable
0N/Ainstruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
0N/A rolI_rReg_CL(dst, shift, cr);
0N/A// Rotate Left by variable
0N/Ainstruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
0N/A match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
0N/A rolI_rReg_CL(dst, shift, cr);
0N/Ainstruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
0N/A effect(USE_DEF dst, KILL cr);
0N/A format %{ "rorl $dst" %}
0N/A opcode(0xD1, 0x1); /* D1 /1 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/Ainstruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rorl $dst, $shift" %}
0N/A opcode(0xC1, 0x1); /* C1 /1 ib */
0N/A ins_encode(reg_opc_imm(dst, shift));
0N/Ainstruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rorl $dst, $shift" %}
0N/A opcode(0xD3, 0x1); /* D3 /1 */
0N/A ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Rotate Right by one
0N/Ainstruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
0N/A match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
0N/A rorI_rReg_imm1(dst, cr);
0N/A// Rotate Right by 8-bit immediate
0N/Ainstruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
0N/A predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
0N/A match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
0N/A rorI_rReg_imm8(dst, rshift, cr);
0N/A// Rotate Right by variable
0N/Ainstruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
0N/A rorI_rReg_CL(dst, shift, cr);
0N/A// Rotate Right by variable
0N/Ainstruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
0N/A match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
0N/A rorI_rReg_CL(dst, shift, cr);
0N/Ainstruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
0N/A effect(USE_DEF dst, KILL cr);
0N/A format %{ "rolq $dst" %}
0N/A opcode(0xD1, 0x0); /* Opcode D1 /0 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/Ainstruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rolq $dst, $shift" %}
0N/A opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
0N/A ins_encode( reg_opc_imm_wide(dst, shift) );
0N/Ainstruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rolq $dst, $shift" %}
0N/A opcode(0xD3, 0x0); /* Opcode D3 /0 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Rotate Left by one
0N/Ainstruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
0N/A match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
0N/A rolL_rReg_imm1(dst, cr);
0N/A// Rotate Left by 8-bit immediate
0N/Ainstruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
0N/A predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
0N/A match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
0N/A rolL_rReg_imm8(dst, lshift, cr);
0N/A// Rotate Left by variable
0N/Ainstruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
0N/A rolL_rReg_CL(dst, shift, cr);
0N/A// Rotate Left by variable
0N/Ainstruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
0N/A match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
0N/A rolL_rReg_CL(dst, shift, cr);
0N/Ainstruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
0N/A effect(USE_DEF dst, KILL cr);
0N/A format %{ "rorq $dst" %}
0N/A opcode(0xD1, 0x1); /* D1 /1 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/Ainstruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rorq $dst, $shift" %}
0N/A opcode(0xC1, 0x1); /* C1 /1 ib */
0N/A ins_encode(reg_opc_imm_wide(dst, shift));
0N/Ainstruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE shift, KILL cr);
0N/A format %{ "rorq $dst, $shift" %}
0N/A opcode(0xD3, 0x1); /* D3 /1 */
0N/A ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Rotate Right by one
0N/Ainstruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
0N/A match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
0N/A rorL_rReg_imm1(dst, cr);
0N/A// Rotate Right by 8-bit immediate
0N/Ainstruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
0N/A predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
0N/A match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
0N/A rorL_rReg_imm8(dst, rshift, cr);
0N/A// Rotate Right by variable
0N/Ainstruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
0N/A rorL_rReg_CL(dst, shift, cr);
0N/A// Rotate Right by variable
0N/Ainstruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
0N/A match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
0N/A rorL_rReg_CL(dst, shift, cr);
0N/A// Logical Instructions
0N/A// Integer Logical Instructions
0N/A// And Register with Register
0N/Ainstruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (AndI dst src));
0N/A format %{ "andl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// And Register with Immediate 255
0N/Ainstruct andI_rReg_imm255(rRegI dst, immI_255 src)
0N/A match(Set dst (AndI dst src));
0N/A format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
0N/A ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
0N/A// And Register with Immediate 255 and promote to long
0N/Ainstruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
0N/A match(Set dst (ConvI2L (AndI src mask)));
0N/A format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
0N/A ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A// And Register with Immediate 65535
0N/Ainstruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
0N/A match(Set dst (AndI dst src));
0N/A format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
0N/A ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
0N/A// And Register with Immediate 65535 and promote to long
0N/Ainstruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
0N/A match(Set dst (ConvI2L (AndI src mask)));
0N/A format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A// And Register with Immediate
0N/Ainstruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
0N/A match(Set dst (AndI dst src));
0N/A format %{ "andl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x04); /* Opcode 81 /4 */
0N/A ins_encode(OpcSErm(dst, src), Con8or32(src));
0N/A// And Register with Memory
0N/Ainstruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (AndI dst (LoadI src)));
0N/A format %{ "andl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// And Memory with Register
0N/Ainstruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (AndI (LoadI dst) src)));
0N/A format %{ "andl $dst, $src\t# int" %}
0N/A opcode(0x21); /* Opcode 21 /r */
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// And Memory with Immediate
0N/Ainstruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (AndI (LoadI dst) src)));
0N/A format %{ "andl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x4); /* Opcode 81 /4 id */
0N/A ins_encode(REX_mem(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Or Register with Register
0N/Ainstruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (OrI dst src));
0N/A format %{ "orl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Or Register with Immediate
0N/Ainstruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
0N/A match(Set dst (OrI dst src));
0N/A format %{ "orl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x01); /* Opcode 81 /1 id */
0N/A ins_encode(OpcSErm(dst, src), Con8or32(src));
0N/A// Or Register with Memory
0N/Ainstruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (OrI dst (LoadI src)));
0N/A format %{ "orl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Or Memory with Register
0N/Ainstruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (OrI (LoadI dst) src)));
0N/A format %{ "orl $dst, $src\t# int" %}
0N/A opcode(0x09); /* Opcode 09 /r */
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Or Memory with Immediate
0N/Ainstruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (OrI (LoadI dst) src)));
0N/A format %{ "orl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x1); /* Opcode 81 /1 id */
0N/A ins_encode(REX_mem(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Xor Register with Register
0N/Ainstruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (XorI dst src));
0N/A format %{ "xorl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Xor Register with Immediate
0N/Ainstruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
0N/A match(Set dst (XorI dst src));
0N/A format %{ "xorl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x06); /* Opcode 81 /6 id */
0N/A ins_encode(OpcSErm(dst, src), Con8or32(src));
0N/A// Xor Register with Memory
0N/Ainstruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
0N/A match(Set dst (XorI dst (LoadI src)));
0N/A format %{ "xorl $dst, $src\t# int" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Xor Memory with Register
0N/Ainstruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (XorI (LoadI dst) src)));
0N/A format %{ "xorl $dst, $src\t# int" %}
0N/A opcode(0x31); /* Opcode 31 /r */
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Xor Memory with Immediate
0N/Ainstruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
0N/A match(Set dst (StoreI dst (XorI (LoadI dst) src)));
0N/A format %{ "xorl $dst, $src\t# int" %}
0N/A opcode(0x81, 0x6); /* Opcode 81 /6 id */
0N/A ins_encode(REX_mem(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Long Logical Instructions
0N/A// And Register with Register
0N/Ainstruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (AndL dst src));
0N/A format %{ "andq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// And Register with Immediate 255
0N/Ainstruct andL_rReg_imm255(rRegL dst, immL_255 src)
0N/A match(Set dst (AndL dst src));
0N/A format %{ "movzbq $dst, $src\t# long & 0xFF" %}
0N/A ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
0N/A// And Register with Immediate 65535
0N/Ainstruct andL_rReg_imm65535(rRegI dst, immL_65535 src)
0N/A match(Set dst (AndL dst src));
0N/A format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
0N/A ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
0N/A// And Register with Immediate
0N/Ainstruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (AndL dst src));
0N/A format %{ "andq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x04); /* Opcode 81 /4 */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/A// And Register with Memory
0N/Ainstruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (AndL dst (LoadL src)));
0N/A format %{ "andq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// And Memory with Register
0N/Ainstruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (AndL (LoadL dst) src)));
0N/A format %{ "andq $dst, $src\t# long" %}
0N/A opcode(0x21); /* Opcode 21 /r */
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// And Memory with Immediate
0N/Ainstruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (AndL (LoadL dst) src)));
0N/A format %{ "andq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x4); /* Opcode 81 /4 id */
0N/A ins_encode(REX_mem_wide(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Or Register with Register
0N/Ainstruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (OrL dst src));
0N/A format %{ "orq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Or Register with Immediate
0N/Ainstruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (OrL dst src));
0N/A format %{ "orq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x01); /* Opcode 81 /1 id */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/A// Or Register with Memory
0N/Ainstruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (OrL dst (LoadL src)));
0N/A format %{ "orq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Or Memory with Register
0N/Ainstruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (OrL (LoadL dst) src)));
0N/A format %{ "orq $dst, $src\t# long" %}
0N/A opcode(0x09); /* Opcode 09 /r */
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Or Memory with Immediate
0N/Ainstruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (OrL (LoadL dst) src)));
0N/A format %{ "orq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x1); /* Opcode 81 /1 id */
0N/A ins_encode(REX_mem_wide(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Xor Register with Register
0N/Ainstruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (XorL dst src));
0N/A format %{ "xorq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Xor Register with Immediate
0N/Ainstruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (XorL dst src));
0N/A format %{ "xorq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x06); /* Opcode 81 /6 id */
0N/A ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
0N/A// Xor Register with Memory
0N/Ainstruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
0N/A match(Set dst (XorL dst (LoadL src)));
0N/A format %{ "xorq $dst, $src\t# long" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Xor Memory with Register
0N/Ainstruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (XorL (LoadL dst) src)));
0N/A format %{ "xorq $dst, $src\t# long" %}
0N/A opcode(0x31); /* Opcode 31 /r */
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/A// Xor Memory with Immediate
0N/Ainstruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
0N/A match(Set dst (StoreL dst (XorL (LoadL dst) src)));
0N/A format %{ "xorq $dst, $src\t# long" %}
0N/A opcode(0x81, 0x6); /* Opcode 81 /6 id */
0N/A ins_encode(REX_mem_wide(dst), OpcSE(src),
0N/A RM_opc_mem(secondary, dst), Con8or32(src));
0N/A ins_pipe(ialu_mem_imm);
0N/A// Convert Int to Boolean
0N/Ainstruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
0N/A match(Set dst (Conv2B src));
0N/A format %{ "testl $src, $src\t# ci2b\n\t"
0N/A "movzbl $dst, $dst" %}
0N/A ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
0N/A REX_reg_breg(dst, dst), // movzbl
0N/A Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// Convert Pointer to Boolean
0N/Ainstruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
0N/A match(Set dst (Conv2B src));
0N/A format %{ "testq $src, $src\t# cp2b\n\t"
0N/A "movzbl $dst, $dst" %}
0N/A ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
0N/A REX_reg_breg(dst, dst), // movzbl
0N/A Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
0N/A match(Set dst (CmpLTMask p q));
0N/A ins_cost(400); // XXX
0N/A format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
0N/A "movzbl $dst, $dst\n\t"
0N/A ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
0N/A REX_reg_breg(dst, dst), // movzbl
0N/A Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
0N/A match(Set dst (CmpLTMask dst zero));
0N/A ins_cost(100); // XXX
0N/A format %{ "sarl $dst, #31\t# cmpLTMask0" %}
0N/A opcode(0xC1, 0x7); /* C1 /7 ib */
0N/A ins_encode(reg_opc_imm(dst, 0x1F));
0N/Ainstruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
0N/A match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
0N/A effect(TEMP tmp, KILL cr);
0N/A ins_cost(400); // XXX
0N/A format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
0N/A "sbbl $tmp, $tmp\n\t"
0N/A ins_encode(enc_cmpLTP(p, q, y, tmp));
0N/A ins_pipe(pipe_cmplt);
0N/A/* If I enable this, I encourage spilling in the inner loop of compress.
0N/Ainstruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
0N/A match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
0N/A effect( TEMP tmp, KILL cr );
0N/A format %{ "SUB $p,$q\n\t"
0N/A ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
0N/A//---------- FP Instructions------------------------------------------------
0N/Ainstruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
0N/A match(Set cr (CmpF src1 src2));
0N/A format %{ "ucomiss $src1, $src2\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
0N/A match(Set cr (CmpF src1 (LoadF src2)));
0N/A format %{ "ucomiss $src1, $src2\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2)
0N/A match(Set cr (CmpF src1 src2));
0N/A format %{ "ucomiss $src1, $src2\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
0N/A match(Set cr (CmpD src1 src2));
0N/A format %{ "ucomisd $src1, $src2\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
0N/A match(Set cr (CmpD src1 (LoadD src2)));
0N/A format %{ "ucomisd $src1, $src2\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2)
0N/A match(Set cr (CmpD src1 src2));
0N/A format %{ "ucomisd $src1, [$src2]\n\t"
0N/A "pushfq\t# saw NaN, set CF\n\t"
0N/A "andq [rsp], #0xffffff2b\n\t"
0N/A "exit: nop\t# avoid branch to branch" %}
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
0N/A match(Set dst (CmpF3 src1 src2));
0N/A format %{ "ucomiss $src1, $src2\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
0N/A match(Set dst (CmpF3 src1 (LoadF src2)));
0N/A format %{ "ucomiss $src1, $src2\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr)
0N/A match(Set dst (CmpF3 src1 src2));
0N/A format %{ "ucomiss $src1, [$src2]\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
0N/A match(Set dst (CmpD3 src1 src2));
0N/A format %{ "ucomisd $src1, $src2\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
0N/A match(Set dst (CmpD3 src1 (LoadD src2)));
0N/A format %{ "ucomisd $src1, $src2\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/A// Compare into -1,0,1
0N/Ainstruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr)
0N/A match(Set dst (CmpD3 src1 src2));
0N/A format %{ "ucomisd $src1, [$src2]\n\t"
0N/A "movl $dst, #-1\n\t"
0N/A "movzbl $dst, $dst\n"
0N/A opcode(0x66, 0x0F, 0x2E);
0N/A ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addF_reg(regF dst, regF src)
0N/A match(Set dst (AddF dst src));
0N/A format %{ "addss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addF_mem(regF dst, memory src)
0N/A match(Set dst (AddF dst (LoadF src)));
0N/A format %{ "addss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addF_imm(regF dst, immF src)
0N/A match(Set dst (AddF dst src));
0N/A format %{ "addss $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addD_reg(regD dst, regD src)
0N/A match(Set dst (AddD dst src));
0N/A format %{ "addsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addD_mem(regD dst, memory src)
0N/A match(Set dst (AddD dst (LoadD src)));
0N/A format %{ "addsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct addD_imm(regD dst, immD src)
0N/A match(Set dst (AddD dst src));
0N/A format %{ "addsd $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x58);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subF_reg(regF dst, regF src)
0N/A match(Set dst (SubF dst src));
0N/A format %{ "subss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subF_mem(regF dst, memory src)
0N/A match(Set dst (SubF dst (LoadF src)));
0N/A format %{ "subss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subF_imm(regF dst, immF src)
0N/A match(Set dst (SubF dst src));
0N/A format %{ "subss $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subD_reg(regD dst, regD src)
0N/A match(Set dst (SubD dst src));
0N/A format %{ "subsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subD_mem(regD dst, memory src)
0N/A match(Set dst (SubD dst (LoadD src)));
0N/A format %{ "subsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct subD_imm(regD dst, immD src)
0N/A match(Set dst (SubD dst src));
0N/A format %{ "subsd $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5C);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulF_reg(regF dst, regF src)
0N/A match(Set dst (MulF dst src));
0N/A format %{ "mulss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulF_mem(regF dst, memory src)
0N/A match(Set dst (MulF dst (LoadF src)));
0N/A format %{ "mulss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulF_imm(regF dst, immF src)
0N/A match(Set dst (MulF dst src));
0N/A format %{ "mulss $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulD_reg(regD dst, regD src)
0N/A match(Set dst (MulD dst src));
0N/A format %{ "mulsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulD_mem(regD dst, memory src)
0N/A match(Set dst (MulD dst (LoadD src)));
0N/A format %{ "mulsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct mulD_imm(regD dst, immD src)
0N/A match(Set dst (MulD dst src));
0N/A format %{ "mulsd $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x59);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divF_reg(regF dst, regF src)
0N/A match(Set dst (DivF dst src));
0N/A format %{ "divss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divF_mem(regF dst, memory src)
0N/A match(Set dst (DivF dst (LoadF src)));
0N/A format %{ "divss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divF_imm(regF dst, immF src)
0N/A match(Set dst (DivF dst src));
0N/A format %{ "divss $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divD_reg(regD dst, regD src)
0N/A match(Set dst (DivD dst src));
0N/A format %{ "divsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divD_mem(regD dst, memory src)
0N/A match(Set dst (DivD dst (LoadD src)));
0N/A format %{ "divsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct divD_imm(regD dst, immD src)
0N/A match(Set dst (DivD dst src));
0N/A format %{ "divsd $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x5E);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtF_reg(regF dst, regF src)
0N/A match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
0N/A format %{ "sqrtss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtF_mem(regF dst, memory src)
0N/A match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
0N/A format %{ "sqrtss $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtF_imm(regF dst, immF src)
0N/A match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
0N/A format %{ "sqrtss $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF3, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtD_reg(regD dst, regD src)
0N/A match(Set dst (SqrtD src));
0N/A format %{ "sqrtsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtD_mem(regD dst, memory src)
0N/A match(Set dst (SqrtD (LoadD src)));
0N/A format %{ "sqrtsd $dst, $src" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct sqrtD_imm(regD dst, immD src)
0N/A match(Set dst (SqrtD src));
0N/A format %{ "sqrtsd $dst, [$src]" %}
0N/A ins_cost(150); // XXX
0N/A opcode(0xF2, 0x0F, 0x51);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct absF_reg(regF dst)
0N/A match(Set dst (AbsF dst));
0N/A format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
0N/A ins_encode(absF_encoding(dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct absD_reg(regD dst)
0N/A match(Set dst (AbsD dst));
0N/A format %{ "andpd $dst, [0x7fffffffffffffff]\t"
0N/A "# abs double by sign masking" %}
0N/A ins_encode(absD_encoding(dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct negF_reg(regF dst)
0N/A match(Set dst (NegF dst));
0N/A format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
0N/A ins_encode(negF_encoding(dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct negD_reg(regD dst)
0N/A match(Set dst (NegD dst));
0N/A format %{ "xorpd $dst, [0x8000000000000000]\t"
0N/A "# neg double by sign flipping" %}
0N/A ins_encode(negD_encoding(dst));
0N/A ins_pipe(pipe_slow);
0N/A// -----------Trig and Trancendental Instructions------------------------------
0N/Ainstruct cosD_reg(regD dst) %{
0N/A match(Set dst (CosD dst));
0N/A format %{ "dcos $dst\n\t" %}
0N/A ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
0N/A ins_pipe( pipe_slow );
0N/Ainstruct sinD_reg(regD dst) %{
0N/A match(Set dst (SinD dst));
0N/A format %{ "dsin $dst\n\t" %}
0N/A ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
0N/A ins_pipe( pipe_slow );
0N/Ainstruct tanD_reg(regD dst) %{
0N/A match(Set dst (TanD dst));
0N/A format %{ "dtan $dst\n\t" %}
0N/A ins_encode( Push_SrcXD(dst),
0N/A Opcode(0xD9), Opcode(0xF2), //fptan
0N/A Opcode(0xDD), Opcode(0xD8), //fstp st
0N/A Push_ResultXD(dst) );
0N/A ins_pipe( pipe_slow );
0N/Ainstruct log10D_reg(regD dst) %{
0N/A // The source and result Double operands in XMM registers
0N/A match(Set dst (Log10D dst));
0N/A // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
0N/A // fyl2x ; compute log_10(2) * log_2(x)
0N/A format %{ "fldlg2\t\t\t#Log10\n\t"
0N/A "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
0N/A ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
0N/A Opcode(0xD9), Opcode(0xF1), // fyl2x
0N/A Push_ResultXD(dst));
0N/A ins_pipe( pipe_slow );
0N/Ainstruct logD_reg(regD dst) %{
0N/A // The source and result Double operands in XMM registers
0N/A match(Set dst (LogD dst));
0N/A // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
0N/A // fyl2x ; compute log_e(2) * log_2(x)
0N/A format %{ "fldln2\t\t\t#Log_e\n\t"
0N/A "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
0N/A ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
0N/A Opcode(0xD9), Opcode(0xF1), // fyl2x
0N/A Push_ResultXD(dst));
0N/A ins_pipe( pipe_slow );
0N/A//----------Arithmetic Conversion Instructions---------------------------------
0N/Ainstruct roundFloat_nop(regF dst)
0N/A match(Set dst (RoundFloat dst));
0N/Ainstruct roundDouble_nop(regD dst)
0N/A match(Set dst (RoundDouble dst));
0N/Ainstruct convF2D_reg_reg(regD dst, regF src)
0N/A match(Set dst (ConvF2D src));
0N/A format %{ "cvtss2sd $dst, $src" %}
0N/A opcode(0xF3, 0x0F, 0x5A);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convF2D_reg_mem(regD dst, memory src)
0N/A match(Set dst (ConvF2D (LoadF src)));
0N/A format %{ "cvtss2sd $dst, $src" %}
0N/A opcode(0xF3, 0x0F, 0x5A);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convD2F_reg_reg(regF dst, regD src)
0N/A match(Set dst (ConvD2F src));
0N/A format %{ "cvtsd2ss $dst, $src" %}
0N/A opcode(0xF2, 0x0F, 0x5A);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convD2F_reg_mem(regF dst, memory src)
0N/A match(Set dst (ConvD2F (LoadD src)));
0N/A format %{ "cvtsd2ss $dst, $src" %}
0N/A opcode(0xF2, 0x0F, 0x5A);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/A// XXX do mem variants
0N/Ainstruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
0N/A match(Set dst (ConvF2I src));
0N/A format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
0N/A "cmpl $dst, #0x80000000\n\t"
0N/A "movss [rsp], $src\n\t"
0N/A "call f2i_fixup\n\t"
0N/A opcode(0xF3, 0x0F, 0x2C);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
0N/A f2i_fixup(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
0N/A match(Set dst (ConvF2L src));
0N/A format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
0N/A "cmpq $dst, [0x8000000000000000]\n\t"
0N/A "movss [rsp], $src\n\t"
0N/A "call f2l_fixup\n\t"
0N/A opcode(0xF3, 0x0F, 0x2C);
0N/A ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
0N/A f2l_fixup(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
0N/A match(Set dst (ConvD2I src));
0N/A format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
0N/A "cmpl $dst, #0x80000000\n\t"
0N/A "movsd [rsp], $src\n\t"
0N/A "call d2i_fixup\n\t"
0N/A opcode(0xF2, 0x0F, 0x2C);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
0N/A d2i_fixup(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
0N/A match(Set dst (ConvD2L src));
0N/A format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
0N/A "cmpq $dst, [0x8000000000000000]\n\t"
0N/A "movsd [rsp], $src\n\t"
0N/A "call d2l_fixup\n\t"
0N/A opcode(0xF2, 0x0F, 0x2C);
0N/A ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
0N/A d2l_fixup(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct convI2F_reg_reg(regF dst, rRegI src)
71N/A predicate(!UseXmmI2F);
0N/A match(Set dst (ConvI2F src));
0N/A format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
0N/A opcode(0xF3, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convI2F_reg_mem(regF dst, memory src)
0N/A match(Set dst (ConvI2F (LoadI src)));
0N/A format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
0N/A opcode(0xF3, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convI2D_reg_reg(regD dst, rRegI src)
71N/A predicate(!UseXmmI2D);
0N/A match(Set dst (ConvI2D src));
0N/A format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
0N/A opcode(0xF2, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convI2D_reg_mem(regD dst, memory src)
0N/A match(Set dst (ConvI2D (LoadI src)));
0N/A format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
0N/A opcode(0xF2, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
71N/Ainstruct convXI2F_reg(regF dst, rRegI src)
71N/A predicate(UseXmmI2F);
71N/A match(Set dst (ConvI2F src));
71N/A format %{ "movdl $dst, $src\n\t"
71N/A "cvtdq2psl $dst, $dst\t# i2f" %}
71N/A __ movdl($dst$$XMMRegister, $src$$Register);
71N/A __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
71N/A ins_pipe(pipe_slow); // XXX
71N/Ainstruct convXI2D_reg(regD dst, rRegI src)
71N/A predicate(UseXmmI2D);
71N/A match(Set dst (ConvI2D src));
71N/A format %{ "movdl $dst, $src\n\t"
71N/A "cvtdq2pdl $dst, $dst\t# i2d" %}
71N/A __ movdl($dst$$XMMRegister, $src$$Register);
71N/A __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
71N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convL2F_reg_reg(regF dst, rRegL src)
0N/A match(Set dst (ConvL2F src));
0N/A format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
0N/A opcode(0xF3, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convL2F_reg_mem(regF dst, memory src)
0N/A match(Set dst (ConvL2F (LoadL src)));
0N/A format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
0N/A opcode(0xF3, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convL2D_reg_reg(regD dst, rRegL src)
0N/A match(Set dst (ConvL2D src));
0N/A format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
0N/A opcode(0xF2, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convL2D_reg_mem(regD dst, memory src)
0N/A match(Set dst (ConvL2D (LoadL src)));
0N/A format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
0N/A opcode(0xF2, 0x0F, 0x2A);
0N/A ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow); // XXX
0N/Ainstruct convI2L_reg_reg(rRegL dst, rRegI src)
0N/A match(Set dst (ConvI2L src));
0N/A format %{ "movslq $dst, $src\t# i2l" %}
0N/A ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
0N/A// match(Set dst (ConvI2L src));
0N/A// // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
0N/A// // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
0N/A// predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
0N/A// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
0N/A// ((const TypeNode*) n)->type()->is_long()->_lo ==
0N/A// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
0N/A// format %{ "movl $dst, $src\t# unsigned i2l" %}
0N/A// ins_encode(enc_copy(dst, src));
0N/A// // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
0N/A// ins_pipe(ialu_reg_reg);
0N/Ainstruct convI2L_reg_mem(rRegL dst, memory src)
0N/A match(Set dst (ConvI2L (LoadI src)));
0N/A format %{ "movslq $dst, $src\t# i2l" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src));
0N/A ins_pipe(ialu_reg_mem);
0N/A// Zero-extend convert int to long
0N/Ainstruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
0N/A match(Set dst (AndL (ConvI2L src) mask));
0N/A format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
0N/A ins_encode(enc_copy(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/A// Zero-extend convert int to long
0N/Ainstruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
0N/A match(Set dst (AndL (ConvI2L (LoadI src)) mask));
0N/A format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
0N/A match(Set dst (AndL src mask));
0N/A format %{ "movl $dst, $src\t# zero-extend long" %}
0N/A ins_encode(enc_copy_always(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct convL2I_reg_reg(rRegI dst, rRegL src)
0N/A match(Set dst (ConvL2I src));
0N/A format %{ "movl $dst, $src\t# l2i" %}
0N/A ins_encode(enc_copy_always(dst, src));
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
0N/A match(Set dst (MoveF2I src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
0N/A ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
0N/A match(Set dst (MoveI2F src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
0N/A opcode(0xF3, 0x0F, 0x10);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
0N/A match(Set dst (MoveD2L src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
0N/A ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
0N/A ins_pipe(ialu_reg_mem);
0N/Ainstruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
0N/A predicate(!UseXmmLoadAndClearUpper);
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
0N/A opcode(0x66, 0x0F, 0x12);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
0N/A predicate(UseXmmLoadAndClearUpper);
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
0N/A opcode(0xF2, 0x0F, 0x10);
0N/A ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
0N/A match(Set dst (MoveF2I src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(95); // XXX
0N/A format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
0N/A opcode(0xF3, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
0N/A match(Set dst (MoveI2F src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
0N/A ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe( ialu_mem_reg );
0N/Ainstruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
0N/A match(Set dst (MoveD2L src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(95); // XXX
0N/A format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
0N/A opcode(0xF2, 0x0F, 0x11);
0N/A ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
0N/A ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
0N/A ins_pipe(ialu_mem_reg);
0N/Ainstruct MoveF2I_reg_reg(rRegI dst, regF src) %{
0N/A match(Set dst (MoveF2I src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movd $dst,$src\t# MoveF2I" %}
0N/A ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
0N/A ins_pipe( pipe_slow );
0N/Ainstruct MoveD2L_reg_reg(rRegL dst, regD src) %{
0N/A match(Set dst (MoveD2L src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movd $dst,$src\t# MoveD2L" %}
0N/A ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
0N/A ins_pipe( pipe_slow );
0N/A// The next instructions have long latency and use Int unit. Set high cost.
0N/Ainstruct MoveI2F_reg_reg(regF dst, rRegI src) %{
0N/A match(Set dst (MoveI2F src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movd $dst,$src\t# MoveI2F" %}
0N/A ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
0N/A ins_pipe( pipe_slow );
0N/Ainstruct MoveL2D_reg_reg(regD dst, rRegL src) %{
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A format %{ "movd $dst,$src\t# MoveL2D" %}
0N/A ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
0N/A ins_pipe( pipe_slow );
0N/A// Replicate scalar to packed byte (1 byte) values in xmm
0N/Ainstruct Repl8B_reg(regD dst, regD src) %{
0N/A match(Set dst (Replicate8B src));
0N/A format %{ "MOVDQA $dst,$src\n\t"
0N/A "PUNPCKLBW $dst,$dst\n\t"
0N/A "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
0N/A ins_encode( pshufd_8x8(dst, src));
0N/A ins_pipe( pipe_slow );
0N/A// Replicate scalar to packed byte (1 byte) values in xmm
0N/Ainstruct Repl8B_rRegI(regD dst, rRegI src) %{
0N/A match(Set dst (Replicate8B src));
0N/A format %{ "MOVD $dst,$src\n\t"
0N/A "PUNPCKLBW $dst,$dst\n\t"
0N/A "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
0N/A ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
0N/A ins_pipe( pipe_slow );
0N/A// Replicate scalar zero to packed byte (1 byte) values in xmm
0N/Ainstruct Repl8B_immI0(regD dst, immI0 zero) %{
0N/A match(Set dst (Replicate8B zero));
0N/A format %{ "PXOR $dst,$dst\t! replicate8B" %}
0N/A ins_encode( pxor(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed shore (2 byte) values in xmm
0N/Ainstruct Repl4S_reg(regD dst, regD src) %{
0N/A match(Set dst (Replicate4S src));
0N/A format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
0N/A ins_encode( pshufd_4x16(dst, src));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed shore (2 byte) values in xmm
0N/Ainstruct Repl4S_rRegI(regD dst, rRegI src) %{
0N/A match(Set dst (Replicate4S src));
0N/A format %{ "MOVD $dst,$src\n\t"
0N/A "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
0N/A ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar zero to packed short (2 byte) values in xmm
0N/Ainstruct Repl4S_immI0(regD dst, immI0 zero) %{
0N/A match(Set dst (Replicate4S zero));
0N/A format %{ "PXOR $dst,$dst\t! replicate4S" %}
0N/A ins_encode( pxor(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed char (2 byte) values in xmm
0N/Ainstruct Repl4C_reg(regD dst, regD src) %{
0N/A match(Set dst (Replicate4C src));
0N/A format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
0N/A ins_encode( pshufd_4x16(dst, src));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed char (2 byte) values in xmm
0N/Ainstruct Repl4C_rRegI(regD dst, rRegI src) %{
0N/A match(Set dst (Replicate4C src));
0N/A format %{ "MOVD $dst,$src\n\t"
0N/A "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
0N/A ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar zero to packed char (2 byte) values in xmm
0N/Ainstruct Repl4C_immI0(regD dst, immI0 zero) %{
0N/A match(Set dst (Replicate4C zero));
0N/A format %{ "PXOR $dst,$dst\t! replicate4C" %}
0N/A ins_encode( pxor(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed integer (4 byte) values in xmm
0N/Ainstruct Repl2I_reg(regD dst, regD src) %{
0N/A match(Set dst (Replicate2I src));
0N/A format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
0N/A ins_encode( pshufd(dst, src, 0x00));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed integer (4 byte) values in xmm
0N/Ainstruct Repl2I_rRegI(regD dst, rRegI src) %{
0N/A match(Set dst (Replicate2I src));
0N/A format %{ "MOVD $dst,$src\n\t"
0N/A "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
0N/A ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar zero to packed integer (2 byte) values in xmm
0N/Ainstruct Repl2I_immI0(regD dst, immI0 zero) %{
0N/A match(Set dst (Replicate2I zero));
0N/A format %{ "PXOR $dst,$dst\t! replicate2I" %}
0N/A ins_encode( pxor(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed single precision floating point values in xmm
0N/Ainstruct Repl2F_reg(regD dst, regD src) %{
0N/A match(Set dst (Replicate2F src));
0N/A format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
0N/A ins_encode( pshufd(dst, src, 0xe0));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed single precision floating point values in xmm
0N/Ainstruct Repl2F_regF(regD dst, regF src) %{
0N/A match(Set dst (Replicate2F src));
0N/A format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
0N/A ins_encode( pshufd(dst, src, 0xe0));
0N/A ins_pipe( fpu_reg_reg );
0N/A// Replicate scalar to packed single precision floating point values in xmm
0N/Ainstruct Repl2F_immF0(regD dst, immF0 zero) %{
0N/A match(Set dst (Replicate2F zero));
0N/A format %{ "PXOR $dst,$dst\t! replicate2F" %}
0N/A ins_encode( pxor(dst, dst));
0N/A ins_pipe( fpu_reg_reg );
0N/A// =======================================================================
0N/A// fast clearing of an array
0N/Ainstruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
0N/A match(Set dummy (ClearArray cnt base));
0N/A effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
0N/A format %{ "xorl rax, rax\t# ClearArray:\n\t"
0N/A "rep stosq\t# Store rax to *rdi++ while rcx--" %}
0N/A ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
0N/A Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
0N/A ins_pipe(pipe_slow);
0N/Ainstruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1,
0N/A rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr)
0N/A match(Set result (StrComp str1 str2));
0N/A effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
0N/A format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %}
0N/A ins_encode( enc_String_Compare() );
0N/A ins_pipe( pipe_slow );
169N/Ainstruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1,
169N/A rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) %{
169N/A match(Set result (AryEq ary1 ary2));
169N/A effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
169N/A format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %}
169N/A ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
0N/A//----------Control Flow Instructions------------------------------------------
0N/A// Signed compare Instructions
0N/A// XXX more variants!!
0N/Ainstruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
0N/A match(Set cr (CmpI op1 op2));
0N/A effect(DEF cr, USE op1, USE op2);
0N/A format %{ "cmpl $op1, $op2" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
0N/A ins_pipe(ialu_cr_reg_reg);
0N/Ainstruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
0N/A match(Set cr (CmpI op1 op2));
0N/A format %{ "cmpl $op1, $op2" %}
0N/A opcode(0x81, 0x07); /* Opcode 81 /7 */
0N/A ins_encode(OpcSErm(op1, op2), Con8or32(op2));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
0N/A match(Set cr (CmpI op1 (LoadI op2)));
0N/A ins_cost(500); // XXX
0N/A format %{ "cmpl $op1, $op2" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/Ainstruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
0N/A match(Set cr (CmpI src zero));
0N/A format %{ "testl $src, $src" %}
0N/A ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
0N/A match(Set cr (CmpI (AndI src con) zero));
0N/A format %{ "testl $src, $con" %}
0N/A ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
0N/A match(Set cr (CmpI (AndI src (LoadI mem)) zero));
0N/A format %{ "testl $src, $mem" %}
0N/A ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/A// Unsigned compare Instructions; really, same as signed except they
0N/A// produce an rFlagsRegU instead of rFlagsReg.
0N/Ainstruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
0N/A match(Set cr (CmpU op1 op2));
0N/A format %{ "cmpl $op1, $op2\t# unsigned" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
0N/A ins_pipe(ialu_cr_reg_reg);
0N/Ainstruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
0N/A match(Set cr (CmpU op1 op2));
0N/A format %{ "cmpl $op1, $op2\t# unsigned" %}
0N/A opcode(0x81,0x07); /* Opcode 81 /7 */
0N/A ins_encode(OpcSErm(op1, op2), Con8or32(op2));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
0N/A match(Set cr (CmpU op1 (LoadI op2)));
0N/A ins_cost(500); // XXX
0N/A format %{ "cmpl $op1, $op2\t# unsigned" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/A// // // Cisc-spilled version of cmpU_rReg
0N/A// //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
0N/A// // match(Set cr (CmpU (LoadI op1) op2));
0N/A// // format %{ "CMPu $op1,$op2" %}
0N/A// // opcode(0x39); /* Opcode 39 /r */
0N/A// // ins_encode( OpcP, reg_mem( op1, op2) );
0N/Ainstruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
0N/A match(Set cr (CmpU src zero));
0N/A format %{ "testl $src, $src\t# unsigned" %}
0N/A ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
0N/A match(Set cr (CmpP op1 op2));
0N/A format %{ "cmpq $op1, $op2\t# ptr" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
0N/A ins_pipe(ialu_cr_reg_reg);
0N/Ainstruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
0N/A match(Set cr (CmpP op1 (LoadP op2)));
0N/A ins_cost(500); // XXX
0N/A format %{ "cmpq $op1, $op2\t# ptr" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/A// // // Cisc-spilled version of cmpP_rReg
0N/A// //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
0N/A// // match(Set cr (CmpP (LoadP op1) op2));
0N/A// // format %{ "CMPu $op1,$op2" %}
0N/A// // opcode(0x39); /* Opcode 39 /r */
0N/A// // ins_encode( OpcP, reg_mem( op1, op2) );
0N/A// XXX this is generalized by compP_rReg_mem???
0N/A// Compare raw pointer (used in out-of-heap check).
0N/A// Only works because non-oop pointers must be raw pointers
0N/A// and raw pointers have no anti-dependencies.
0N/Ainstruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
0N/A predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
0N/A match(Set cr (CmpP op1 (LoadP op2)));
0N/A format %{ "cmpq $op1, $op2\t# raw ptr" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/A// This will generate a signed flags result. This should be OK since
0N/Ainstruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
0N/A match(Set cr (CmpP src zero));
0N/A format %{ "testq $src, $src\t# ptr" %}
0N/A ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/A// This will generate a signed flags result. This should be OK since
0N/Ainstruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero)
0N/A match(Set cr (CmpP (LoadP op) zero));
0N/A ins_cost(500); // XXX
0N/A format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
0N/A opcode(0xF7); /* Opcode F7 /0 */
0N/A ins_encode(REX_mem_wide(op),
0N/A OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
0N/A ins_pipe(ialu_cr_reg_imm);
164N/Ainstruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
164N/A match(Set cr (CmpN op1 op2));
164N/A format %{ "cmpl $op1, $op2\t# compressed ptr" %}
164N/A ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %}
164N/A ins_pipe(ialu_cr_reg_reg);
164N/Ainstruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
164N/A match(Set cr (CmpN src (LoadN mem)));
164N/A format %{ "cmpl $src, mem\t# compressed ptr" %}
164N/A Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
164N/A __ cmpl(as_Register($src$$reg), adr);
164N/A ins_pipe(ialu_cr_reg_mem);
113N/Ainstruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
113N/A match(Set cr (CmpN src zero));
164N/A format %{ "testl $src, $src\t# compressed ptr" %}
113N/A ins_encode %{ __ testl($src$$Register, $src$$Register); %}
113N/A ins_pipe(ialu_cr_reg_imm);
164N/Ainstruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero)
164N/A match(Set cr (CmpN (LoadN mem) zero));
164N/A format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
164N/A Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
164N/A __ cmpl(addr, (int)0xFFFFFFFF);
164N/A ins_pipe(ialu_cr_reg_mem);
0N/A// Yanked all unsigned pointer compare operations.
0N/A// Pointer compares are done with CmpP which is already unsigned.
0N/Ainstruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
0N/A match(Set cr (CmpL op1 op2));
0N/A format %{ "cmpq $op1, $op2" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
0N/A ins_pipe(ialu_cr_reg_reg);
0N/Ainstruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
0N/A match(Set cr (CmpL op1 op2));
0N/A format %{ "cmpq $op1, $op2" %}
0N/A opcode(0x81, 0x07); /* Opcode 81 /7 */
0N/A ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
0N/A match(Set cr (CmpL op1 (LoadL op2)));
0N/A ins_cost(500); // XXX
0N/A format %{ "cmpq $op1, $op2" %}
0N/A opcode(0x3B); /* Opcode 3B /r */
0N/A ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/Ainstruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
0N/A match(Set cr (CmpL src zero));
0N/A format %{ "testq $src, $src" %}
0N/A ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
0N/A match(Set cr (CmpL (AndL src con) zero));
0N/A format %{ "testq $src, $con\t# long" %}
0N/A ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
0N/A ins_pipe(ialu_cr_reg_imm);
0N/Ainstruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
0N/A match(Set cr (CmpL (AndL src (LoadL mem)) zero));
0N/A format %{ "testq $src, $mem" %}
0N/A ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
0N/A ins_pipe(ialu_cr_reg_mem);
0N/A// Manifest a CmpL result in an integer register. Very painful.
0N/A// This is the test to avoid.
0N/Ainstruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
0N/A match(Set dst (CmpL3 src1 src2));
0N/A ins_cost(275); // XXX
0N/A format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
0N/A "movzbl $dst, $dst\n\t"
0N/A ins_encode(cmpl3_flag(src1, src2, dst));
0N/A ins_pipe(pipe_slow);
0N/A//----------Max and Min--------------------------------------------------------
0N/Ainstruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE src, USE cr);
0N/A format %{ "cmovlgt $dst, $src\t# min" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg);
0N/Ainstruct minI_rReg(rRegI dst, rRegI src)
0N/A match(Set dst (MinI dst src));
0N/A compI_rReg(cr, dst, src);
0N/A cmovI_reg_g(dst, src, cr);
0N/Ainstruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
0N/A effect(USE_DEF dst, USE src, USE cr);
0N/A format %{ "cmovllt $dst, $src\t# max" %}
0N/A ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
0N/A ins_pipe(pipe_cmov_reg);
0N/Ainstruct maxI_rReg(rRegI dst, rRegI src)
0N/A match(Set dst (MaxI dst src));
0N/A compI_rReg(cr, dst, src);
0N/A cmovI_reg_l(dst, src, cr);
0N/A// ============================================================================
0N/A// Branch Instructions
0N/A// Jump Direct - Label defines a relative address from JMP+1
0N/Ainstruct jmpDir(label labl)
0N/A format %{ "jmp $labl" %}
0N/A ins_encode(OpcP, Lbl(labl));
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
0N/A format %{ "j$cop $labl" %}
0N/A ins_encode(Jcc(cop, labl));
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
0N/A match(CountedLoopEnd cop cr);
0N/A format %{ "j$cop $labl\t# loop end" %}
0N/A ins_encode(Jcc(cop, labl));
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl)
0N/A match(CountedLoopEnd cop cmp);
0N/A format %{ "j$cop,u $labl\t# loop end" %}
0N/A ins_encode(Jcc(cop, labl));
0N/A// Jump Direct Conditional - using unsigned comparison
0N/Ainstruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl)
0N/A format %{ "j$cop,u $labl" %}
0N/A ins_encode(Jcc(cop, labl));
0N/A// ============================================================================
0N/A// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
0N/A// superklass array for an instance of the superklass. Set a hidden
0N/A// internal cache on a hit (cache is checked with exposed code in
0N/A// gen_subtype_check()). Return NZ for a miss or zero for a hit. The
0N/A// encoding ALSO sets flags.
0N/Ainstruct partialSubtypeCheck(rdi_RegP result,
0N/A rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
0N/A match(Set result (PartialSubtypeCheck sub super));
0N/A effect(KILL rcx, KILL cr);
0N/A ins_cost(1100); // slightly larger than the next version
0N/A format %{ "cmpq rax, rsi\n\t"
0N/A "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
0N/A "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
0N/A "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
0N/A "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
0N/A "jne,s miss\t\t# Missed: rdi not-zero\n\t"
0N/A "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
0N/A "xorq $result, $result\t\t Hit: rdi zero\n\t"
0N/A opcode(0x1); // Force a XOR of RDI
0N/A ins_encode(enc_PartialSubtypeCheck());
0N/A ins_pipe(pipe_slow);
0N/Ainstruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
0N/A rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
0N/A match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
113N/A predicate(!UseCompressedOops); // decoding oop kills condition codes
0N/A effect(KILL rcx, KILL result);
0N/A format %{ "cmpq rax, rsi\n\t"
0N/A "jeq,s miss\t# Actually a hit; we are done.\n\t"
0N/A "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
0N/A "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
0N/A "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
0N/A "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
0N/A "jne,s miss\t\t# Missed: flags nz\n\t"
0N/A "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
0N/A opcode(0x0); // No need to XOR RDI
0N/A ins_encode(enc_PartialSubtypeCheck());
0N/A ins_pipe(pipe_slow);
0N/A// ============================================================================
0N/A// Branch Instructions -- short offset versions
0N/A// These instructions are used to replace jumps of a long offset (the default
0N/A// match) with jumps of a shorter offset. These instructions are all tagged
0N/A// with the ins_short_branch attribute, which causes the ADLC to suppress the
0N/A// match rules in general matching. Instead, the ADLC generates a conversion
0N/A// method in the MachNode which can be used to do in-place replacement of the
0N/A// long variant with the shorter variant. The compiler will determine if a
0N/A// branch can be taken by the is_short_branch_offset() predicate in the machine
0N/A// specific code section of the file.
0N/A// Jump Direct - Label defines a relative address from JMP+1
0N/Ainstruct jmpDir_short(label labl)
0N/A format %{ "jmp,s $labl" %}
0N/A ins_encode(OpcP, LblShort(labl));
0N/A ins_short_branch(1);
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl)
0N/A format %{ "j$cop,s $labl" %}
0N/A ins_encode(JccShort(cop, labl));
0N/A ins_short_branch(1);
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl)
0N/A match(CountedLoopEnd cop cr);
0N/A format %{ "j$cop,s $labl" %}
0N/A ins_encode(JccShort(cop, labl));
0N/A ins_short_branch(1);
0N/A// Jump Direct Conditional - Label defines a relative address from Jcc+1
0N/Ainstruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
0N/A match(CountedLoopEnd cop cmp);
0N/A format %{ "j$cop,us $labl" %}
0N/A ins_encode(JccShort(cop, labl));
0N/A ins_short_branch(1);
0N/A// Jump Direct Conditional - using unsigned comparison
0N/Ainstruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
0N/A format %{ "j$cop,us $labl" %}
0N/A ins_encode(JccShort(cop, labl));
0N/A ins_short_branch(1);
0N/A// ============================================================================
0N/A// inlined locking and unlocking
0N/Ainstruct cmpFastLock(rFlagsReg cr,
0N/A rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
0N/A match(Set cr (FastLock object box));
0N/A effect(TEMP tmp, TEMP scr);
0N/A format %{ "fastlock $object,$box,$tmp,$scr" %}
0N/A ins_encode(Fast_Lock(object, box, tmp, scr));
0N/A ins_pipe(pipe_slow);
0N/Ainstruct cmpFastUnlock(rFlagsReg cr,
0N/A rRegP object, rax_RegP box, rRegP tmp)
0N/A match(Set cr (FastUnlock object box));
0N/A format %{ "fastunlock $object, $box, $tmp" %}
0N/A ins_encode(Fast_Unlock(object, box, tmp));
0N/A ins_pipe(pipe_slow);
0N/A// ============================================================================
0N/A// Safepoint Instructions
0N/Ainstruct safePoint_poll(rFlagsReg cr)
0N/A format %{ "testl rax, [rip + #offset_to_poll_page]\t"
0N/A "# Safepoint: poll for GC" %}
0N/A size(6); // Opcode + ModRM + Disp32 == 6 bytes
0N/A ins_encode(enc_safepoint_poll);
0N/A ins_pipe(ialu_reg_mem);
0N/A// ============================================================================
0N/A// Call Java Static Instruction
0N/A// Note: If this code changes, the corresponding ret_addr_offset() and
0N/A// compute_padding() functions will have to be adjusted.
0N/Ainstruct CallStaticJavaDirect(method meth)
0N/A match(CallStaticJava);
0N/A format %{ "call,static " %}
0N/A opcode(0xE8); /* E8 cd */
0N/A ins_encode(Java_Static_Call(meth), call_epilog);
0N/A ins_pipe(pipe_slow);
0N/A// Call Java Dynamic Instruction
0N/A// Note: If this code changes, the corresponding ret_addr_offset() and
0N/A// compute_padding() functions will have to be adjusted.
0N/Ainstruct CallDynamicJavaDirect(method meth)
0N/A match(CallDynamicJava);
0N/A format %{ "movq rax, #Universe::non_oop_word()\n\t"
0N/A opcode(0xE8); /* E8 cd */
0N/A ins_encode(Java_Dynamic_Call(meth), call_epilog);
0N/A ins_pipe(pipe_slow);
0N/A// Call Runtime Instruction
0N/Ainstruct CallRuntimeDirect(method meth)
0N/A format %{ "call,runtime " %}
0N/A opcode(0xE8); /* E8 cd */
0N/A ins_encode(Java_To_Runtime(meth));
0N/A ins_pipe(pipe_slow);
0N/A// Call runtime without safepoint
0N/Ainstruct CallLeafDirect(method meth)
0N/A format %{ "call_leaf,runtime " %}
0N/A opcode(0xE8); /* E8 cd */
0N/A ins_encode(Java_To_Runtime(meth));
0N/A ins_pipe(pipe_slow);
0N/A// Call runtime without safepoint
0N/Ainstruct CallLeafNoFPDirect(method meth)
0N/A match(CallLeafNoFP);
0N/A format %{ "call_leaf_nofp,runtime " %}
0N/A opcode(0xE8); /* E8 cd */
0N/A ins_encode(Java_To_Runtime(meth));
0N/A ins_pipe(pipe_slow);
0N/A// Return Instruction
0N/A// Remove the return address & jump to it.
0N/A// Notice: We always emit a nop after a ret to make sure there is room
0N/A// for safepoint patching
0N/A// Tail Call; Jump from runtime stub to Java code.
0N/A// Also known as an 'interprocedural jump'.
0N/A// Target of jump will eventually return to caller.
0N/A// TailJump below removes the return address.
0N/Ainstruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
0N/A match(TailCall jump_target method_oop);
0N/A format %{ "jmp $jump_target\t# rbx holds method oop" %}
0N/A opcode(0xFF, 0x4); /* Opcode FF /4 */
0N/A ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
0N/A// Tail Jump; remove the return address; jump to target.
0N/A// TailCall above leaves the return address around.
0N/Ainstruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
0N/A match(TailJump jump_target ex_oop);
0N/A format %{ "popq rdx\t# pop return address\n\t"
0N/A "jmp $jump_target" %}
0N/A opcode(0xFF, 0x4); /* Opcode FF /4 */
0N/A ins_encode(Opcode(0x5a), // popq rdx
0N/A REX_reg(jump_target), OpcP, reg_opc(jump_target));
0N/A// Create exception oop: created by stack-crawling runtime code.
0N/A// Created exception is now available to this handler, and is setup
0N/A// just prior to jumping to this handler. No code emitted.
0N/Ainstruct CreateException(rax_RegP ex_oop)
0N/A match(Set ex_oop (CreateEx));
0N/A // use the following format syntax
0N/A format %{ "# exception oop is in rax; no code emitted" %}
0N/A// Rethrow exception:
0N/A// The exception oop will come in the first argument position.
0N/A// Then JUMP (not call) to the rethrow stub code.
0N/Ainstruct RethrowException()
0N/A // use the following format syntax
0N/A format %{ "jmp rethrow_stub" %}
0N/A ins_encode(enc_rethrow);
0N/A//----------PEEPHOLE RULES-----------------------------------------------------
0N/A// These must follow all instruction definitions as they use the names
0N/A// defined in the instructions definitions.
0N/A// peepmatch ( root_instr_name [precerding_instruction]* );
0N/A// // instruction numbers are zero-based using left to right order in peepmatch
0N/A// // in the replacement instruction's match rule
0N/A// ---------VM FLAGS---------------------------------------------------------
0N/A// All peephole optimizations can be turned off using -XX:-OptoPeephole
0N/A// Each peephole rule is given an identifying number starting with zero and
0N/A// increasing by one in the order seen by the parser. An individual peephole
0N/A// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
0N/A// on the command-line.
0N/A// ---------CURRENT LIMITATIONS----------------------------------------------
0N/A// Only match adjacent instructions in same basic block
0N/A// Only equality constraints
0N/A// Only one replacement instruction
0N/A// ---------EXAMPLE----------------------------------------------------------
0N/A// // pertinent parts of existing instructions in architecture description
0N/A// instruct movI(rRegI dst, rRegI src)
0N/A// match(Set dst (CopyI src));
0N/A// instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
0N/A// match(Set dst (AddI dst src));
0N/A// // Change (inc mov) to lea
0N/A// // increment preceeded by register-register move
0N/A// peepmatch ( incI_rReg movI );
0N/A// // require that the destination register of the increment
0N/A// // match the destination register of the move
0N/A// // construct a replacement instruction that sets
0N/A// // the destination to ( move's source register + one )
0N/A// Implementation no longer uses movX instructions since
0N/A// machine-independent system no longer uses CopyX nodes.
0N/A// peepmatch (incI_rReg movI);
0N/A// peepmatch (decI_rReg movI);
0N/A// peepmatch (addI_rReg_imm movI);
0N/A// peepmatch (incL_rReg movL);
0N/A// peepmatch (decL_rReg movL);
0N/A// peepmatch (addL_rReg_imm movL);
0N/A// peepmatch (addP_rReg_imm movP);
0N/A// // Change load of spilled value to only a spill
0N/A// instruct storeI(memory mem, rRegI src)
0N/A// match(Set mem (StoreI mem src));
0N/A// instruct loadI(rRegI dst, memory mem)
0N/A// match(Set dst (LoadI mem));
0N/A peepmatch (loadI storeI);
0N/A peepmatch (loadL storeL);
0N/A//----------SMARTSPILL RULES---------------------------------------------------
0N/A// These must follow all instruction definitions as they use the names
0N/A// defined in the instructions definitions.