x86.ad revision 3239
0N/A//
0N/A// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
0N/A// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A//
0N/A// This code is free software; you can redistribute it and/or modify it
0N/A// under the terms of the GNU General Public License version 2 only, as
0N/A// published by the Free Software Foundation.
0N/A//
0N/A// This code is distributed in the hope that it will be useful, but WITHOUT
0N/A// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A// version 2 for more details (a copy is included in the LICENSE file that
0N/A// accompanied this code).
0N/A//
0N/A// You should have received a copy of the GNU General Public License version
0N/A// 2 along with this work; if not, write to the Free Software Foundation,
0N/A// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A//
0N/A// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
0N/A// or visit www.oracle.com if you need additional information or have any
0N/A// questions.
0N/A//
0N/A//
0N/A
0N/A// X86 Common Architecture Description File
0N/A
0N/Asource %{
0N/A // Float masks come from different places depending on platform.
0N/A#ifdef _LP64
0N/A static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
0N/A static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
0N/A static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
0N/A static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
0N/A#else
0N/A static address float_signmask() { return (address)float_signmask_pool; }
0N/A static address float_signflip() { return (address)float_signflip_pool; }
0N/A static address double_signmask() { return (address)double_signmask_pool; }
0N/A static address double_signflip() { return (address)double_signflip_pool; }
0N/A#endif
0N/A
338N/A#ifndef PRODUCT
0N/A void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
0N/A st->print("nop \t# %d bytes pad for loops and calls", _count);
338N/A }
0N/A#endif
0N/A
0N/A void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A __ nop(_count);
0N/A }
0N/A
0N/A uint MachNopNode::size(PhaseRegAlloc*) const {
0N/A return _count;
0N/A }
0N/A
0N/A#ifndef PRODUCT
0N/A void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
0N/A st->print("# breakpoint");
0N/A }
0N/A#endif
0N/A
0N/A void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A __ int3();
0N/A }
0N/A
0N/A uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
0N/A return MachNode::size(ra_);
0N/A }
0N/A
0N/A%}
0N/A
0N/Aencode %{
0N/A
0N/A enc_class preserve_SP %{
0N/A debug_only(int off0 = cbuf.insts_size());
0N/A MacroAssembler _masm(&cbuf);
0N/A // RBP is preserved across all calls, even compiled calls.
0N/A // Use it to preserve RSP in places where the callee might change the SP.
0N/A __ movptr(rbp_mh_SP_save, rsp);
0N/A debug_only(int off1 = cbuf.insts_size());
0N/A assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
0N/A %}
0N/A
0N/A enc_class restore_SP %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ movptr(rsp, rbp_mh_SP_save);
0N/A %}
0N/A
0N/A enc_class call_epilog %{
0N/A if (VerifyStackAtCalls) {
0N/A // Check that stack depth is unchanged: find majik cookie on stack
0N/A int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
0N/A MacroAssembler _masm(&cbuf);
0N/A Label L;
0N/A __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
0N/A __ jccb(Assembler::equal, L);
0N/A // Die if stack mismatch
0N/A __ int3();
260N/A __ bind(L);
0N/A }
260N/A %}
0N/A
0N/A%}
0N/A
0N/A// INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
0N/A
0N/A// ============================================================================
0N/A
0N/Ainstruct ShouldNotReachHere() %{
0N/A match(Halt);
0N/A format %{ "int3\t# ShouldNotReachHere" %}
0N/A ins_encode %{
0N/A __ int3();
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/A// ============================================================================
0N/A
0N/Ainstruct addF_reg(regF dst, regF src) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (AddF dst src));
0N/A
0N/A format %{ "addss $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addss($dst$$XMMRegister, $src$$XMMRegister);
260N/A %}
0N/A ins_pipe(pipe_slow);
260N/A%}
0N/A
0N/Ainstruct addF_mem(regF dst, memory src) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (AddF dst (LoadF src)));
0N/A
0N/A format %{ "addss $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addss($dst$$XMMRegister, $src$$Address);
0N/A %}
260N/A ins_pipe(pipe_slow);
0N/A%}
260N/A
0N/Ainstruct addF_imm(regF dst, immF con) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (AddF dst con));
0N/A format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addss($dst$$XMMRegister, $constantaddress($con));
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vaddF_reg(regF dst, regF src1, regF src2) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (AddF src1 src2));
0N/A
0N/A format %{ "vaddss $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vaddF_mem(regF dst, regF src1, memory src2) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (AddF src1 (LoadF src2)));
0N/A
0N/A format %{ "vaddss $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
260N/Ainstruct vaddF_imm(regF dst, regF src, immF con) %{
0N/A predicate(UseAVX > 0);
260N/A match(Set dst (AddF src con));
0N/A
0N/A format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct addD_reg(regD dst, regD src) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
0N/A match(Set dst (AddD dst src));
0N/A
0N/A format %{ "addsd $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addsd($dst$$XMMRegister, $src$$XMMRegister);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct addD_mem(regD dst, memory src) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
0N/A match(Set dst (AddD dst (LoadD src)));
0N/A
0N/A format %{ "addsd $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addsd($dst$$XMMRegister, $src$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct addD_imm(regD dst, immD con) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
0N/A match(Set dst (AddD dst con));
0N/A format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ addsd($dst$$XMMRegister, $constantaddress($con));
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
260N/Ainstruct vaddD_reg(regD dst, regD src1, regD src2) %{
0N/A predicate(UseAVX > 0);
260N/A match(Set dst (AddD src1 src2));
0N/A
0N/A format %{ "vaddsd $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vaddD_mem(regD dst, regD src1, memory src2) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (AddD src1 (LoadD src2)));
0N/A
0N/A format %{ "vaddsd $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vaddD_imm(regD dst, regD src, immD con) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (AddD src con));
0N/A
0N/A format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct subF_reg(regF dst, regF src) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (SubF dst src));
0N/A
0N/A format %{ "subss $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ subss($dst$$XMMRegister, $src$$XMMRegister);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct subF_mem(regF dst, memory src) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (SubF dst (LoadF src)));
260N/A
0N/A format %{ "subss $dst, $src" %}
260N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ subss($dst$$XMMRegister, $src$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct subF_imm(regF dst, immF con) %{
0N/A predicate((UseSSE>=1) && (UseAVX == 0));
0N/A match(Set dst (SubF dst con));
0N/A format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0N/A ins_cost(150);
260N/A ins_encode %{
0N/A __ subss($dst$$XMMRegister, $constantaddress($con));
260N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vsubF_reg(regF dst, regF src1, regF src2) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (SubF src1 src2));
0N/A
0N/A format %{ "vsubss $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vsubF_mem(regF dst, regF src1, memory src2) %{
260N/A predicate(UseAVX > 0);
0N/A match(Set dst (SubF src1 (LoadF src2)));
260N/A
0N/A format %{ "vsubss $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct vsubF_imm(regF dst, regF src, immF con) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (SubF src con));
0N/A
0N/A format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
0N/A ins_cost(150);
0N/A ins_encode %{
260N/A __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
0N/A %}
260N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct subD_reg(regD dst, regD src) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
0N/A match(Set dst (SubD dst src));
0N/A
0N/A format %{ "subsd $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ subsd($dst$$XMMRegister, $src$$XMMRegister);
260N/A %}
0N/A ins_pipe(pipe_slow);
260N/A%}
0N/A
0N/Ainstruct subD_mem(regD dst, memory src) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
0N/A match(Set dst (SubD dst (LoadD src)));
0N/A
0N/A format %{ "subsd $dst, $src" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ subsd($dst$$XMMRegister, $src$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
0N/A%}
0N/A
0N/Ainstruct subD_imm(regD dst, immD con) %{
0N/A predicate((UseSSE>=2) && (UseAVX == 0));
260N/A match(Set dst (SubD dst con));
0N/A format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
260N/A ins_cost(150);
260N/A ins_encode %{
260N/A __ subsd($dst$$XMMRegister, $constantaddress($con));
260N/A %}
260N/A ins_pipe(pipe_slow);
260N/A%}
260N/A
260N/Ainstruct vsubD_reg(regD dst, regD src1, regD src2) %{
260N/A predicate(UseAVX > 0);
260N/A match(Set dst (SubD src1 src2));
260N/A
260N/A format %{ "vsubsd $dst, $src1, $src2" %}
260N/A ins_cost(150);
260N/A ins_encode %{
260N/A __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
260N/A %}
260N/A ins_pipe(pipe_slow);
260N/A%}
260N/A
260N/Ainstruct vsubD_mem(regD dst, regD src1, memory src2) %{
0N/A predicate(UseAVX > 0);
0N/A match(Set dst (SubD src1 (LoadD src2)));
0N/A
0N/A format %{ "vsubsd $dst, $src1, $src2" %}
0N/A ins_cost(150);
0N/A ins_encode %{
0N/A __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
0N/A %}
0N/A ins_pipe(pipe_slow);
%}
instruct vsubD_imm(regD dst, regD src, immD con) %{
predicate(UseAVX > 0);
match(Set dst (SubD src con));
format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct mulF_reg(regF dst, regF src) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (MulF dst src));
format %{ "mulss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ mulss($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct mulF_mem(regF dst, memory src) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (MulF dst (LoadF src)));
format %{ "mulss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ mulss($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct mulF_imm(regF dst, immF con) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (MulF dst con));
format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
ins_cost(150);
ins_encode %{
__ mulss($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct vmulF_reg(regF dst, regF src1, regF src2) %{
predicate(UseAVX > 0);
match(Set dst (MulF src1 src2));
format %{ "vmulss $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct vmulF_mem(regF dst, regF src1, memory src2) %{
predicate(UseAVX > 0);
match(Set dst (MulF src1 (LoadF src2)));
format %{ "vmulss $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct vmulF_imm(regF dst, regF src, immF con) %{
predicate(UseAVX > 0);
match(Set dst (MulF src con));
format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
ins_cost(150);
ins_encode %{
__ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct mulD_reg(regD dst, regD src) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (MulD dst src));
format %{ "mulsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ mulsd($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct mulD_mem(regD dst, memory src) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (MulD dst (LoadD src)));
format %{ "mulsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ mulsd($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct mulD_imm(regD dst, immD con) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (MulD dst con));
format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ mulsd($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct vmulD_reg(regD dst, regD src1, regD src2) %{
predicate(UseAVX > 0);
match(Set dst (MulD src1 src2));
format %{ "vmulsd $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct vmulD_mem(regD dst, regD src1, memory src2) %{
predicate(UseAVX > 0);
match(Set dst (MulD src1 (LoadD src2)));
format %{ "vmulsd $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct vmulD_imm(regD dst, regD src, immD con) %{
predicate(UseAVX > 0);
match(Set dst (MulD src con));
format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct divF_reg(regF dst, regF src) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (DivF dst src));
format %{ "divss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ divss($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct divF_mem(regF dst, memory src) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (DivF dst (LoadF src)));
format %{ "divss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ divss($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct divF_imm(regF dst, immF con) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (DivF dst con));
format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
ins_cost(150);
ins_encode %{
__ divss($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct vdivF_reg(regF dst, regF src1, regF src2) %{
predicate(UseAVX > 0);
match(Set dst (DivF src1 src2));
format %{ "vdivss $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct vdivF_mem(regF dst, regF src1, memory src2) %{
predicate(UseAVX > 0);
match(Set dst (DivF src1 (LoadF src2)));
format %{ "vdivss $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct vdivF_imm(regF dst, regF src, immF con) %{
predicate(UseAVX > 0);
match(Set dst (DivF src con));
format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
ins_cost(150);
ins_encode %{
__ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct divD_reg(regD dst, regD src) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (DivD dst src));
format %{ "divsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ divsd($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct divD_mem(regD dst, memory src) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (DivD dst (LoadD src)));
format %{ "divsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ divsd($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct divD_imm(regD dst, immD con) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (DivD dst con));
format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ divsd($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct vdivD_reg(regD dst, regD src1, regD src2) %{
predicate(UseAVX > 0);
match(Set dst (DivD src1 src2));
format %{ "vdivsd $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct vdivD_mem(regD dst, regD src1, memory src2) %{
predicate(UseAVX > 0);
match(Set dst (DivD src1 (LoadD src2)));
format %{ "vdivsd $dst, $src1, $src2" %}
ins_cost(150);
ins_encode %{
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct vdivD_imm(regD dst, regD src, immD con) %{
predicate(UseAVX > 0);
match(Set dst (DivD src con));
format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct absF_reg(regF dst) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (AbsF dst));
ins_cost(150);
format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
ins_encode %{
__ andps($dst$$XMMRegister, ExternalAddress(float_signmask()));
%}
ins_pipe(pipe_slow);
%}
instruct vabsF_reg(regF dst, regF src) %{
predicate(UseAVX > 0);
match(Set dst (AbsF src));
ins_cost(150);
format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %}
ins_encode %{
__ vandps($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(float_signmask()));
%}
ins_pipe(pipe_slow);
%}
instruct absD_reg(regD dst) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (AbsD dst));
ins_cost(150);
format %{ "andpd $dst, [0x7fffffffffffffff]\t"
"# abs double by sign masking" %}
ins_encode %{
__ andpd($dst$$XMMRegister, ExternalAddress(double_signmask()));
%}
ins_pipe(pipe_slow);
%}
instruct vabsD_reg(regD dst, regD src) %{
predicate(UseAVX > 0);
match(Set dst (AbsD src));
ins_cost(150);
format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t"
"# abs double by sign masking" %}
ins_encode %{
__ vandpd($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(double_signmask()));
%}
ins_pipe(pipe_slow);
%}
instruct negF_reg(regF dst) %{
predicate((UseSSE>=1) && (UseAVX == 0));
match(Set dst (NegF dst));
ins_cost(150);
format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
ins_encode %{
__ xorps($dst$$XMMRegister, ExternalAddress(float_signflip()));
%}
ins_pipe(pipe_slow);
%}
instruct vnegF_reg(regF dst, regF src) %{
predicate(UseAVX > 0);
match(Set dst (NegF src));
ins_cost(150);
format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %}
ins_encode %{
__ vxorps($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(float_signflip()));
%}
ins_pipe(pipe_slow);
%}
instruct negD_reg(regD dst) %{
predicate((UseSSE>=2) && (UseAVX == 0));
match(Set dst (NegD dst));
ins_cost(150);
format %{ "xorpd $dst, [0x8000000000000000]\t"
"# neg double by sign flipping" %}
ins_encode %{
__ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip()));
%}
ins_pipe(pipe_slow);
%}
instruct vnegD_reg(regD dst, regD src) %{
predicate(UseAVX > 0);
match(Set dst (NegD src));
ins_cost(150);
format %{ "vxorpd $dst, $src, [0x8000000000000000]\t"
"# neg double by sign flipping" %}
ins_encode %{
__ vxorpd($dst$$XMMRegister, $src$$XMMRegister,
ExternalAddress(double_signflip()));
%}
ins_pipe(pipe_slow);
%}
instruct sqrtF_reg(regF dst, regF src) %{
predicate(UseSSE>=1);
match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
format %{ "sqrtss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct sqrtF_mem(regF dst, memory src) %{
predicate(UseSSE>=1);
match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
format %{ "sqrtss $dst, $src" %}
ins_cost(150);
ins_encode %{
__ sqrtss($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct sqrtF_imm(regF dst, immF con) %{
predicate(UseSSE>=1);
match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
ins_cost(150);
ins_encode %{
__ sqrtss($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}
instruct sqrtD_reg(regD dst, regD src) %{
predicate(UseSSE>=2);
match(Set dst (SqrtD src));
format %{ "sqrtsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe(pipe_slow);
%}
instruct sqrtD_mem(regD dst, memory src) %{
predicate(UseSSE>=2);
match(Set dst (SqrtD (LoadD src)));
format %{ "sqrtsd $dst, $src" %}
ins_cost(150);
ins_encode %{
__ sqrtsd($dst$$XMMRegister, $src$$Address);
%}
ins_pipe(pipe_slow);
%}
instruct sqrtD_imm(regD dst, immD con) %{
predicate(UseSSE>=2);
match(Set dst (SqrtD con));
format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
ins_cost(150);
ins_encode %{
__ sqrtsd($dst$$XMMRegister, $constantaddress($con));
%}
ins_pipe(pipe_slow);
%}