sharedRuntime_x86_64.cpp revision 3158
0N/A/*
3158N/A * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "asm/assembler.hpp"
1879N/A#include "assembler_x86.inline.hpp"
1879N/A#include "code/debugInfoRec.hpp"
1879N/A#include "code/icBuffer.hpp"
1879N/A#include "code/vtableStubs.hpp"
1879N/A#include "interpreter/interpreter.hpp"
1879N/A#include "oops/compiledICHolderOop.hpp"
1879N/A#include "prims/jvmtiRedefineClassesTrace.hpp"
1879N/A#include "runtime/sharedRuntime.hpp"
1879N/A#include "runtime/vframeArray.hpp"
1879N/A#include "vmreg_x86.inline.hpp"
1879N/A#ifdef COMPILER1
1879N/A#include "c1/c1_Runtime1.hpp"
1879N/A#endif
1879N/A#ifdef COMPILER2
1879N/A#include "opto/runtime.hpp"
1879N/A#endif
0N/A
2578N/A#define __ masm->
0N/A
524N/Aconst int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
524N/A
0N/Aclass SimpleRuntimeFrame {
0N/A
0N/A public:
0N/A
0N/A // Most of the runtime stubs have this simple frame layout.
0N/A // This class exists to make the layout shared in one place.
0N/A // Offsets are for compiler stack slots, which are jints.
0N/A enum layout {
0N/A // The frame sender code expects that rbp will be in the "natural" place and
0N/A // will override any oopMap setting for it. We must therefore force the layout
0N/A // so that it agrees with the frame sender code.
0N/A rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
0N/A rbp_off2,
0N/A return_off, return_off2,
0N/A framesize
0N/A };
0N/A};
0N/A
0N/Aclass RegisterSaver {
0N/A // Capture info about frame layout. Layout offsets are in jint
0N/A // units because compiler frame slots are jints.
0N/A#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
0N/A enum layout {
0N/A fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
0N/A xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
0N/A DEF_XMM_OFFS(0),
0N/A DEF_XMM_OFFS(1),
0N/A DEF_XMM_OFFS(2),
0N/A DEF_XMM_OFFS(3),
0N/A DEF_XMM_OFFS(4),
0N/A DEF_XMM_OFFS(5),
0N/A DEF_XMM_OFFS(6),
0N/A DEF_XMM_OFFS(7),
0N/A DEF_XMM_OFFS(8),
0N/A DEF_XMM_OFFS(9),
0N/A DEF_XMM_OFFS(10),
0N/A DEF_XMM_OFFS(11),
0N/A DEF_XMM_OFFS(12),
0N/A DEF_XMM_OFFS(13),
0N/A DEF_XMM_OFFS(14),
0N/A DEF_XMM_OFFS(15),
0N/A fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
0N/A fpu_stateH_end,
0N/A r15_off, r15H_off,
0N/A r14_off, r14H_off,
0N/A r13_off, r13H_off,
0N/A r12_off, r12H_off,
0N/A r11_off, r11H_off,
0N/A r10_off, r10H_off,
0N/A r9_off, r9H_off,
0N/A r8_off, r8H_off,
0N/A rdi_off, rdiH_off,
0N/A rsi_off, rsiH_off,
0N/A ignore_off, ignoreH_off, // extra copy of rbp
0N/A rsp_off, rspH_off,
0N/A rbx_off, rbxH_off,
0N/A rdx_off, rdxH_off,
0N/A rcx_off, rcxH_off,
0N/A rax_off, raxH_off,
0N/A // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
0N/A align_off, alignH_off,
0N/A flags_off, flagsH_off,
0N/A // The frame sender code expects that rbp will be in the "natural" place and
0N/A // will override any oopMap setting for it. We must therefore force the layout
0N/A // so that it agrees with the frame sender code.
0N/A rbp_off, rbpH_off, // copy of rbp we will restore
0N/A return_off, returnH_off, // slot for return address
0N/A reg_save_size // size in compiler stack slots
0N/A };
0N/A
0N/A public:
0N/A static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
0N/A static void restore_live_registers(MacroAssembler* masm);
0N/A
0N/A // Offsets into the register save area
0N/A // Used by deoptimization when it is managing result register
0N/A // values on its own
0N/A
0N/A static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
304N/A static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
0N/A static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
0N/A static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
0N/A static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
0N/A
0N/A // During deoptimization only the result registers need to be restored,
0N/A // all the other values have already been extracted.
0N/A static void restore_result_registers(MacroAssembler* masm);
0N/A};
0N/A
0N/AOopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
0N/A
0N/A // Always make the frame size 16-byte aligned
0N/A int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
0N/A reg_save_size*BytesPerInt, 16);
0N/A // OopMap frame size is in compiler stack slots (jint's) not bytes or words
0N/A int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
0N/A // The caller will allocate additional_frame_words
0N/A int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
0N/A // CodeBlob frame size is in words.
0N/A int frame_size_in_words = frame_size_in_bytes / wordSize;
0N/A *total_frame_words = frame_size_in_words;
0N/A
0N/A // Save registers, fpu state, and flags.
0N/A // We assume caller has already pushed the return address onto the
0N/A // stack, so rsp is 8-byte aligned here.
0N/A // We push rpb twice in this sequence because we want the real rbp
0N/A // to be under the return like a normal enter.
0N/A
0N/A __ enter(); // rsp becomes 16-byte aligned here
0N/A __ push_CPU_state(); // Push a multiple of 16 bytes
0N/A if (frame::arg_reg_save_area_bytes != 0) {
0N/A // Allocate argument register save area
304N/A __ subptr(rsp, frame::arg_reg_save_area_bytes);
0N/A }
0N/A
0N/A // Set an oopmap for the call site. This oopmap will map all
0N/A // oop-registers and debug-info registers as callee-saved. This
0N/A // will allow deoptimization at this safepoint to find all possible
0N/A // debug-info recordings, as well as let GC find all oops.
0N/A
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map = new OopMap(frame_size_in_slots, 0);
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg());
0N/A // rbp location is known implicitly by the frame sender code, needs no oopmap
0N/A // and the location where rbp was saved by is ignored
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg());
0N/A
0N/A // %%% These should all be a waste but we'll keep things as they were for now
0N/A if (true) {
0N/A map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots),
0N/A rax->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots),
0N/A rcx->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots),
0N/A rdx->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots),
0N/A rbx->as_VMReg()->next());
0N/A // rbp location is known implicitly by the frame sender code, needs no oopmap
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots),
0N/A rsi->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots),
0N/A rdi->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots),
0N/A r8->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots),
0N/A r9->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots),
0N/A r10->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots),
0N/A r11->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots),
0N/A r12->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots),
0N/A r13->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots),
0N/A r14->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots),
0N/A r15->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots),
0N/A xmm0->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots),
0N/A xmm1->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots),
0N/A xmm2->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots),
0N/A xmm3->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots),
0N/A xmm4->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots),
0N/A xmm5->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots),
0N/A xmm6->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots),
0N/A xmm7->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots),
0N/A xmm8->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots),
0N/A xmm9->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots),
0N/A xmm10->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots),
0N/A xmm11->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots),
0N/A xmm12->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots),
0N/A xmm13->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots),
0N/A xmm14->as_VMReg()->next());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots),
0N/A xmm15->as_VMReg()->next());
0N/A }
0N/A
0N/A return map;
0N/A}
0N/A
0N/Avoid RegisterSaver::restore_live_registers(MacroAssembler* masm) {
0N/A if (frame::arg_reg_save_area_bytes != 0) {
0N/A // Pop arg register save area
304N/A __ addptr(rsp, frame::arg_reg_save_area_bytes);
0N/A }
0N/A // Recover CPU state
0N/A __ pop_CPU_state();
0N/A // Get the rbp described implicitly by the calling convention (no oopMap)
304N/A __ pop(rbp);
0N/A}
0N/A
0N/Avoid RegisterSaver::restore_result_registers(MacroAssembler* masm) {
0N/A
0N/A // Just restore result register. Only used by deoptimization. By
0N/A // now any callee save register that needs to be restored to a c2
0N/A // caller of the deoptee has been extracted into the vframeArray
0N/A // and will be stuffed into the c2i adapter we create for later
0N/A // restoration so only result registers need to be restored here.
0N/A
0N/A // Restore fp result register
0N/A __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
0N/A // Restore integer result register
304N/A __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
304N/A __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
304N/A
0N/A // Pop all of the register save are off the stack except the return address
304N/A __ addptr(rsp, return_offset_in_bytes());
0N/A}
0N/A
0N/A// The java_calling_convention describes stack locations as ideal slots on
0N/A// a frame with no abi restrictions. Since we must observe abi restrictions
0N/A// (like the placement of the register window) the slots must be biased by
0N/A// the following value.
0N/Astatic int reg2offset_in(VMReg r) {
0N/A // Account for saved rbp and return address
0N/A // This should really be in_preserve_stack_slots
0N/A return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
0N/A}
0N/A
0N/Astatic int reg2offset_out(VMReg r) {
0N/A return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
0N/A}
0N/A
0N/A// ---------------------------------------------------------------------------
0N/A// Read the array of BasicTypes from a signature, and compute where the
0N/A// arguments should go. Values in the VMRegPair regs array refer to 4-byte
0N/A// quantities. Values less than VMRegImpl::stack0 are registers, those above
0N/A// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
0N/A// as framesizes are fixed.
0N/A// VMRegImpl::stack0 refers to the first slot 0(sp).
0N/A// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
0N/A// up to RegisterImpl::number_of_registers) are the 64-bit
0N/A// integer registers.
0N/A
0N/A// Note: the INPUTS in sig_bt are in units of Java argument words, which are
0N/A// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
0N/A// units regardless of build. Of course for i486 there is no 64 bit build
0N/A
0N/A// The Java calling convention is a "shifted" version of the C ABI.
0N/A// By skipping the first C ABI register we can call non-static jni methods
0N/A// with small numbers of arguments without having to shuffle the arguments
0N/A// at all. Since we control the java ABI we ought to at least get some
0N/A// advantage out of it.
0N/A
0N/Aint SharedRuntime::java_calling_convention(const BasicType *sig_bt,
0N/A VMRegPair *regs,
0N/A int total_args_passed,
0N/A int is_outgoing) {
0N/A
0N/A // Create the mapping between argument positions and
0N/A // registers.
0N/A static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
0N/A j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
0N/A };
0N/A static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
0N/A j_farg0, j_farg1, j_farg2, j_farg3,
0N/A j_farg4, j_farg5, j_farg6, j_farg7
0N/A };
0N/A
0N/A
0N/A uint int_args = 0;
0N/A uint fp_args = 0;
0N/A uint stk_args = 0; // inc by 2 each time
0N/A
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A switch (sig_bt[i]) {
0N/A case T_BOOLEAN:
0N/A case T_CHAR:
0N/A case T_BYTE:
0N/A case T_SHORT:
0N/A case T_INT:
0N/A if (int_args < Argument::n_int_register_parameters_j) {
0N/A regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_VOID:
0N/A // halves of T_LONG or T_DOUBLE
0N/A assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
0N/A regs[i].set_bad();
0N/A break;
0N/A case T_LONG:
0N/A assert(sig_bt[i + 1] == T_VOID, "expecting half");
0N/A // fall through
0N/A case T_OBJECT:
0N/A case T_ARRAY:
0N/A case T_ADDRESS:
0N/A if (int_args < Argument::n_int_register_parameters_j) {
0N/A regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
0N/A } else {
0N/A regs[i].set2(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_FLOAT:
0N/A if (fp_args < Argument::n_float_register_parameters_j) {
0N/A regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_DOUBLE:
0N/A assert(sig_bt[i + 1] == T_VOID, "expecting half");
0N/A if (fp_args < Argument::n_float_register_parameters_j) {
0N/A regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
0N/A } else {
0N/A regs[i].set2(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A default:
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A }
0N/A
0N/A return round_to(stk_args, 2);
0N/A}
0N/A
0N/A// Patch the callers callsite with entry to compiled code if it exists.
0N/Astatic void patch_callers_callsite(MacroAssembler *masm) {
0N/A Label L;
0N/A __ verify_oop(rbx);
304N/A __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A
0N/A // Save the current stack pointer
304N/A __ mov(r13, rsp);
0N/A // Schedule the branch target address early.
0N/A // Call into the VM to patch the caller, then jump to compiled callee
0N/A // rax isn't live so capture return address while we easily can
304N/A __ movptr(rax, Address(rsp, 0));
0N/A
0N/A // align stack so push_CPU_state doesn't fault
304N/A __ andptr(rsp, -(StackAlignmentInBytes));
0N/A __ push_CPU_state();
0N/A
0N/A
0N/A __ verify_oop(rbx);
0N/A // VM needs caller's callsite
0N/A // VM needs target method
0N/A // This needs to be a long call since we will relocate this adapter to
0N/A // the codeBuffer and it may not reach
0N/A
0N/A // Allocate argument register save area
0N/A if (frame::arg_reg_save_area_bytes != 0) {
304N/A __ subptr(rsp, frame::arg_reg_save_area_bytes);
0N/A }
304N/A __ mov(c_rarg0, rbx);
304N/A __ mov(c_rarg1, rax);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
0N/A
0N/A // De-allocate argument register save area
0N/A if (frame::arg_reg_save_area_bytes != 0) {
304N/A __ addptr(rsp, frame::arg_reg_save_area_bytes);
0N/A }
0N/A
0N/A __ pop_CPU_state();
0N/A // restore sp
304N/A __ mov(rsp, r13);
0N/A __ bind(L);
0N/A}
0N/A
0N/A
0N/Astatic void gen_c2i_adapter(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
0N/A const VMRegPair *regs,
0N/A Label& skip_fixup) {
0N/A // Before we get into the guts of the C2I adapter, see if we should be here
0N/A // at all. We've come from compiled code and are attempting to jump to the
0N/A // interpreter, which means the caller made a static call to get here
0N/A // (vcalls always get a compiled target if there is one). Check for a
0N/A // compiled target. If there is one, we need to patch the caller's call.
0N/A patch_callers_callsite(masm);
0N/A
0N/A __ bind(skip_fixup);
0N/A
0N/A // Since all args are passed on the stack, total_args_passed *
0N/A // Interpreter::stackElementSize is the space we need. Plus 1 because
0N/A // we also account for the return address location since
0N/A // we store it first rather than hold it in rax across all the shuffling
0N/A
1426N/A int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
0N/A
0N/A // stack is aligned, keep it that way
0N/A extraspace = round_to(extraspace, 2*wordSize);
0N/A
0N/A // Get return address
304N/A __ pop(rax);
0N/A
0N/A // set senderSP value
304N/A __ mov(r13, rsp);
304N/A
304N/A __ subptr(rsp, extraspace);
0N/A
0N/A // Store the return address in the expected location
304N/A __ movptr(Address(rsp, 0), rax);
0N/A
0N/A // Now write the args into the outgoing interpreter space
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A if (sig_bt[i] == T_VOID) {
0N/A assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
0N/A continue;
0N/A }
0N/A
0N/A // offset to start parameters
1426N/A int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
1426N/A int next_off = st_off - Interpreter::stackElementSize;
0N/A
0N/A // Say 4 args:
0N/A // i st_off
0N/A // 0 32 T_LONG
0N/A // 1 24 T_VOID
0N/A // 2 16 T_OBJECT
0N/A // 3 8 T_BOOL
0N/A // - 0 return address
0N/A //
0N/A // However to make thing extra confusing. Because we can fit a long/double in
0N/A // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
0N/A // leaves one slot empty and only stores to a single slot. In this case the
0N/A // slot that is occupied is the T_VOID slot. See I said it was confusing.
0N/A
0N/A VMReg r_1 = regs[i].first();
0N/A VMReg r_2 = regs[i].second();
0N/A if (!r_1->is_valid()) {
0N/A assert(!r_2->is_valid(), "");
0N/A continue;
0N/A }
0N/A if (r_1->is_stack()) {
0N/A // memory to memory use rax
0N/A int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
0N/A if (!r_2->is_valid()) {
0N/A // sign extend??
0N/A __ movl(rax, Address(rsp, ld_off));
304N/A __ movptr(Address(rsp, st_off), rax);
0N/A
0N/A } else {
0N/A
0N/A __ movq(rax, Address(rsp, ld_off));
0N/A
0N/A // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
0N/A // T_DOUBLE and T_LONG use two slots in the interpreter
0N/A if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
0N/A // ld_off == LSW, ld_off+wordSize == MSW
0N/A // st_off == MSW, next_off == LSW
0N/A __ movq(Address(rsp, next_off), rax);
0N/A#ifdef ASSERT
0N/A // Overwrite the unused slot with known junk
0N/A __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
304N/A __ movptr(Address(rsp, st_off), rax);
0N/A#endif /* ASSERT */
0N/A } else {
0N/A __ movq(Address(rsp, st_off), rax);
0N/A }
0N/A }
0N/A } else if (r_1->is_Register()) {
0N/A Register r = r_1->as_Register();
0N/A if (!r_2->is_valid()) {
0N/A // must be only an int (or less ) so move only 32bits to slot
0N/A // why not sign extend??
0N/A __ movl(Address(rsp, st_off), r);
0N/A } else {
0N/A // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
0N/A // T_DOUBLE and T_LONG use two slots in the interpreter
0N/A if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
0N/A // long/double in gpr
0N/A#ifdef ASSERT
0N/A // Overwrite the unused slot with known junk
0N/A __ mov64(rax, CONST64(0xdeadffffdeadaaab));
304N/A __ movptr(Address(rsp, st_off), rax);
0N/A#endif /* ASSERT */
0N/A __ movq(Address(rsp, next_off), r);
0N/A } else {
304N/A __ movptr(Address(rsp, st_off), r);
0N/A }
0N/A }
0N/A } else {
0N/A assert(r_1->is_XMMRegister(), "");
0N/A if (!r_2->is_valid()) {
0N/A // only a float use just part of the slot
0N/A __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
0N/A } else {
0N/A#ifdef ASSERT
0N/A // Overwrite the unused slot with known junk
0N/A __ mov64(rax, CONST64(0xdeadffffdeadaaac));
304N/A __ movptr(Address(rsp, st_off), rax);
0N/A#endif /* ASSERT */
0N/A __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
0N/A }
0N/A }
0N/A }
0N/A
0N/A // Schedule the branch target address early.
304N/A __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
0N/A __ jmp(rcx);
0N/A}
0N/A
0N/Astatic void gen_i2c_adapter(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
0N/A const VMRegPair *regs) {
0N/A
0N/A // Note: r13 contains the senderSP on entry. We must preserve it since
0N/A // we may do a i2c -> c2i transition if we lose a race where compiled
0N/A // code goes non-entrant while we get args ready.
0N/A // In addition we use r13 to locate all the interpreter args as
0N/A // we must align the stack to 16 bytes on an i2c entry else we
0N/A // lose alignment we expect in all compiled code and register
0N/A // save code can segv when fxsave instructions find improperly
0N/A // aligned stack pointer.
0N/A
2117N/A // Pick up the return address
304N/A __ movptr(rax, Address(rsp, 0));
0N/A
1135N/A // Must preserve original SP for loading incoming arguments because
1135N/A // we need to align the outgoing SP for compiled code.
1135N/A __ movptr(r11, rsp);
1135N/A
0N/A // Cut-out for having no stack args. Since up to 2 int/oop args are passed
0N/A // in registers, we will occasionally have no stack args.
0N/A int comp_words_on_stack = 0;
0N/A if (comp_args_on_stack) {
0N/A // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
0N/A // registers are below. By subtracting stack0, we either get a negative
0N/A // number (all values in registers) or the maximum stack slot accessed.
0N/A
0N/A // Convert 4-byte c2 stack slots to words.
0N/A comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
0N/A // Round up to miminum stack alignment, in wordSize
0N/A comp_words_on_stack = round_to(comp_words_on_stack, 2);
304N/A __ subptr(rsp, comp_words_on_stack * wordSize);
0N/A }
0N/A
0N/A
0N/A // Ensure compiled code always sees stack at proper alignment
304N/A __ andptr(rsp, -16);
0N/A
0N/A // push the return address and misalign the stack that youngest frame always sees
0N/A // as far as the placement of the call instruction
304N/A __ push(rax);
0N/A
1135N/A // Put saved SP in another register
1135N/A const Register saved_sp = rax;
1135N/A __ movptr(saved_sp, r11);
1135N/A
0N/A // Will jump to the compiled code just as if compiled code was doing it.
0N/A // Pre-load the register-jump target early, to schedule it better.
304N/A __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
0N/A
0N/A // Now generate the shuffle code. Pick up all register args and move the
0N/A // rest through the floating point stack top.
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A if (sig_bt[i] == T_VOID) {
0N/A // Longs and doubles are passed in native word order, but misaligned
0N/A // in the 32-bit build.
0N/A assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
0N/A continue;
0N/A }
0N/A
0N/A // Pick up 0, 1 or 2 words from SP+offset.
0N/A
0N/A assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
0N/A "scrambled load targets?");
0N/A // Load in argument order going down.
1426N/A int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
0N/A // Point to interpreter value (vs. tag)
1426N/A int next_off = ld_off - Interpreter::stackElementSize;
0N/A //
0N/A //
0N/A //
0N/A VMReg r_1 = regs[i].first();
0N/A VMReg r_2 = regs[i].second();
0N/A if (!r_1->is_valid()) {
0N/A assert(!r_2->is_valid(), "");
0N/A continue;
0N/A }
0N/A if (r_1->is_stack()) {
0N/A // Convert stack slot to an SP offset (+ wordSize to account for return address )
0N/A int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
1135N/A
1135N/A // We can use r13 as a temp here because compiled code doesn't need r13 as an input
1135N/A // and if we end up going thru a c2i because of a miss a reasonable value of r13
1135N/A // will be generated.
0N/A if (!r_2->is_valid()) {
0N/A // sign extend???
1135N/A __ movl(r13, Address(saved_sp, ld_off));
1135N/A __ movptr(Address(rsp, st_off), r13);
0N/A } else {
0N/A //
0N/A // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
0N/A // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
0N/A // So we must adjust where to pick up the data to match the interpreter.
0N/A //
0N/A // Interpreter local[n] == MSW, local[n+1] == LSW however locals
0N/A // are accessed as negative so LSW is at LOW address
0N/A
0N/A // ld_off is MSW so get LSW
0N/A const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
0N/A next_off : ld_off;
1135N/A __ movq(r13, Address(saved_sp, offset));
0N/A // st_off is LSW (i.e. reg.first())
1135N/A __ movq(Address(rsp, st_off), r13);
0N/A }
0N/A } else if (r_1->is_Register()) { // Register argument
0N/A Register r = r_1->as_Register();
0N/A assert(r != rax, "must be different");
0N/A if (r_2->is_valid()) {
0N/A //
0N/A // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
0N/A // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
0N/A // So we must adjust where to pick up the data to match the interpreter.
0N/A
0N/A const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
0N/A next_off : ld_off;
0N/A
0N/A // this can be a misaligned move
1135N/A __ movq(r, Address(saved_sp, offset));
0N/A } else {
0N/A // sign extend and use a full word?
1135N/A __ movl(r, Address(saved_sp, ld_off));
0N/A }
0N/A } else {
0N/A if (!r_2->is_valid()) {
1135N/A __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
0N/A } else {
1135N/A __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
0N/A }
0N/A }
0N/A }
0N/A
0N/A // 6243940 We might end up in handle_wrong_method if
0N/A // the callee is deoptimized as we race thru here. If that
0N/A // happens we don't want to take a safepoint because the
0N/A // caller frame will look interpreted and arguments are now
0N/A // "compiled" so it is much better to make this transition
0N/A // invisible to the stack walking code. Unfortunately if
0N/A // we try and find the callee by normal means a safepoint
0N/A // is possible. So we stash the desired callee in the thread
0N/A // and the vm will find there should this case occur.
0N/A
304N/A __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
0N/A
0N/A // put methodOop where a c2i would expect should we end up there
0N/A // only needed becaus eof c2 resolve stubs return methodOop as a result in
0N/A // rax
304N/A __ mov(rax, rbx);
0N/A __ jmp(r11);
0N/A}
0N/A
0N/A// ---------------------------------------------------------------
0N/AAdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
1187N/A const VMRegPair *regs,
1187N/A AdapterFingerPrint* fingerprint) {
0N/A address i2c_entry = __ pc();
0N/A
0N/A gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
0N/A
0N/A // -------------------------------------------------------------------------
0N/A // Generate a C2I adapter. On entry we know rbx holds the methodOop during calls
0N/A // to the interpreter. The args start out packed in the compiled layout. They
0N/A // need to be unpacked into the interpreter layout. This will almost always
0N/A // require some stack space. We grow the current (compiled) stack, then repack
0N/A // the args. We finally end in a jump to the generic interpreter entry point.
0N/A // On exit from the interpreter, the interpreter will restore our SP (lest the
0N/A // compiled code, which relys solely on SP and not RBP, get sick).
0N/A
0N/A address c2i_unverified_entry = __ pc();
0N/A Label skip_fixup;
0N/A Label ok;
0N/A
0N/A Register holder = rax;
0N/A Register receiver = j_rarg0;
0N/A Register temp = rbx;
0N/A
0N/A {
0N/A __ verify_oop(holder);
113N/A __ load_klass(temp, receiver);
0N/A __ verify_oop(temp);
0N/A
304N/A __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
304N/A __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
0N/A __ jcc(Assembler::equal, ok);
0N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A
0N/A __ bind(ok);
0N/A // Method might have been compiled since the call site was patched to
0N/A // interpreted if that is the case treat it as a miss so we can get
0N/A // the call site corrected.
304N/A __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, skip_fixup);
0N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A }
0N/A
0N/A address c2i_entry = __ pc();
0N/A
0N/A gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
0N/A
0N/A __ flush();
1187N/A return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
0N/A}
0N/A
0N/Aint SharedRuntime::c_calling_convention(const BasicType *sig_bt,
0N/A VMRegPair *regs,
0N/A int total_args_passed) {
0N/A// We return the amount of VMRegImpl stack slots we need to reserve for all
0N/A// the arguments NOT counting out_preserve_stack_slots.
0N/A
0N/A// NOTE: These arrays will have to change when c1 is ported
0N/A#ifdef _WIN64
0N/A static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
0N/A c_rarg0, c_rarg1, c_rarg2, c_rarg3
0N/A };
0N/A static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
0N/A c_farg0, c_farg1, c_farg2, c_farg3
0N/A };
0N/A#else
0N/A static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
0N/A c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
0N/A };
0N/A static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
0N/A c_farg0, c_farg1, c_farg2, c_farg3,
0N/A c_farg4, c_farg5, c_farg6, c_farg7
0N/A };
0N/A#endif // _WIN64
0N/A
0N/A
0N/A uint int_args = 0;
0N/A uint fp_args = 0;
0N/A uint stk_args = 0; // inc by 2 each time
0N/A
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A switch (sig_bt[i]) {
0N/A case T_BOOLEAN:
0N/A case T_CHAR:
0N/A case T_BYTE:
0N/A case T_SHORT:
0N/A case T_INT:
0N/A if (int_args < Argument::n_int_register_parameters_c) {
0N/A regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
0N/A#ifdef _WIN64
0N/A fp_args++;
0N/A // Allocate slots for callee to stuff register args the stack.
0N/A stk_args += 2;
0N/A#endif
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_LONG:
0N/A assert(sig_bt[i + 1] == T_VOID, "expecting half");
0N/A // fall through
0N/A case T_OBJECT:
0N/A case T_ARRAY:
0N/A case T_ADDRESS:
0N/A if (int_args < Argument::n_int_register_parameters_c) {
0N/A regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
0N/A#ifdef _WIN64
0N/A fp_args++;
0N/A stk_args += 2;
0N/A#endif
0N/A } else {
0N/A regs[i].set2(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_FLOAT:
0N/A if (fp_args < Argument::n_float_register_parameters_c) {
0N/A regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
0N/A#ifdef _WIN64
0N/A int_args++;
0N/A // Allocate slots for callee to stuff register args the stack.
0N/A stk_args += 2;
0N/A#endif
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_DOUBLE:
0N/A assert(sig_bt[i + 1] == T_VOID, "expecting half");
0N/A if (fp_args < Argument::n_float_register_parameters_c) {
0N/A regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
0N/A#ifdef _WIN64
0N/A int_args++;
0N/A // Allocate slots for callee to stuff register args the stack.
0N/A stk_args += 2;
0N/A#endif
0N/A } else {
0N/A regs[i].set2(VMRegImpl::stack2reg(stk_args));
0N/A stk_args += 2;
0N/A }
0N/A break;
0N/A case T_VOID: // Halves of longs and doubles
0N/A assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
0N/A regs[i].set_bad();
0N/A break;
0N/A default:
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A }
0N/A#ifdef _WIN64
0N/A // windows abi requires that we always allocate enough stack space
0N/A // for 4 64bit registers to be stored down.
0N/A if (stk_args < 8) {
0N/A stk_args = 8;
0N/A }
0N/A#endif // _WIN64
0N/A
0N/A return stk_args;
0N/A}
0N/A
0N/A// On 64 bit we will store integer like items to the stack as
0N/A// 64 bits items (sparc abi) even though java would only store
0N/A// 32bits for a parameter. On 32bit it will simply be 32 bits
0N/A// So this routine will do 32->32 on 32bit and 32->64 on 64bit
0N/Astatic void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A if (src.first()->is_stack()) {
0N/A if (dst.first()->is_stack()) {
0N/A // stack to stack
0N/A __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
0N/A __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A } else {
0N/A // stack to reg
0N/A __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
0N/A }
0N/A } else if (dst.first()->is_stack()) {
0N/A // reg to stack
0N/A // Do we really have to sign extend???
0N/A // __ movslq(src.first()->as_Register(), src.first()->as_Register());
0N/A __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
0N/A } else {
0N/A // Do we really have to sign extend???
0N/A // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
0N/A if (dst.first() != src.first()) {
0N/A __ movq(dst.first()->as_Register(), src.first()->as_Register());
0N/A }
0N/A }
0N/A}
0N/A
3158N/Astatic void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
3158N/A if (src.first()->is_stack()) {
3158N/A if (dst.first()->is_stack()) {
3158N/A // stack to stack
3158N/A __ movq(rax, Address(rbp, reg2offset_in(src.first())));
3158N/A __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
3158N/A } else {
3158N/A // stack to reg
3158N/A __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
3158N/A }
3158N/A } else if (dst.first()->is_stack()) {
3158N/A // reg to stack
3158N/A __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
3158N/A } else {
3158N/A if (dst.first() != src.first()) {
3158N/A __ movq(dst.first()->as_Register(), src.first()->as_Register());
3158N/A }
3158N/A }
3158N/A}
0N/A
0N/A// An oop arg. Must pass a handle not the oop itself
0N/Astatic void object_move(MacroAssembler* masm,
0N/A OopMap* map,
0N/A int oop_handle_offset,
0N/A int framesize_in_slots,
0N/A VMRegPair src,
0N/A VMRegPair dst,
0N/A bool is_receiver,
0N/A int* receiver_offset) {
0N/A
0N/A // must pass a handle. First figure out the location we use as a handle
0N/A
0N/A Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
0N/A
0N/A // See if oop is NULL if it is we need no handle
0N/A
0N/A if (src.first()->is_stack()) {
0N/A
0N/A // Oop is already on the stack as an argument
0N/A int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
0N/A map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
0N/A if (is_receiver) {
0N/A *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
0N/A }
0N/A
304N/A __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
304N/A __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
0N/A // conditionally move a NULL
304N/A __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
0N/A } else {
0N/A
0N/A // Oop is in an a register we must store it to the space we reserve
0N/A // on the stack for oop_handles and pass a handle if oop is non-NULL
0N/A
0N/A const Register rOop = src.first()->as_Register();
0N/A int oop_slot;
0N/A if (rOop == j_rarg0)
0N/A oop_slot = 0;
0N/A else if (rOop == j_rarg1)
0N/A oop_slot = 1;
0N/A else if (rOop == j_rarg2)
0N/A oop_slot = 2;
0N/A else if (rOop == j_rarg3)
0N/A oop_slot = 3;
0N/A else if (rOop == j_rarg4)
0N/A oop_slot = 4;
0N/A else {
0N/A assert(rOop == j_rarg5, "wrong register");
0N/A oop_slot = 5;
0N/A }
0N/A
0N/A oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
0N/A int offset = oop_slot*VMRegImpl::stack_slot_size;
0N/A
0N/A map->set_oop(VMRegImpl::stack2reg(oop_slot));
0N/A // Store oop in handle area, may be NULL
304N/A __ movptr(Address(rsp, offset), rOop);
0N/A if (is_receiver) {
0N/A *receiver_offset = offset;
0N/A }
0N/A
304N/A __ cmpptr(rOop, (int32_t)NULL_WORD);
304N/A __ lea(rHandle, Address(rsp, offset));
0N/A // conditionally move a NULL from the handle area where it was just stored
304N/A __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
0N/A }
0N/A
0N/A // If arg is on the stack then place it otherwise it is already in correct reg.
0N/A if (dst.first()->is_stack()) {
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
0N/A }
0N/A}
0N/A
0N/A// A float arg may have to do float reg int reg conversion
0N/Astatic void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
0N/A
0N/A // The calling conventions assures us that each VMregpair is either
0N/A // all really one physical register or adjacent stack slots.
0N/A // This greatly simplifies the cases here compared to sparc.
0N/A
0N/A if (src.first()->is_stack()) {
0N/A if (dst.first()->is_stack()) {
0N/A __ movl(rax, Address(rbp, reg2offset_in(src.first())));
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A } else {
0N/A // stack to reg
0N/A assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
0N/A __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
0N/A }
0N/A } else if (dst.first()->is_stack()) {
0N/A // reg to stack
0N/A assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
0N/A __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
0N/A } else {
0N/A // reg to reg
0N/A // In theory these overlap but the ordering is such that this is likely a nop
0N/A if ( src.first() != dst.first()) {
0N/A __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
0N/A }
0N/A }
0N/A}
0N/A
0N/A// A long move
0N/Astatic void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A
0N/A // The calling conventions assures us that each VMregpair is either
0N/A // all really one physical register or adjacent stack slots.
0N/A // This greatly simplifies the cases here compared to sparc.
0N/A
0N/A if (src.is_single_phys_reg() ) {
0N/A if (dst.is_single_phys_reg()) {
0N/A if (dst.first() != src.first()) {
304N/A __ mov(dst.first()->as_Register(), src.first()->as_Register());
0N/A }
0N/A } else {
0N/A assert(dst.is_single_reg(), "not a stack pair");
0N/A __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
0N/A }
0N/A } else if (dst.is_single_phys_reg()) {
0N/A assert(src.is_single_reg(), "not a stack pair");
0N/A __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
0N/A } else {
0N/A assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
0N/A __ movq(rax, Address(rbp, reg2offset_in(src.first())));
0N/A __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A }
0N/A}
0N/A
0N/A// A double move
0N/Astatic void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A
0N/A // The calling conventions assures us that each VMregpair is either
0N/A // all really one physical register or adjacent stack slots.
0N/A // This greatly simplifies the cases here compared to sparc.
0N/A
0N/A if (src.is_single_phys_reg() ) {
0N/A if (dst.is_single_phys_reg()) {
0N/A // In theory these overlap but the ordering is such that this is likely a nop
0N/A if ( src.first() != dst.first()) {
0N/A __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
0N/A }
0N/A } else {
0N/A assert(dst.is_single_reg(), "not a stack pair");
0N/A __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
0N/A }
0N/A } else if (dst.is_single_phys_reg()) {
0N/A assert(src.is_single_reg(), "not a stack pair");
0N/A __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
0N/A } else {
0N/A assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
0N/A __ movq(rax, Address(rbp, reg2offset_in(src.first())));
0N/A __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
0N/A // We always ignore the frame_slots arg and just use the space just below frame pointer
0N/A // which by this time is free to use
0N/A switch (ret_type) {
0N/A case T_FLOAT:
0N/A __ movflt(Address(rbp, -wordSize), xmm0);
0N/A break;
0N/A case T_DOUBLE:
0N/A __ movdbl(Address(rbp, -wordSize), xmm0);
0N/A break;
0N/A case T_VOID: break;
0N/A default: {
304N/A __ movptr(Address(rbp, -wordSize), rax);
0N/A }
0N/A }
0N/A}
0N/A
0N/Avoid SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
0N/A // We always ignore the frame_slots arg and just use the space just below frame pointer
0N/A // which by this time is free to use
0N/A switch (ret_type) {
0N/A case T_FLOAT:
0N/A __ movflt(xmm0, Address(rbp, -wordSize));
0N/A break;
0N/A case T_DOUBLE:
0N/A __ movdbl(xmm0, Address(rbp, -wordSize));
0N/A break;
0N/A case T_VOID: break;
0N/A default: {
304N/A __ movptr(rax, Address(rbp, -wordSize));
0N/A }
0N/A }
0N/A}
0N/A
0N/Astatic void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
0N/A for ( int i = first_arg ; i < arg_count ; i++ ) {
0N/A if (args[i].first()->is_Register()) {
304N/A __ push(args[i].first()->as_Register());
0N/A } else if (args[i].first()->is_XMMRegister()) {
304N/A __ subptr(rsp, 2*wordSize);
0N/A __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
0N/A }
0N/A }
0N/A}
0N/A
0N/Astatic void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
0N/A for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
0N/A if (args[i].first()->is_Register()) {
304N/A __ pop(args[i].first()->as_Register());
0N/A } else if (args[i].first()->is_XMMRegister()) {
0N/A __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
304N/A __ addptr(rsp, 2*wordSize);
0N/A }
0N/A }
0N/A}
0N/A
3158N/A
3158N/Astatic void save_or_restore_arguments(MacroAssembler* masm,
3158N/A const int stack_slots,
3158N/A const int total_in_args,
3158N/A const int arg_save_area,
3158N/A OopMap* map,
3158N/A VMRegPair* in_regs,
3158N/A BasicType* in_sig_bt) {
3158N/A // if map is non-NULL then the code should store the values,
3158N/A // otherwise it should load them.
3158N/A int handle_index = 0;
3158N/A // Save down double word first
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
3158N/A int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A handle_index += 2;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
3158N/A } else {
3158N/A __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
3158N/A }
3158N/A }
3158N/A if (in_regs[i].first()->is_Register() &&
3158N/A (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
3158N/A int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A handle_index += 2;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
3158N/A if (in_sig_bt[i] == T_ARRAY) {
3158N/A map->set_oop(VMRegImpl::stack2reg(slot));;
3158N/A }
3158N/A } else {
3158N/A __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
3158N/A }
3158N/A }
3158N/A }
3158N/A // Save or restore single word registers
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A
3158N/A // Value is in an input register pass we must flush it to the stack
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A switch (in_sig_bt[i]) {
3158N/A case T_BOOLEAN:
3158N/A case T_CHAR:
3158N/A case T_BYTE:
3158N/A case T_SHORT:
3158N/A case T_INT:
3158N/A if (map != NULL) {
3158N/A __ movl(Address(rsp, offset), reg);
3158N/A } else {
3158N/A __ movl(reg, Address(rsp, offset));
3158N/A }
3158N/A break;
3158N/A case T_ARRAY:
3158N/A case T_LONG:
3158N/A // handled above
3158N/A break;
3158N/A case T_OBJECT:
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A if (in_sig_bt[i] == T_FLOAT) {
3158N/A int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
3158N/A } else {
3158N/A __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
3158N/A }
3158N/A }
3158N/A } else if (in_regs[i].first()->is_stack()) {
3158N/A if (in_sig_bt[i] == T_ARRAY && map != NULL) {
3158N/A int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
3158N/A map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
3158N/A }
3158N/A }
3158N/A }
3158N/A}
3158N/A
3158N/A
3158N/A// Check GC_locker::needs_gc and enter the runtime if it's true. This
3158N/A// keeps a new JNI critical region from starting until a GC has been
3158N/A// forced. Save down any oops in registers and describe them in an
3158N/A// OopMap.
3158N/Astatic void check_needs_gc_for_critical_native(MacroAssembler* masm,
3158N/A int stack_slots,
3158N/A int total_c_args,
3158N/A int total_in_args,
3158N/A int arg_save_area,
3158N/A OopMapSet* oop_maps,
3158N/A VMRegPair* in_regs,
3158N/A BasicType* in_sig_bt) {
3158N/A __ block_comment("check GC_locker::needs_gc");
3158N/A Label cont;
3158N/A __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
3158N/A __ jcc(Assembler::equal, cont);
3158N/A
3158N/A // Save down any incoming oops and call into the runtime to halt for a GC
3158N/A
3158N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, map, in_regs, in_sig_bt);
3158N/A
3158N/A address the_pc = __ pc();
3158N/A oop_maps->add_gc_map( __ offset(), map);
3158N/A __ set_last_Java_frame(rsp, noreg, the_pc);
3158N/A
3158N/A __ block_comment("block_for_jni_critical");
3158N/A __ movptr(c_rarg0, r15_thread);
3158N/A __ mov(r12, rsp); // remember sp
3158N/A __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
3158N/A __ andptr(rsp, -16); // align stack as required by ABI
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
3158N/A __ mov(rsp, r12); // restore sp
3158N/A __ reinit_heapbase();
3158N/A
3158N/A __ reset_last_Java_frame(false, true);
3158N/A
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, NULL, in_regs, in_sig_bt);
3158N/A
3158N/A __ bind(cont);
3158N/A#ifdef ASSERT
3158N/A if (StressCriticalJNINatives) {
3158N/A // Stress register saving
3158N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, map, in_regs, in_sig_bt);
3158N/A // Destroy argument registers
3158N/A for (int i = 0; i < total_in_args - 1; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A __ xorptr(reg, reg);
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
3158N/A } else if (in_regs[i].first()->is_FloatRegister()) {
3158N/A ShouldNotReachHere();
3158N/A } else if (in_regs[i].first()->is_stack()) {
3158N/A // Nothing to do
3158N/A } else {
3158N/A ShouldNotReachHere();
3158N/A }
3158N/A if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
3158N/A i++;
3158N/A }
3158N/A }
3158N/A
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, NULL, in_regs, in_sig_bt);
3158N/A }
3158N/A#endif
3158N/A}
3158N/A
3158N/A// Unpack an array argument into a pointer to the body and the length
3158N/A// if the array is non-null, otherwise pass 0 for both.
3158N/Astatic void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
3158N/A Register tmp_reg = rax;
3158N/A assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
3158N/A "possible collision");
3158N/A assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
3158N/A "possible collision");
3158N/A
3158N/A // Pass the length, ptr pair
3158N/A Label is_null, done;
3158N/A VMRegPair tmp;
3158N/A tmp.set_ptr(tmp_reg->as_VMReg());
3158N/A if (reg.first()->is_stack()) {
3158N/A // Load the arg up from the stack
3158N/A move_ptr(masm, reg, tmp);
3158N/A reg = tmp;
3158N/A }
3158N/A __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
3158N/A __ jccb(Assembler::equal, is_null);
3158N/A __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
3158N/A move_ptr(masm, tmp, body_arg);
3158N/A // load the length relative to the body.
3158N/A __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
3158N/A arrayOopDesc::base_offset_in_bytes(in_elem_type)));
3158N/A move32_64(masm, tmp, length_arg);
3158N/A __ jmpb(done);
3158N/A __ bind(is_null);
3158N/A // Pass zeros
3158N/A __ xorptr(tmp_reg, tmp_reg);
3158N/A move_ptr(masm, tmp, body_arg);
3158N/A move32_64(masm, tmp, length_arg);
3158N/A __ bind(done);
3158N/A}
3158N/A
0N/A// ---------------------------------------------------------------------------
0N/A// Generate a native wrapper for a given method. The method takes arguments
0N/A// in the Java compiled code convention, marshals them to the native
0N/A// convention (handlizes oops, etc), transitions to native, makes the call,
0N/A// returns to java state (possibly blocking), unhandlizes any result and
0N/A// returns.
0N/Anmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
0N/A methodHandle method,
2252N/A int compile_id,
0N/A int total_in_args,
0N/A int comp_args_on_stack,
0N/A BasicType *in_sig_bt,
0N/A VMRegPair *in_regs,
0N/A BasicType ret_type) {
3158N/A bool is_critical_native = true;
3158N/A address native_func = method->critical_native_function();
3158N/A if (native_func == NULL) {
3158N/A native_func = method->native_function();
3158N/A is_critical_native = false;
3158N/A }
3158N/A assert(native_func != NULL, "must have function");
3158N/A
0N/A // An OopMap for lock (and class if static)
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A intptr_t start = (intptr_t)__ pc();
0N/A
0N/A // We have received a description of where all the java arg are located
0N/A // on entry to the wrapper. We need to convert these args to where
0N/A // the jni function will expect them. To figure out where they go
0N/A // we convert the java signature to a C signature by inserting
0N/A // the hidden arguments as arg[0] and possibly arg[1] (static method)
0N/A
3158N/A int total_c_args = total_in_args;
3158N/A if (!is_critical_native) {
3158N/A total_c_args += 1;
3158N/A if (method->is_static()) {
3158N/A total_c_args++;
3158N/A }
3158N/A } else {
3158N/A for (int i = 0; i < total_in_args; i++) {
3158N/A if (in_sig_bt[i] == T_ARRAY) {
3158N/A total_c_args++;
3158N/A }
3158N/A }
0N/A }
0N/A
0N/A BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
3158N/A VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
3158N/A BasicType* in_elem_bt = NULL;
0N/A
0N/A int argc = 0;
3158N/A if (!is_critical_native) {
3158N/A out_sig_bt[argc++] = T_ADDRESS;
3158N/A if (method->is_static()) {
3158N/A out_sig_bt[argc++] = T_OBJECT;
3158N/A }
3158N/A
3158N/A for (int i = 0; i < total_in_args ; i++ ) {
3158N/A out_sig_bt[argc++] = in_sig_bt[i];
3158N/A }
3158N/A } else {
3158N/A Thread* THREAD = Thread::current();
3158N/A in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
3158N/A SignatureStream ss(method->signature());
3158N/A for (int i = 0; i < total_in_args ; i++ ) {
3158N/A if (in_sig_bt[i] == T_ARRAY) {
3158N/A // Arrays are passed as int, elem* pair
3158N/A out_sig_bt[argc++] = T_INT;
3158N/A out_sig_bt[argc++] = T_ADDRESS;
3158N/A Symbol* atype = ss.as_symbol(CHECK_NULL);
3158N/A const char* at = atype->as_C_string();
3158N/A if (strlen(at) == 2) {
3158N/A assert(at[0] == '[', "must be");
3158N/A switch (at[1]) {
3158N/A case 'B': in_elem_bt[i] = T_BYTE; break;
3158N/A case 'C': in_elem_bt[i] = T_CHAR; break;
3158N/A case 'D': in_elem_bt[i] = T_DOUBLE; break;
3158N/A case 'F': in_elem_bt[i] = T_FLOAT; break;
3158N/A case 'I': in_elem_bt[i] = T_INT; break;
3158N/A case 'J': in_elem_bt[i] = T_LONG; break;
3158N/A case 'S': in_elem_bt[i] = T_SHORT; break;
3158N/A case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A }
3158N/A } else {
3158N/A out_sig_bt[argc++] = in_sig_bt[i];
3158N/A in_elem_bt[i] = T_VOID;
3158N/A }
3158N/A if (in_sig_bt[i] != T_VOID) {
3158N/A assert(in_sig_bt[i] == ss.type(), "must match");
3158N/A ss.next();
3158N/A }
3158N/A }
0N/A }
0N/A
0N/A // Now figure out where the args must be stored and how much stack space
0N/A // they require.
0N/A int out_arg_slots;
0N/A out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
0N/A
0N/A // Compute framesize for the wrapper. We need to handlize all oops in
0N/A // incoming registers
0N/A
0N/A // Calculate the total number of stack slots we will need.
0N/A
0N/A // First count the abi requirement plus all of the outgoing args
0N/A int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
0N/A
0N/A // Now the space for the inbound oop handle area
3158N/A int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
3158N/A if (is_critical_native) {
3158N/A // Critical natives may have to call out so they need a save area
3158N/A // for register arguments.
3158N/A int double_slots = 0;
3158N/A int single_slots = 0;
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A switch (in_sig_bt[i]) {
3158N/A case T_ARRAY:
3158N/A case T_BOOLEAN:
3158N/A case T_BYTE:
3158N/A case T_SHORT:
3158N/A case T_CHAR:
3158N/A case T_INT: single_slots++; break;
3158N/A case T_LONG: double_slots++; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A switch (in_sig_bt[i]) {
3158N/A case T_FLOAT: single_slots++; break;
3158N/A case T_DOUBLE: double_slots++; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_FloatRegister()) {
3158N/A ShouldNotReachHere();
3158N/A }
3158N/A }
3158N/A total_save_slots = double_slots * 2 + single_slots;
3158N/A // align the save area
3158N/A if (double_slots != 0) {
3158N/A stack_slots = round_to(stack_slots, 2);
3158N/A }
3158N/A }
0N/A
0N/A int oop_handle_offset = stack_slots;
3158N/A stack_slots += total_save_slots;
0N/A
0N/A // Now any space we need for handlizing a klass if static method
0N/A
0N/A int klass_slot_offset = 0;
0N/A int klass_offset = -1;
0N/A int lock_slot_offset = 0;
0N/A bool is_static = false;
0N/A
0N/A if (method->is_static()) {
0N/A klass_slot_offset = stack_slots;
0N/A stack_slots += VMRegImpl::slots_per_word;
0N/A klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
0N/A is_static = true;
0N/A }
0N/A
0N/A // Plus a lock if needed
0N/A
0N/A if (method->is_synchronized()) {
0N/A lock_slot_offset = stack_slots;
0N/A stack_slots += VMRegImpl::slots_per_word;
0N/A }
0N/A
0N/A // Now a place (+2) to save return values or temp during shuffling
0N/A // + 4 for return address (which we own) and saved rbp
0N/A stack_slots += 6;
0N/A
0N/A // Ok The space we have allocated will look like:
0N/A //
0N/A //
0N/A // FP-> | |
0N/A // |---------------------|
0N/A // | 2 slots for moves |
0N/A // |---------------------|
0N/A // | lock box (if sync) |
0N/A // |---------------------| <- lock_slot_offset
0N/A // | klass (if static) |
0N/A // |---------------------| <- klass_slot_offset
0N/A // | oopHandle area |
0N/A // |---------------------| <- oop_handle_offset (6 java arg registers)
0N/A // | outbound memory |
0N/A // | based arguments |
0N/A // | |
0N/A // |---------------------|
0N/A // | |
0N/A // SP-> | out_preserved_slots |
0N/A //
0N/A //
0N/A
0N/A
0N/A // Now compute actual number of stack words we need rounding to make
0N/A // stack properly aligned.
524N/A stack_slots = round_to(stack_slots, StackAlignmentInSlots);
0N/A
0N/A int stack_size = stack_slots * VMRegImpl::stack_slot_size;
0N/A
0N/A // First thing make an ic check to see if we should even be here
0N/A
0N/A // We are free to use all registers as temps without saving them and
0N/A // restoring them except rbp. rbp is the only callee save register
0N/A // as far as the interpreter and the compiler(s) are concerned.
0N/A
0N/A
0N/A const Register ic_reg = rax;
0N/A const Register receiver = j_rarg0;
0N/A
3158N/A Label hit;
0N/A Label exception_pending;
0N/A
848N/A assert_different_registers(ic_reg, receiver, rscratch1);
0N/A __ verify_oop(receiver);
848N/A __ load_klass(rscratch1, receiver);
848N/A __ cmpq(ic_reg, rscratch1);
3158N/A __ jcc(Assembler::equal, hit);
0N/A
0N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A
0N/A // Verified entry point must be aligned
0N/A __ align(8);
0N/A
3158N/A __ bind(hit);
3158N/A
0N/A int vep_offset = ((intptr_t)__ pc()) - start;
0N/A
0N/A // The instruction at the verified entry point must be 5 bytes or longer
0N/A // because it can be patched on the fly by make_non_entrant. The stack bang
0N/A // instruction fits that requirement.
0N/A
0N/A // Generate stack overflow check
0N/A
0N/A if (UseStackBanging) {
0N/A __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
0N/A } else {
0N/A // need a 5 byte instruction to allow MT safe patching to non-entrant
0N/A __ fat_nop();
0N/A }
0N/A
0N/A // Generate a new frame for the wrapper.
0N/A __ enter();
0N/A // -2 because return address is already present and so is saved rbp
304N/A __ subptr(rsp, stack_size - 2*wordSize);
0N/A
3158N/A // Frame is now completed as far as size and linkage.
3158N/A int frame_complete = ((intptr_t)__ pc()) - start;
0N/A
0N/A#ifdef ASSERT
0N/A {
0N/A Label L;
304N/A __ mov(rax, rsp);
605N/A __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
304N/A __ cmpptr(rax, rsp);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("improperly aligned stack");
0N/A __ bind(L);
0N/A }
0N/A#endif /* ASSERT */
0N/A
0N/A
0N/A // We use r14 as the oop handle for the receiver/klass
0N/A // It is callee save so it survives the call to native
0N/A
0N/A const Register oop_handle_reg = r14;
0N/A
3158N/A if (is_critical_native) {
3158N/A check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
3158N/A oop_handle_offset, oop_maps, in_regs, in_sig_bt);
3158N/A }
0N/A
0N/A //
0N/A // We immediately shuffle the arguments so that any vm call we have to
0N/A // make from here on out (sync slow path, jvmti, etc.) we will have
0N/A // captured the oops from our caller and have a valid oopMap for
0N/A // them.
0N/A
0N/A // -----------------
0N/A // The Grand Shuffle
0N/A
0N/A // The Java calling convention is either equal (linux) or denser (win64) than the
0N/A // c calling convention. However the because of the jni_env argument the c calling
0N/A // convention always has at least one more (and two for static) arguments than Java.
0N/A // Therefore if we move the args from java -> c backwards then we will never have
0N/A // a register->register conflict and we don't have to build a dependency graph
0N/A // and figure out how to break any cycles.
0N/A //
0N/A
0N/A // Record esp-based slot for receiver on stack for non-static methods
0N/A int receiver_offset = -1;
0N/A
0N/A // This is a trick. We double the stack slots so we can claim
0N/A // the oops in the caller's frame. Since we are sure to have
0N/A // more args than the caller doubling is enough to make
0N/A // sure we can capture all the incoming oop args from the
0N/A // caller.
0N/A //
0N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
0N/A
0N/A // Mark location of rbp (someday)
0N/A // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
0N/A
0N/A // Use eax, ebx as temporaries during any memory-memory moves we have to do
0N/A // All inbound args are referenced based on rbp and all outbound args via rsp.
0N/A
0N/A
0N/A#ifdef ASSERT
0N/A bool reg_destroyed[RegisterImpl::number_of_registers];
0N/A bool freg_destroyed[XMMRegisterImpl::number_of_registers];
0N/A for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
0N/A reg_destroyed[r] = false;
0N/A }
0N/A for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
0N/A freg_destroyed[f] = false;
0N/A }
0N/A
0N/A#endif /* ASSERT */
0N/A
3158N/A if (is_critical_native) {
3158N/A // The mapping of Java and C arguments passed in registers are
3158N/A // rotated by one, which helps when passing arguments to regular
3158N/A // Java method but for critical natives that creates a cycle which
3158N/A // can cause arguments to be killed before they are used. Break
3158N/A // the cycle by moving the first argument into a temporary
3158N/A // register.
3158N/A for (int i = 0; i < total_c_args; i++) {
3158N/A if (in_regs[i].first()->is_Register() &&
3158N/A in_regs[i].first()->as_Register() == rdi) {
3158N/A __ mov(rbx, rdi);
3158N/A in_regs[i].set1(rbx->as_VMReg());
3158N/A }
3158N/A }
3158N/A }
3158N/A
3158N/A // This may iterate in two different directions depending on the
3158N/A // kind of native it is. The reason is that for regular JNI natives
3158N/A // the incoming and outgoing registers are offset upwards and for
3158N/A // critical natives they are offset down.
0N/A int c_arg = total_c_args - 1;
3158N/A int stride = -1;
3158N/A int init = total_in_args - 1;
3158N/A if (is_critical_native) {
3158N/A // stride forwards
3158N/A c_arg = 0;
3158N/A stride = 1;
3158N/A init = 0;
3158N/A }
3158N/A for (int i = init, count = 0; count < total_in_args; i += stride, c_arg += stride, count++ ) {
0N/A#ifdef ASSERT
0N/A if (in_regs[i].first()->is_Register()) {
0N/A assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
0N/A } else if (in_regs[i].first()->is_XMMRegister()) {
0N/A assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
0N/A }
0N/A if (out_regs[c_arg].first()->is_Register()) {
0N/A reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
0N/A } else if (out_regs[c_arg].first()->is_XMMRegister()) {
0N/A freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
0N/A }
0N/A#endif /* ASSERT */
0N/A switch (in_sig_bt[i]) {
0N/A case T_ARRAY:
3158N/A if (is_critical_native) {
3158N/A unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
3158N/A c_arg++;
3158N/A#ifdef ASSERT
3158N/A if (out_regs[c_arg].first()->is_Register()) {
3158N/A reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
3158N/A } else if (out_regs[c_arg].first()->is_XMMRegister()) {
3158N/A freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
3158N/A }
3158N/A#endif
3158N/A break;
3158N/A }
0N/A case T_OBJECT:
3158N/A assert(!is_critical_native, "no oop arguments");
0N/A object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
0N/A ((i == 0) && (!is_static)),
0N/A &receiver_offset);
0N/A break;
0N/A case T_VOID:
0N/A break;
0N/A
0N/A case T_FLOAT:
0N/A float_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_DOUBLE:
0N/A assert( i + 1 < total_in_args &&
0N/A in_sig_bt[i + 1] == T_VOID &&
0N/A out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
0N/A double_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_LONG :
0N/A long_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
0N/A
0N/A default:
0N/A move32_64(masm, in_regs[i], out_regs[c_arg]);
0N/A }
0N/A }
0N/A
0N/A // point c_arg at the first arg that is already loaded in case we
0N/A // need to spill before we call out
0N/A c_arg++;
0N/A
0N/A // Pre-load a static method's oop into r14. Used both by locking code and
0N/A // the normal JNI call code.
3158N/A if (method->is_static() && !is_critical_native) {
0N/A
0N/A // load oop into a register
0N/A __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
0N/A
0N/A // Now handlize the static class mirror it's known not-null.
304N/A __ movptr(Address(rsp, klass_offset), oop_handle_reg);
0N/A map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
0N/A
0N/A // Now get the handle
304N/A __ lea(oop_handle_reg, Address(rsp, klass_offset));
0N/A // store the klass handle as second argument
304N/A __ movptr(c_rarg1, oop_handle_reg);
0N/A // and protect the arg if we must spill
0N/A c_arg--;
0N/A }
0N/A
0N/A // Change state to native (we save the return address in the thread, since it might not
0N/A // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
0N/A // points into the right code segment. It does not have to be the correct return pc.
0N/A // We use the same pc/oopMap repeatedly when we call out
0N/A
0N/A intptr_t the_pc = (intptr_t) __ pc();
0N/A oop_maps->add_gc_map(the_pc - start, map);
0N/A
0N/A __ set_last_Java_frame(rsp, noreg, (address)the_pc);
0N/A
0N/A
0N/A // We have all of the arguments setup at this point. We must not touch any register
0N/A // argument registers at this point (what if we save/restore them there are no oop?
0N/A
0N/A {
0N/A SkipIfEqual skip(masm, &DTraceMethodProbes, false);
0N/A // protect the args we've loaded
0N/A save_args(masm, total_c_args, c_arg, out_regs);
0N/A __ movoop(c_rarg1, JNIHandles::make_local(method()));
0N/A __ call_VM_leaf(
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
0N/A r15_thread, c_rarg1);
0N/A restore_args(masm, total_c_args, c_arg, out_regs);
0N/A }
0N/A
610N/A // RedefineClasses() tracing support for obsolete method entry
610N/A if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
610N/A // protect the args we've loaded
610N/A save_args(masm, total_c_args, c_arg, out_regs);
610N/A __ movoop(c_rarg1, JNIHandles::make_local(method()));
610N/A __ call_VM_leaf(
610N/A CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
610N/A r15_thread, c_rarg1);
610N/A restore_args(masm, total_c_args, c_arg, out_regs);
610N/A }
610N/A
0N/A // Lock a synchronized method
0N/A
0N/A // Register definitions used by locking and unlocking
0N/A
0N/A const Register swap_reg = rax; // Must use rax for cmpxchg instruction
0N/A const Register obj_reg = rbx; // Will contain the oop
0N/A const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
0N/A const Register old_hdr = r13; // value of old header at unlock time
0N/A
0N/A Label slow_path_lock;
0N/A Label lock_done;
0N/A
0N/A if (method->is_synchronized()) {
3158N/A assert(!is_critical_native, "unhandled");
0N/A
0N/A
0N/A const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
0N/A
0N/A // Get the handle (the 2nd argument)
304N/A __ mov(oop_handle_reg, c_rarg1);
0N/A
0N/A // Get address of the box
0N/A
304N/A __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
0N/A
0N/A // Load the oop from the handle
304N/A __ movptr(obj_reg, Address(oop_handle_reg, 0));
0N/A
0N/A if (UseBiasedLocking) {
0N/A __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
0N/A }
0N/A
0N/A // Load immediate 1 into swap_reg %rax
0N/A __ movl(swap_reg, 1);
0N/A
0N/A // Load (object->mark() | 1) into swap_reg %rax
304N/A __ orptr(swap_reg, Address(obj_reg, 0));
0N/A
0N/A // Save (object->mark() | 1) into BasicLock's displaced header
304N/A __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
0N/A
0N/A if (os::is_MP()) {
0N/A __ lock();
0N/A }
0N/A
0N/A // src -> dest iff dest == rax else rax <- dest
304N/A __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
0N/A __ jcc(Assembler::equal, lock_done);
0N/A
0N/A // Hmm should this move to the slow path code area???
0N/A
0N/A // Test if the oopMark is an obvious stack pointer, i.e.,
0N/A // 1) (mark & 3) == 0, and
0N/A // 2) rsp <= mark < mark + os::pagesize()
0N/A // These 3 tests can be done by evaluating the following
0N/A // expression: ((mark - rsp) & (3 - os::vm_page_size())),
0N/A // assuming both stack pointer and pagesize have their
0N/A // least significant 2 bits clear.
0N/A // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
0N/A
304N/A __ subptr(swap_reg, rsp);
304N/A __ andptr(swap_reg, 3 - os::vm_page_size());
0N/A
0N/A // Save the test result, for recursive case, the result is zero
304N/A __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
0N/A __ jcc(Assembler::notEqual, slow_path_lock);
0N/A
0N/A // Slow path will re-enter here
0N/A
0N/A __ bind(lock_done);
0N/A }
0N/A
0N/A
0N/A // Finally just about ready to make the JNI call
0N/A
0N/A
0N/A // get JNIEnv* which is first argument to native
3158N/A if (!is_critical_native) {
3158N/A __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
3158N/A }
0N/A
0N/A // Now set thread in native
304N/A __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
0N/A
3158N/A __ call(RuntimeAddress(native_func));
0N/A
0N/A // Either restore the MXCSR register after returning from the JNI Call
0N/A // or verify that it wasn't changed.
0N/A if (RestoreMXCSROnJNICalls) {
304N/A __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
0N/A
0N/A }
0N/A else if (CheckJNICalls ) {
304N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
0N/A }
0N/A
0N/A
0N/A // Unpack native results.
0N/A switch (ret_type) {
0N/A case T_BOOLEAN: __ c2bool(rax); break;
0N/A case T_CHAR : __ movzwl(rax, rax); break;
0N/A case T_BYTE : __ sign_extend_byte (rax); break;
0N/A case T_SHORT : __ sign_extend_short(rax); break;
0N/A case T_INT : /* nothing to do */ break;
0N/A case T_DOUBLE :
0N/A case T_FLOAT :
0N/A // Result is in xmm0 we'll save as needed
0N/A break;
0N/A case T_ARRAY: // Really a handle
0N/A case T_OBJECT: // Really a handle
0N/A break; // can't de-handlize until after safepoint check
0N/A case T_VOID: break;
0N/A case T_LONG: break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A
0N/A // Switch thread to "native transition" state before reading the synchronization state.
0N/A // This additional state is necessary because reading and testing the synchronization
0N/A // state is not atomic w.r.t. GC, as this scenario demonstrates:
0N/A // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
0N/A // VM thread changes sync state to synchronizing and suspends threads for GC.
0N/A // Thread A is resumed to finish this native method, but doesn't block here since it
0N/A // didn't see any synchronization is progress, and escapes.
304N/A __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
0N/A
0N/A if(os::is_MP()) {
0N/A if (UseMembar) {
0N/A // Force this write out before the read below
0N/A __ membar(Assembler::Membar_mask_bits(
0N/A Assembler::LoadLoad | Assembler::LoadStore |
0N/A Assembler::StoreLoad | Assembler::StoreStore));
0N/A } else {
0N/A // Write serialization page so VM thread can do a pseudo remote membar.
0N/A // We use the current thread pointer to calculate a thread specific
0N/A // offset to write to within the page. This minimizes bus traffic
0N/A // due to cache line collision.
0N/A __ serialize_memory(r15_thread, rcx);
0N/A }
0N/A }
0N/A
3158N/A Label after_transition;
0N/A
0N/A // check for safepoint operation in progress and/or pending suspend requests
0N/A {
0N/A Label Continue;
0N/A
0N/A __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
0N/A SafepointSynchronize::_not_synchronized);
0N/A
0N/A Label L;
0N/A __ jcc(Assembler::notEqual, L);
0N/A __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
0N/A __ jcc(Assembler::equal, Continue);
0N/A __ bind(L);
0N/A
0N/A // Don't use call_VM as it will see a possible pending exception and forward it
0N/A // and never return here preventing us from clearing _last_native_pc down below.
0N/A // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
0N/A // preserved and correspond to the bcp/locals pointers. So we do a runtime call
0N/A // by hand.
0N/A //
0N/A save_native_result(masm, ret_type, stack_slots);
304N/A __ mov(c_rarg0, r15_thread);
304N/A __ mov(r12, rsp); // remember sp
304N/A __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
304N/A __ andptr(rsp, -16); // align stack as required by ABI
3158N/A if (!is_critical_native) {
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
3158N/A } else {
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
3158N/A }
304N/A __ mov(rsp, r12); // restore sp
113N/A __ reinit_heapbase();
0N/A // Restore any method result value
0N/A restore_native_result(masm, ret_type, stack_slots);
3158N/A
3158N/A if (is_critical_native) {
3158N/A // The call above performed the transition to thread_in_Java so
3158N/A // skip the transition logic below.
3158N/A __ jmpb(after_transition);
3158N/A }
3158N/A
0N/A __ bind(Continue);
0N/A }
0N/A
0N/A // change thread state
0N/A __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
3158N/A __ bind(after_transition);
0N/A
0N/A Label reguard;
0N/A Label reguard_done;
0N/A __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
0N/A __ jcc(Assembler::equal, reguard);
0N/A __ bind(reguard_done);
0N/A
0N/A // native result if any is live
0N/A
0N/A // Unlock
0N/A Label unlock_done;
0N/A Label slow_path_unlock;
0N/A if (method->is_synchronized()) {
0N/A
0N/A // Get locked oop from the handle we passed to jni
304N/A __ movptr(obj_reg, Address(oop_handle_reg, 0));
0N/A
0N/A Label done;
0N/A
0N/A if (UseBiasedLocking) {
0N/A __ biased_locking_exit(obj_reg, old_hdr, done);
0N/A }
0N/A
0N/A // Simple recursive lock?
0N/A
304N/A __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, done);
0N/A
0N/A // Must save rax if if it is live now because cmpxchg must use it
0N/A if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A
0N/A // get address of the stack lock
304N/A __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
0N/A // get old displaced header
304N/A __ movptr(old_hdr, Address(rax, 0));
0N/A
0N/A // Atomic swap old header if oop still contains the stack lock
0N/A if (os::is_MP()) {
0N/A __ lock();
0N/A }
304N/A __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
0N/A __ jcc(Assembler::notEqual, slow_path_unlock);
0N/A
0N/A // slow path re-enters here
0N/A __ bind(unlock_done);
0N/A if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A __ bind(done);
0N/A
0N/A }
0N/A {
0N/A SkipIfEqual skip(masm, &DTraceMethodProbes, false);
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A __ movoop(c_rarg1, JNIHandles::make_local(method()));
0N/A __ call_VM_leaf(
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
0N/A r15_thread, c_rarg1);
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A __ reset_last_Java_frame(false, true);
0N/A
0N/A // Unpack oop result
0N/A if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
0N/A Label L;
304N/A __ testptr(rax, rax);
0N/A __ jcc(Assembler::zero, L);
304N/A __ movptr(rax, Address(rax, 0));
0N/A __ bind(L);
0N/A __ verify_oop(rax);
0N/A }
0N/A
3158N/A if (!is_critical_native) {
3158N/A // reset handle block
3158N/A __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
3158N/A __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
3158N/A }
0N/A
0N/A // pop our frame
0N/A
0N/A __ leave();
0N/A
3158N/A if (!is_critical_native) {
3158N/A // Any exception pending?
3158N/A __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
3158N/A __ jcc(Assembler::notEqual, exception_pending);
3158N/A }
0N/A
0N/A // Return
0N/A
0N/A __ ret(0);
0N/A
0N/A // Unexpected paths are out of line and go here
0N/A
3158N/A if (!is_critical_native) {
3158N/A // forward the exception
3158N/A __ bind(exception_pending);
3158N/A
3158N/A // and forward the exception
3158N/A __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3158N/A }
0N/A
0N/A // Slow path locking & unlocking
0N/A if (method->is_synchronized()) {
0N/A
0N/A // BEGIN Slow path lock
0N/A __ bind(slow_path_lock);
0N/A
0N/A // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
0N/A // args are (oop obj, BasicLock* lock, JavaThread* thread)
0N/A
0N/A // protect the args we've loaded
0N/A save_args(masm, total_c_args, c_arg, out_regs);
0N/A
304N/A __ mov(c_rarg0, obj_reg);
304N/A __ mov(c_rarg1, lock_reg);
304N/A __ mov(c_rarg2, r15_thread);
0N/A
0N/A // Not a leaf but we have last_Java_frame setup as we want
0N/A __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
0N/A restore_args(masm, total_c_args, c_arg, out_regs);
0N/A
0N/A#ifdef ASSERT
0N/A { Label L;
304N/A __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("no pending exception allowed on exit from monitorenter");
0N/A __ bind(L);
0N/A }
0N/A#endif
0N/A __ jmp(lock_done);
0N/A
0N/A // END Slow path lock
0N/A
0N/A // BEGIN Slow path unlock
0N/A __ bind(slow_path_unlock);
0N/A
0N/A // If we haven't already saved the native result we must save it now as xmm registers
0N/A // are still exposed.
0N/A
0N/A if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
304N/A __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
304N/A
304N/A __ mov(c_rarg0, obj_reg);
304N/A __ mov(r12, rsp); // remember sp
304N/A __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
304N/A __ andptr(rsp, -16); // align stack as required by ABI
0N/A
0N/A // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
0N/A // NOTE that obj_reg == rbx currently
304N/A __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
304N/A __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
0N/A
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
304N/A __ mov(rsp, r12); // restore sp
113N/A __ reinit_heapbase();
0N/A#ifdef ASSERT
0N/A {
0N/A Label L;
304N/A __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
0N/A __ bind(L);
0N/A }
0N/A#endif /* ASSERT */
0N/A
304N/A __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
0N/A
0N/A if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A __ jmp(unlock_done);
0N/A
0N/A // END Slow path unlock
0N/A
0N/A } // synchronized
0N/A
0N/A // SLOW PATH Reguard the stack if needed
0N/A
0N/A __ bind(reguard);
0N/A save_native_result(masm, ret_type, stack_slots);
304N/A __ mov(r12, rsp); // remember sp
304N/A __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
304N/A __ andptr(rsp, -16); // align stack as required by ABI
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
304N/A __ mov(rsp, r12); // restore sp
113N/A __ reinit_heapbase();
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A // and continue
0N/A __ jmp(reguard_done);
0N/A
0N/A
0N/A
0N/A __ flush();
0N/A
0N/A nmethod *nm = nmethod::new_native_nmethod(method,
2252N/A compile_id,
0N/A masm->code(),
0N/A vep_offset,
0N/A frame_complete,
0N/A stack_slots / VMRegImpl::slots_per_word,
0N/A (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
0N/A in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
0N/A oop_maps);
3158N/A
3158N/A if (is_critical_native) {
3158N/A nm->set_lazy_critical_native(true);
3158N/A }
3158N/A
0N/A return nm;
0N/A
0N/A}
0N/A
116N/A#ifdef HAVE_DTRACE_H
116N/A// ---------------------------------------------------------------------------
116N/A// Generate a dtrace nmethod for a given signature. The method takes arguments
116N/A// in the Java compiled code convention, marshals them to the native
116N/A// abi and then leaves nops at the position you would expect to call a native
116N/A// function. When the probe is enabled the nops are replaced with a trap
116N/A// instruction that dtrace inserts and the trace will cause a notification
116N/A// to dtrace.
116N/A//
116N/A// The probes are only able to take primitive types and java/lang/String as
116N/A// arguments. No other java types are allowed. Strings are converted to utf8
116N/A// strings so that from dtrace point of view java strings are converted to C
116N/A// strings. There is an arbitrary fixed limit on the total space that a method
116N/A// can use for converting the strings. (256 chars per string in the signature).
116N/A// So any java string larger then this is truncated.
116N/A
116N/Astatic int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
116N/Astatic bool offsets_initialized = false;
116N/A
116N/A
116N/Anmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
116N/A methodHandle method) {
116N/A
116N/A
116N/A // generate_dtrace_nmethod is guarded by a mutex so we are sure to
116N/A // be single threaded in this method.
116N/A assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
116N/A
116N/A if (!offsets_initialized) {
116N/A fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
116N/A fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
116N/A fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
116N/A fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
116N/A fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
116N/A fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
116N/A
116N/A fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
116N/A fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
116N/A fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
116N/A fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
116N/A fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
116N/A fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
116N/A fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
116N/A fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
116N/A
116N/A offsets_initialized = true;
116N/A }
116N/A // Fill in the signature array, for the calling-convention call.
116N/A int total_args_passed = method->size_of_parameters();
116N/A
116N/A BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
116N/A VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
116N/A
116N/A // The signature we are going to use for the trap that dtrace will see
116N/A // java/lang/String is converted. We drop "this" and any other object
116N/A // is converted to NULL. (A one-slot java/lang/Long object reference
116N/A // is converted to a two-slot long, which is why we double the allocation).
116N/A BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
116N/A VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
116N/A
116N/A int i=0;
116N/A int total_strings = 0;
116N/A int first_arg_to_pass = 0;
116N/A int total_c_args = 0;
116N/A
116N/A // Skip the receiver as dtrace doesn't want to see it
116N/A if( !method->is_static() ) {
116N/A in_sig_bt[i++] = T_OBJECT;
116N/A first_arg_to_pass = 1;
116N/A }
116N/A
116N/A // We need to convert the java args to where a native (non-jni) function
116N/A // would expect them. To figure out where they go we convert the java
116N/A // signature to a C signature.
116N/A
116N/A SignatureStream ss(method->signature());
116N/A for ( ; !ss.at_return_type(); ss.next()) {
116N/A BasicType bt = ss.type();
116N/A in_sig_bt[i++] = bt; // Collect remaining bits of signature
116N/A out_sig_bt[total_c_args++] = bt;
116N/A if( bt == T_OBJECT) {
2062N/A Symbol* s = ss.as_symbol_or_null(); // symbol is created
116N/A if (s == vmSymbols::java_lang_String()) {
116N/A total_strings++;
116N/A out_sig_bt[total_c_args-1] = T_ADDRESS;
116N/A } else if (s == vmSymbols::java_lang_Boolean() ||
116N/A s == vmSymbols::java_lang_Character() ||
116N/A s == vmSymbols::java_lang_Byte() ||
116N/A s == vmSymbols::java_lang_Short() ||
116N/A s == vmSymbols::java_lang_Integer() ||
116N/A s == vmSymbols::java_lang_Float()) {
116N/A out_sig_bt[total_c_args-1] = T_INT;
116N/A } else if (s == vmSymbols::java_lang_Long() ||
116N/A s == vmSymbols::java_lang_Double()) {
116N/A out_sig_bt[total_c_args-1] = T_LONG;
116N/A out_sig_bt[total_c_args++] = T_VOID;
116N/A }
116N/A } else if ( bt == T_LONG || bt == T_DOUBLE ) {
116N/A in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
116N/A // We convert double to long
116N/A out_sig_bt[total_c_args-1] = T_LONG;
116N/A out_sig_bt[total_c_args++] = T_VOID;
116N/A } else if ( bt == T_FLOAT) {
116N/A // We convert float to int
116N/A out_sig_bt[total_c_args-1] = T_INT;
116N/A }
116N/A }
116N/A
116N/A assert(i==total_args_passed, "validly parsed signature");
116N/A
116N/A // Now get the compiled-Java layout as input arguments
116N/A int comp_args_on_stack;
116N/A comp_args_on_stack = SharedRuntime::java_calling_convention(
116N/A in_sig_bt, in_regs, total_args_passed, false);
116N/A
116N/A // Now figure out where the args must be stored and how much stack space
116N/A // they require (neglecting out_preserve_stack_slots but space for storing
116N/A // the 1st six register arguments). It's weird see int_stk_helper.
116N/A
116N/A int out_arg_slots;
116N/A out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
116N/A
116N/A // Calculate the total number of stack slots we will need.
116N/A
116N/A // First count the abi requirement plus all of the outgoing args
116N/A int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
116N/A
116N/A // Now space for the string(s) we must convert
116N/A int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
116N/A for (i = 0; i < total_strings ; i++) {
116N/A string_locs[i] = stack_slots;
116N/A stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
116N/A }
116N/A
116N/A // Plus the temps we might need to juggle register args
116N/A // regs take two slots each
116N/A stack_slots += (Argument::n_int_register_parameters_c +
116N/A Argument::n_float_register_parameters_c) * 2;
116N/A
116N/A
116N/A // + 4 for return address (which we own) and saved rbp,
116N/A
116N/A stack_slots += 4;
116N/A
116N/A // Ok The space we have allocated will look like:
116N/A //
116N/A //
116N/A // FP-> | |
116N/A // |---------------------|
116N/A // | string[n] |
116N/A // |---------------------| <- string_locs[n]
116N/A // | string[n-1] |
116N/A // |---------------------| <- string_locs[n-1]
116N/A // | ... |
116N/A // | ... |
116N/A // |---------------------| <- string_locs[1]
116N/A // | string[0] |
116N/A // |---------------------| <- string_locs[0]
116N/A // | outbound memory |
116N/A // | based arguments |
116N/A // | |
116N/A // |---------------------|
116N/A // | |
116N/A // SP-> | out_preserved_slots |
116N/A //
116N/A //
116N/A
116N/A // Now compute actual number of stack words we need rounding to make
116N/A // stack properly aligned.
116N/A stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
116N/A
116N/A int stack_size = stack_slots * VMRegImpl::stack_slot_size;
116N/A
116N/A intptr_t start = (intptr_t)__ pc();
116N/A
116N/A // First thing make an ic check to see if we should even be here
116N/A
116N/A // We are free to use all registers as temps without saving them and
116N/A // restoring them except rbp. rbp, is the only callee save register
116N/A // as far as the interpreter and the compiler(s) are concerned.
116N/A
116N/A const Register ic_reg = rax;
116N/A const Register receiver = rcx;
116N/A Label hit;
116N/A Label exception_pending;
116N/A
116N/A
116N/A __ verify_oop(receiver);
116N/A __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
116N/A __ jcc(Assembler::equal, hit);
116N/A
116N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
116N/A
116N/A // verified entry must be aligned for code patching.
116N/A // and the first 5 bytes must be in the same cache line
116N/A // if we align at 8 then we will be sure 5 bytes are in the same line
116N/A __ align(8);
116N/A
116N/A __ bind(hit);
116N/A
116N/A int vep_offset = ((intptr_t)__ pc()) - start;
116N/A
116N/A
116N/A // The instruction at the verified entry point must be 5 bytes or longer
116N/A // because it can be patched on the fly by make_non_entrant. The stack bang
116N/A // instruction fits that requirement.
116N/A
116N/A // Generate stack overflow check
116N/A
116N/A if (UseStackBanging) {
116N/A if (stack_size <= StackShadowPages*os::vm_page_size()) {
116N/A __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
116N/A } else {
116N/A __ movl(rax, stack_size);
116N/A __ bang_stack_size(rax, rbx);
116N/A }
116N/A } else {
116N/A // need a 5 byte instruction to allow MT safe patching to non-entrant
116N/A __ fat_nop();
116N/A }
116N/A
116N/A assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
116N/A "valid size for make_non_entrant");
116N/A
116N/A // Generate a new frame for the wrapper.
116N/A __ enter();
116N/A
116N/A // -4 because return address is already present and so is saved rbp,
116N/A if (stack_size - 2*wordSize != 0) {
116N/A __ subq(rsp, stack_size - 2*wordSize);
116N/A }
116N/A
116N/A // Frame is now completed as far a size and linkage.
116N/A
116N/A int frame_complete = ((intptr_t)__ pc()) - start;
116N/A
116N/A int c_arg, j_arg;
116N/A
116N/A // State of input register args
116N/A
116N/A bool live[ConcreteRegisterImpl::number_of_registers];
116N/A
116N/A live[j_rarg0->as_VMReg()->value()] = false;
116N/A live[j_rarg1->as_VMReg()->value()] = false;
116N/A live[j_rarg2->as_VMReg()->value()] = false;
116N/A live[j_rarg3->as_VMReg()->value()] = false;
116N/A live[j_rarg4->as_VMReg()->value()] = false;
116N/A live[j_rarg5->as_VMReg()->value()] = false;
116N/A
116N/A live[j_farg0->as_VMReg()->value()] = false;
116N/A live[j_farg1->as_VMReg()->value()] = false;
116N/A live[j_farg2->as_VMReg()->value()] = false;
116N/A live[j_farg3->as_VMReg()->value()] = false;
116N/A live[j_farg4->as_VMReg()->value()] = false;
116N/A live[j_farg5->as_VMReg()->value()] = false;
116N/A live[j_farg6->as_VMReg()->value()] = false;
116N/A live[j_farg7->as_VMReg()->value()] = false;
116N/A
116N/A
116N/A bool rax_is_zero = false;
116N/A
116N/A // All args (except strings) destined for the stack are moved first
116N/A for (j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A j_arg < total_args_passed ; j_arg++, c_arg++ ) {
116N/A VMRegPair src = in_regs[j_arg];
116N/A VMRegPair dst = out_regs[c_arg];
116N/A
116N/A // Get the real reg value or a dummy (rsp)
116N/A
116N/A int src_reg = src.first()->is_reg() ?
116N/A src.first()->value() :
116N/A rsp->as_VMReg()->value();
116N/A
116N/A bool useless = in_sig_bt[j_arg] == T_ARRAY ||
116N/A (in_sig_bt[j_arg] == T_OBJECT &&
116N/A out_sig_bt[c_arg] != T_INT &&
116N/A out_sig_bt[c_arg] != T_ADDRESS &&
116N/A out_sig_bt[c_arg] != T_LONG);
116N/A
116N/A live[src_reg] = !useless;
116N/A
116N/A if (dst.first()->is_stack()) {
116N/A
116N/A // Even though a string arg in a register is still live after this loop
116N/A // after the string conversion loop (next) it will be dead so we take
116N/A // advantage of that now for simpler code to manage live.
116N/A
116N/A live[src_reg] = false;
116N/A switch (in_sig_bt[j_arg]) {
116N/A
116N/A case T_ARRAY:
116N/A case T_OBJECT:
116N/A {
116N/A Address stack_dst(rsp, reg2offset_out(dst.first()));
116N/A
116N/A if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
116N/A // need to unbox a one-word value
116N/A Register in_reg = rax;
116N/A if ( src.first()->is_reg() ) {
116N/A in_reg = src.first()->as_Register();
116N/A } else {
116N/A __ movq(rax, Address(rbp, reg2offset_in(src.first())));
116N/A rax_is_zero = false;
116N/A }
116N/A Label skipUnbox;
116N/A __ movptr(Address(rsp, reg2offset_out(dst.first())),
116N/A (int32_t)NULL_WORD);
116N/A __ testq(in_reg, in_reg);
116N/A __ jcc(Assembler::zero, skipUnbox);
116N/A
165N/A BasicType bt = out_sig_bt[c_arg];
165N/A int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
116N/A Address src1(in_reg, box_offset);
165N/A if ( bt == T_LONG ) {
116N/A __ movq(in_reg, src1);
116N/A __ movq(stack_dst, in_reg);
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // skip over T_VOID to keep the loop indices in sync
116N/A } else {
116N/A __ movl(in_reg, src1);
116N/A __ movl(stack_dst, in_reg);
116N/A }
116N/A
116N/A __ bind(skipUnbox);
116N/A } else if (out_sig_bt[c_arg] != T_ADDRESS) {
116N/A // Convert the arg to NULL
116N/A if (!rax_is_zero) {
116N/A __ xorq(rax, rax);
116N/A rax_is_zero = true;
116N/A }
116N/A __ movq(stack_dst, rax);
116N/A }
116N/A }
116N/A break;
116N/A
116N/A case T_VOID:
116N/A break;
116N/A
116N/A case T_FLOAT:
116N/A // This does the right thing since we know it is destined for the
116N/A // stack
116N/A float_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_DOUBLE:
116N/A // This does the right thing since we know it is destined for the
116N/A // stack
116N/A double_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_LONG :
116N/A long_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
116N/A
116N/A default:
116N/A move32_64(masm, src, dst);
116N/A }
116N/A }
116N/A
116N/A }
116N/A
116N/A // If we have any strings we must store any register based arg to the stack
116N/A // This includes any still live xmm registers too.
116N/A
116N/A int sid = 0;
116N/A
116N/A if (total_strings > 0 ) {
116N/A for (j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A j_arg < total_args_passed ; j_arg++, c_arg++ ) {
116N/A VMRegPair src = in_regs[j_arg];
116N/A VMRegPair dst = out_regs[c_arg];
116N/A
116N/A if (src.first()->is_reg()) {
116N/A Address src_tmp(rbp, fp_offset[src.first()->value()]);
116N/A
116N/A // string oops were left untouched by the previous loop even if the
116N/A // eventual (converted) arg is destined for the stack so park them
116N/A // away now (except for first)
116N/A
116N/A if (out_sig_bt[c_arg] == T_ADDRESS) {
116N/A Address utf8_addr = Address(
116N/A rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
116N/A if (sid != 1) {
116N/A // The first string arg won't be killed until after the utf8
116N/A // conversion
116N/A __ movq(utf8_addr, src.first()->as_Register());
116N/A }
116N/A } else if (dst.first()->is_reg()) {
116N/A if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
116N/A
116N/A // Convert the xmm register to an int and store it in the reserved
116N/A // location for the eventual c register arg
116N/A XMMRegister f = src.first()->as_XMMRegister();
116N/A if (in_sig_bt[j_arg] == T_FLOAT) {
116N/A __ movflt(src_tmp, f);
116N/A } else {
116N/A __ movdbl(src_tmp, f);
116N/A }
116N/A } else {
116N/A // If the arg is an oop type we don't support don't bother to store
116N/A // it remember string was handled above.
116N/A bool useless = in_sig_bt[j_arg] == T_ARRAY ||
116N/A (in_sig_bt[j_arg] == T_OBJECT &&
116N/A out_sig_bt[c_arg] != T_INT &&
116N/A out_sig_bt[c_arg] != T_LONG);
116N/A
116N/A if (!useless) {
116N/A __ movq(src_tmp, src.first()->as_Register());
116N/A }
116N/A }
116N/A }
116N/A }
116N/A if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // skip over T_VOID to keep the loop indices in sync
116N/A }
116N/A }
116N/A
116N/A // Now that the volatile registers are safe, convert all the strings
116N/A sid = 0;
116N/A
116N/A for (j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A j_arg < total_args_passed ; j_arg++, c_arg++ ) {
116N/A if (out_sig_bt[c_arg] == T_ADDRESS) {
116N/A // It's a string
116N/A Address utf8_addr = Address(
116N/A rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
116N/A // The first string we find might still be in the original java arg
116N/A // register
116N/A
116N/A VMReg src = in_regs[j_arg].first();
116N/A
116N/A // We will need to eventually save the final argument to the trap
116N/A // in the von-volatile location dedicated to src. This is the offset
116N/A // from fp we will use.
116N/A int src_off = src->is_reg() ?
116N/A fp_offset[src->value()] : reg2offset_in(src);
116N/A
116N/A // This is where the argument will eventually reside
116N/A VMRegPair dst = out_regs[c_arg];
116N/A
116N/A if (src->is_reg()) {
116N/A if (sid == 1) {
116N/A __ movq(c_rarg0, src->as_Register());
116N/A } else {
116N/A __ movq(c_rarg0, utf8_addr);
116N/A }
116N/A } else {
116N/A // arg is still in the original location
116N/A __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
116N/A }
116N/A Label done, convert;
116N/A
116N/A // see if the oop is NULL
116N/A __ testq(c_rarg0, c_rarg0);
116N/A __ jcc(Assembler::notEqual, convert);
116N/A
116N/A if (dst.first()->is_reg()) {
116N/A // Save the ptr to utf string in the origina src loc or the tmp
116N/A // dedicated to it
116N/A __ movq(Address(rbp, src_off), c_rarg0);
116N/A } else {
116N/A __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
116N/A }
116N/A __ jmp(done);
116N/A
116N/A __ bind(convert);
116N/A
116N/A __ lea(c_rarg1, utf8_addr);
116N/A if (dst.first()->is_reg()) {
116N/A __ movq(Address(rbp, src_off), c_rarg1);
116N/A } else {
116N/A __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
116N/A }
116N/A // And do the conversion
116N/A __ call(RuntimeAddress(
116N/A CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
116N/A
116N/A __ bind(done);
116N/A }
116N/A if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // skip over T_VOID to keep the loop indices in sync
116N/A }
116N/A }
116N/A // The get_utf call killed all the c_arg registers
116N/A live[c_rarg0->as_VMReg()->value()] = false;
116N/A live[c_rarg1->as_VMReg()->value()] = false;
116N/A live[c_rarg2->as_VMReg()->value()] = false;
116N/A live[c_rarg3->as_VMReg()->value()] = false;
116N/A live[c_rarg4->as_VMReg()->value()] = false;
116N/A live[c_rarg5->as_VMReg()->value()] = false;
116N/A
116N/A live[c_farg0->as_VMReg()->value()] = false;
116N/A live[c_farg1->as_VMReg()->value()] = false;
116N/A live[c_farg2->as_VMReg()->value()] = false;
116N/A live[c_farg3->as_VMReg()->value()] = false;
116N/A live[c_farg4->as_VMReg()->value()] = false;
116N/A live[c_farg5->as_VMReg()->value()] = false;
116N/A live[c_farg6->as_VMReg()->value()] = false;
116N/A live[c_farg7->as_VMReg()->value()] = false;
116N/A }
116N/A
116N/A // Now we can finally move the register args to their desired locations
116N/A
116N/A rax_is_zero = false;
116N/A
116N/A for (j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A j_arg < total_args_passed ; j_arg++, c_arg++ ) {
116N/A
116N/A VMRegPair src = in_regs[j_arg];
116N/A VMRegPair dst = out_regs[c_arg];
116N/A
116N/A // Only need to look for args destined for the interger registers (since we
116N/A // convert float/double args to look like int/long outbound)
116N/A if (dst.first()->is_reg()) {
116N/A Register r = dst.first()->as_Register();
116N/A
116N/A // Check if the java arg is unsupported and thereofre useless
116N/A bool useless = in_sig_bt[j_arg] == T_ARRAY ||
116N/A (in_sig_bt[j_arg] == T_OBJECT &&
116N/A out_sig_bt[c_arg] != T_INT &&
116N/A out_sig_bt[c_arg] != T_ADDRESS &&
116N/A out_sig_bt[c_arg] != T_LONG);
116N/A
116N/A
116N/A // If we're going to kill an existing arg save it first
116N/A if (live[dst.first()->value()]) {
116N/A // you can't kill yourself
116N/A if (src.first() != dst.first()) {
116N/A __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
116N/A }
116N/A }
116N/A if (src.first()->is_reg()) {
116N/A if (live[src.first()->value()] ) {
116N/A if (in_sig_bt[j_arg] == T_FLOAT) {
116N/A __ movdl(r, src.first()->as_XMMRegister());
116N/A } else if (in_sig_bt[j_arg] == T_DOUBLE) {
116N/A __ movdq(r, src.first()->as_XMMRegister());
116N/A } else if (r != src.first()->as_Register()) {
116N/A if (!useless) {
116N/A __ movq(r, src.first()->as_Register());
116N/A }
116N/A }
116N/A } else {
116N/A // If the arg is an oop type we don't support don't bother to store
116N/A // it
116N/A if (!useless) {
116N/A if (in_sig_bt[j_arg] == T_DOUBLE ||
116N/A in_sig_bt[j_arg] == T_LONG ||
116N/A in_sig_bt[j_arg] == T_OBJECT ) {
116N/A __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
116N/A } else {
116N/A __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
116N/A }
116N/A }
116N/A }
116N/A live[src.first()->value()] = false;
116N/A } else if (!useless) {
116N/A // full sized move even for int should be ok
116N/A __ movq(r, Address(rbp, reg2offset_in(src.first())));
116N/A }
116N/A
116N/A // At this point r has the original java arg in the final location
116N/A // (assuming it wasn't useless). If the java arg was an oop
116N/A // we have a bit more to do
116N/A
116N/A if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
116N/A if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
116N/A // need to unbox a one-word value
116N/A Label skip;
116N/A __ testq(r, r);
116N/A __ jcc(Assembler::equal, skip);
165N/A BasicType bt = out_sig_bt[c_arg];
165N/A int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
116N/A Address src1(r, box_offset);
165N/A if ( bt == T_LONG ) {
116N/A __ movq(r, src1);
116N/A } else {
116N/A __ movl(r, src1);
116N/A }
116N/A __ bind(skip);
116N/A
116N/A } else if (out_sig_bt[c_arg] != T_ADDRESS) {
116N/A // Convert the arg to NULL
116N/A __ xorq(r, r);
116N/A }
116N/A }
116N/A
116N/A // dst can longer be holding an input value
116N/A live[dst.first()->value()] = false;
116N/A }
116N/A if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // skip over T_VOID to keep the loop indices in sync
116N/A }
116N/A }
116N/A
116N/A
116N/A // Ok now we are done. Need to place the nop that dtrace wants in order to
116N/A // patch in the trap
116N/A int patch_offset = ((intptr_t)__ pc()) - start;
116N/A
116N/A __ nop();
116N/A
116N/A
116N/A // Return
116N/A
116N/A __ leave();
116N/A __ ret(0);
116N/A
116N/A __ flush();
116N/A
116N/A nmethod *nm = nmethod::new_dtrace_nmethod(
116N/A method, masm->code(), vep_offset, patch_offset, frame_complete,
116N/A stack_slots / VMRegImpl::slots_per_word);
116N/A return nm;
116N/A
116N/A}
116N/A
116N/A#endif // HAVE_DTRACE_H
116N/A
0N/A// this function returns the adjust size (in number of words) to a c2i adapter
0N/A// activation for use during deoptimization
0N/Aint Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
1426N/A return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
0N/A}
0N/A
0N/A
0N/Auint SharedRuntime::out_preserve_stack_slots() {
0N/A return 0;
0N/A}
0N/A
0N/A
0N/A//------------------------------generate_deopt_blob----------------------------
0N/Avoid SharedRuntime::generate_deopt_blob() {
0N/A // Allocate space for the code
0N/A ResourceMark rm;
0N/A // Setup code generation tools
0N/A CodeBuffer buffer("deopt_blob", 2048, 1024);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A int frame_size_in_words;
0N/A OopMap* map = NULL;
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A
0N/A // -------------
0N/A // This code enters when returning to a de-optimized nmethod. A return
0N/A // address has been pushed on the the stack, and return values are in
0N/A // registers.
0N/A // If we are doing a normal deopt then we were called from the patched
0N/A // nmethod from the point we returned to the nmethod. So the return
0N/A // address on the stack is wrong by NativeCall::instruction_size
0N/A // We will adjust the value so it looks like we have the original return
0N/A // address on the stack (like when we eagerly deoptimized).
0N/A // In the case of an exception pending when deoptimizing, we enter
0N/A // with a return address on the stack that points after the call we patched
0N/A // into the exception handler. We have the following register state from,
0N/A // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
0N/A // rax: exception oop
0N/A // rbx: exception handler
0N/A // rdx: throwing pc
0N/A // So in this case we simply jam rdx into the useless return address and
0N/A // the stack looks just like we want.
0N/A //
0N/A // At this point we need to de-opt. We save the argument return
0N/A // registers. We call the first C routine, fetch_unroll_info(). This
0N/A // routine captures the return values and returns a structure which
0N/A // describes the current frame size and the sizes of all replacement frames.
0N/A // The current frame is compiled code and may contain many inlined
0N/A // functions, each with their own JVM state. We pop the current frame, then
0N/A // push all the new frames. Then we call the C routine unpack_frames() to
0N/A // populate these frames. Finally unpack_frames() returns us the new target
0N/A // address. Notice that callee-save registers are BLOWN here; they have
0N/A // already been captured in the vframeArray at the time the return PC was
0N/A // patched.
0N/A address start = __ pc();
0N/A Label cont;
0N/A
0N/A // Prolog for non exception case!
0N/A
0N/A // Save everything in sight.
0N/A map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
0N/A
0N/A // Normal deoptimization. Save exec mode for unpack_frames.
113N/A __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
0N/A __ jmp(cont);
304N/A
304N/A int reexecute_offset = __ pc() - start;
304N/A
304N/A // Reexecute case
304N/A // return address is the pc describes what bci to do re-execute at
304N/A
304N/A // No need to update map as each call to save_live_registers will produce identical oopmap
304N/A (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
304N/A
304N/A __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
304N/A __ jmp(cont);
304N/A
0N/A int exception_offset = __ pc() - start;
0N/A
0N/A // Prolog for exception case
0N/A
304N/A // all registers are dead at this entry point, except for rax, and
304N/A // rdx which contain the exception oop and exception pc
304N/A // respectively. Set them in TLS and fall thru to the
304N/A // unpack_with_exception_in_tls entry point.
304N/A
304N/A __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
304N/A __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
304N/A
304N/A int exception_in_tls_offset = __ pc() - start;
304N/A
304N/A // new implementation because exception oop is now passed in JavaThread
304N/A
304N/A // Prolog for exception case
304N/A // All registers must be preserved because they might be used by LinearScan
304N/A // Exceptiop oop and throwing PC are passed in JavaThread
304N/A // tos: stack at point of call to method that threw the exception (i.e. only
304N/A // args are on the stack, no return address)
304N/A
304N/A // make room on stack for the return address
304N/A // It will be patched later with the throwing pc. The correct value is not
304N/A // available now because loading it from memory would destroy registers.
304N/A __ push(0);
0N/A
0N/A // Save everything in sight.
0N/A map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
0N/A
304N/A // Now it is safe to overwrite any register
304N/A
0N/A // Deopt during an exception. Save exec mode for unpack_frames.
113N/A __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
0N/A
304N/A // load throwing pc from JavaThread and patch it as the return address
304N/A // of the current frame. Then clear the field in JavaThread
304N/A
304N/A __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
304N/A __ movptr(Address(rbp, wordSize), rdx);
304N/A __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
304N/A
304N/A#ifdef ASSERT
304N/A // verify that there is really an exception oop in JavaThread
304N/A __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
304N/A __ verify_oop(rax);
304N/A
304N/A // verify that there is no pending exception
304N/A Label no_pending_exception;
304N/A __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
304N/A __ testptr(rax, rax);
304N/A __ jcc(Assembler::zero, no_pending_exception);
304N/A __ stop("must not have pending exception here");
304N/A __ bind(no_pending_exception);
304N/A#endif
304N/A
0N/A __ bind(cont);
0N/A
0N/A // Call C code. Need thread and this frame, but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen.
0N/A //
0N/A // UnrollBlock* fetch_unroll_info(JavaThread* thread)
0N/A
0N/A // fetch_unroll_info needs to call last_java_frame().
0N/A
0N/A __ set_last_Java_frame(noreg, noreg, NULL);
0N/A#ifdef ASSERT
0N/A { Label L;
304N/A __ cmpptr(Address(r15_thread,
0N/A JavaThread::last_Java_fp_offset()),
304N/A (int32_t)0);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
0N/A __ bind(L);
0N/A }
0N/A#endif // ASSERT
304N/A __ mov(c_rarg0, r15_thread);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
0N/A
0N/A // Need to have an oopmap that tells fetch_unroll_info where to
0N/A // find any register it might need.
0N/A oop_maps->add_gc_map(__ pc() - start, map);
0N/A
0N/A __ reset_last_Java_frame(false, false);
0N/A
0N/A // Load UnrollBlock* into rdi
304N/A __ mov(rdi, rax);
304N/A
304N/A Label noException;
682N/A __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
304N/A __ jcc(Assembler::notEqual, noException);
304N/A __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
304N/A // QQQ this is useless it was NULL above
304N/A __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
304N/A __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
304N/A __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
304N/A
304N/A __ verify_oop(rax);
304N/A
304N/A // Overwrite the result registers with the exception results.
304N/A __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
304N/A // I think this is useless
304N/A __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
304N/A
304N/A __ bind(noException);
0N/A
0N/A // Only register save data is on the stack.
0N/A // Now restore the result registers. Everything else is either dead
0N/A // or captured in the vframeArray.
0N/A RegisterSaver::restore_result_registers(masm);
0N/A
0N/A // All of the register save area has been popped of the stack. Only the
0N/A // return address remains.
0N/A
0N/A // Pop all the frames we must move/replace.
0N/A //
0N/A // Frame picture (youngest to oldest)
0N/A // 1: self-frame (no frame link)
0N/A // 2: deopting frame (no frame link)
0N/A // 3: caller of deopting frame (could be compiled/interpreted).
0N/A //
0N/A // Note: by leaving the return address of self-frame on the stack
0N/A // and using the size of frame 2 to adjust the stack
0N/A // when we are done the return to frame 3 will still be on the stack.
0N/A
0N/A // Pop deoptimized frame
0N/A __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
304N/A __ addptr(rsp, rcx);
0N/A
0N/A // rsp should be pointing at the return address to the caller (3)
0N/A
0N/A // Stack bang to make sure there's enough room for these interpreter frames.
0N/A if (UseStackBanging) {
0N/A __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
0N/A __ bang_stack_size(rbx, rcx);
0N/A }
0N/A
0N/A // Load address of array of frame pcs into rcx
304N/A __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
0N/A
0N/A // Trash the old pc
304N/A __ addptr(rsp, wordSize);
0N/A
0N/A // Load address of array of frame sizes into rsi
304N/A __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
0N/A
0N/A // Load counter into rdx
0N/A __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
0N/A
0N/A // Pick up the initial fp we should save
2764N/A __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
0N/A
0N/A // Now adjust the caller's stack to make up for the extra locals
0N/A // but record the original sp so that we can save it in the skeletal interpreter
0N/A // frame and the stack walking of interpreter_sender will get the unextended sp
0N/A // value and not the "real" sp value.
0N/A
0N/A const Register sender_sp = r8;
0N/A
304N/A __ mov(sender_sp, rsp);
0N/A __ movl(rbx, Address(rdi,
0N/A Deoptimization::UnrollBlock::
0N/A caller_adjustment_offset_in_bytes()));
304N/A __ subptr(rsp, rbx);
0N/A
0N/A // Push interpreter frames in a loop
0N/A Label loop;
0N/A __ bind(loop);
304N/A __ movptr(rbx, Address(rsi, 0)); // Load frame size
304N/A#ifdef CC_INTERP
304N/A __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
304N/A#ifdef ASSERT
304N/A __ push(0xDEADDEAD); // Make a recognizable pattern
304N/A __ push(0xDEADDEAD);
304N/A#else /* ASSERT */
304N/A __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
304N/A#endif /* ASSERT */
304N/A#else
304N/A __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
304N/A#endif // CC_INTERP
304N/A __ pushptr(Address(rcx, 0)); // Save return address
0N/A __ enter(); // Save old & set new ebp
304N/A __ subptr(rsp, rbx); // Prolog
304N/A#ifdef CC_INTERP
304N/A __ movptr(Address(rbp,
304N/A -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
304N/A sender_sp); // Make it walkable
304N/A#else /* CC_INTERP */
0N/A // This value is corrected by layout_activation_impl
304N/A __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
304N/A __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
304N/A#endif /* CC_INTERP */
304N/A __ mov(sender_sp, rsp); // Pass sender_sp to next frame
304N/A __ addptr(rsi, wordSize); // Bump array pointer (sizes)
304N/A __ addptr(rcx, wordSize); // Bump array pointer (pcs)
0N/A __ decrementl(rdx); // Decrement counter
0N/A __ jcc(Assembler::notZero, loop);
304N/A __ pushptr(Address(rcx, 0)); // Save final return address
0N/A
0N/A // Re-push self-frame
0N/A __ enter(); // Save old & set new ebp
0N/A
0N/A // Allocate a full sized register save area.
0N/A // Return address and rbp are in place, so we allocate two less words.
304N/A __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
0N/A
0N/A // Restore frame locals after moving the frame
0N/A __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
304N/A __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // restore return values to their stack-slots with the new SP.
0N/A //
0N/A // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
0N/A
0N/A // Use rbp because the frames look interpreted now
2895N/A // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
2895N/A // Don't need the precise return PC here, just precise enough to point into this code blob.
2895N/A address the_pc = __ pc();
2895N/A __ set_last_Java_frame(noreg, rbp, the_pc);
2895N/A
2895N/A __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
304N/A __ mov(c_rarg0, r15_thread);
113N/A __ movl(c_rarg1, r14); // second arg: exec_mode
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
2895N/A // Revert SP alignment after call since we're going to do some SP relative addressing below
2895N/A __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
0N/A
0N/A // Set an oopmap for the call site
2895N/A // Use the same PC we used for the last java frame
2895N/A oop_maps->add_gc_map(the_pc - start,
0N/A new OopMap( frame_size_in_words, 0 ));
0N/A
2895N/A // Clear fp AND pc
2895N/A __ reset_last_Java_frame(true, true);
0N/A
0N/A // Collect return values
0N/A __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
304N/A __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
304N/A // I think this is useless (throwing pc?)
304N/A __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
0N/A
0N/A // Pop self-frame.
0N/A __ leave(); // Epilog
0N/A
0N/A // Jump to interpreter
0N/A __ ret(0);
0N/A
0N/A // Make sure all code is generated
0N/A masm->flush();
0N/A
304N/A _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
304N/A _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
0N/A}
0N/A
0N/A#ifdef COMPILER2
0N/A//------------------------------generate_uncommon_trap_blob--------------------
0N/Avoid SharedRuntime::generate_uncommon_trap_blob() {
0N/A // Allocate space for the code
0N/A ResourceMark rm;
0N/A // Setup code generation tools
0N/A CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
0N/A
0N/A address start = __ pc();
0N/A
0N/A // Push self-frame. We get here with a return address on the
0N/A // stack, so rsp is 8-byte aligned until we allocate our frame.
304N/A __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
0N/A
0N/A // No callee saved registers. rbp is assumed implicitly saved
304N/A __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
0N/A
0N/A // compiler left unloaded_class_index in j_rarg0 move to where the
0N/A // runtime expects it.
0N/A __ movl(c_rarg1, j_rarg0);
0N/A
0N/A __ set_last_Java_frame(noreg, noreg, NULL);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // capture callee-saved registers as well as return values.
0N/A // Thread is in rdi already.
0N/A //
0N/A // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
0N/A
304N/A __ mov(c_rarg0, r15_thread);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
0N/A
0N/A // Set an oopmap for the call site
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
0N/A
0N/A // location of rbp is known implicitly by the frame sender code
0N/A
0N/A oop_maps->add_gc_map(__ pc() - start, map);
0N/A
0N/A __ reset_last_Java_frame(false, false);
0N/A
0N/A // Load UnrollBlock* into rdi
304N/A __ mov(rdi, rax);
0N/A
0N/A // Pop all the frames we must move/replace.
0N/A //
0N/A // Frame picture (youngest to oldest)
0N/A // 1: self-frame (no frame link)
0N/A // 2: deopting frame (no frame link)
0N/A // 3: caller of deopting frame (could be compiled/interpreted).
0N/A
0N/A // Pop self-frame. We have no frame, and must rely only on rax and rsp.
304N/A __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
0N/A
0N/A // Pop deoptimized frame (int)
0N/A __ movl(rcx, Address(rdi,
0N/A Deoptimization::UnrollBlock::
0N/A size_of_deoptimized_frame_offset_in_bytes()));
304N/A __ addptr(rsp, rcx);
0N/A
0N/A // rsp should be pointing at the return address to the caller (3)
0N/A
0N/A // Stack bang to make sure there's enough room for these interpreter frames.
0N/A if (UseStackBanging) {
0N/A __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
0N/A __ bang_stack_size(rbx, rcx);
0N/A }
0N/A
0N/A // Load address of array of frame pcs into rcx (address*)
304N/A __ movptr(rcx,
304N/A Address(rdi,
304N/A Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
0N/A
0N/A // Trash the return pc
304N/A __ addptr(rsp, wordSize);
0N/A
0N/A // Load address of array of frame sizes into rsi (intptr_t*)
304N/A __ movptr(rsi, Address(rdi,
304N/A Deoptimization::UnrollBlock::
304N/A frame_sizes_offset_in_bytes()));
0N/A
0N/A // Counter
0N/A __ movl(rdx, Address(rdi,
0N/A Deoptimization::UnrollBlock::
0N/A number_of_frames_offset_in_bytes())); // (int)
0N/A
0N/A // Pick up the initial fp we should save
304N/A __ movptr(rbp,
304N/A Address(rdi,
2764N/A Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
0N/A
0N/A // Now adjust the caller's stack to make up for the extra locals but
0N/A // record the original sp so that we can save it in the skeletal
0N/A // interpreter frame and the stack walking of interpreter_sender
0N/A // will get the unextended sp value and not the "real" sp value.
0N/A
0N/A const Register sender_sp = r8;
0N/A
304N/A __ mov(sender_sp, rsp);
0N/A __ movl(rbx, Address(rdi,
0N/A Deoptimization::UnrollBlock::
0N/A caller_adjustment_offset_in_bytes())); // (int)
304N/A __ subptr(rsp, rbx);
0N/A
0N/A // Push interpreter frames in a loop
0N/A Label loop;
0N/A __ bind(loop);
304N/A __ movptr(rbx, Address(rsi, 0)); // Load frame size
304N/A __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
304N/A __ pushptr(Address(rcx, 0)); // Save return address
304N/A __ enter(); // Save old & set new rbp
304N/A __ subptr(rsp, rbx); // Prolog
520N/A#ifdef CC_INTERP
520N/A __ movptr(Address(rbp,
520N/A -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
520N/A sender_sp); // Make it walkable
520N/A#else // CC_INTERP
304N/A __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
304N/A sender_sp); // Make it walkable
0N/A // This value is corrected by layout_activation_impl
304N/A __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
520N/A#endif // CC_INTERP
304N/A __ mov(sender_sp, rsp); // Pass sender_sp to next frame
304N/A __ addptr(rsi, wordSize); // Bump array pointer (sizes)
304N/A __ addptr(rcx, wordSize); // Bump array pointer (pcs)
304N/A __ decrementl(rdx); // Decrement counter
0N/A __ jcc(Assembler::notZero, loop);
304N/A __ pushptr(Address(rcx, 0)); // Save final return address
0N/A
0N/A // Re-push self-frame
0N/A __ enter(); // Save old & set new rbp
304N/A __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
0N/A // Prolog
0N/A
0N/A // Use rbp because the frames look interpreted now
2895N/A // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
2895N/A // Don't need the precise return PC here, just precise enough to point into this code blob.
2895N/A address the_pc = __ pc();
2895N/A __ set_last_Java_frame(noreg, rbp, the_pc);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // restore return values to their stack-slots with the new SP.
0N/A // Thread is in rdi already.
0N/A //
0N/A // BasicType unpack_frames(JavaThread* thread, int exec_mode);
0N/A
2895N/A __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
304N/A __ mov(c_rarg0, r15_thread);
0N/A __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
0N/A
0N/A // Set an oopmap for the call site
2895N/A // Use the same PC we used for the last java frame
2895N/A oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
2895N/A
2895N/A // Clear fp AND pc
2895N/A __ reset_last_Java_frame(true, true);
0N/A
0N/A // Pop self-frame.
0N/A __ leave(); // Epilog
0N/A
0N/A // Jump to interpreter
0N/A __ ret(0);
0N/A
0N/A // Make sure all code is generated
0N/A masm->flush();
0N/A
0N/A _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
0N/A SimpleRuntimeFrame::framesize >> 1);
0N/A}
0N/A#endif // COMPILER2
0N/A
0N/A
0N/A//------------------------------generate_handler_blob------
0N/A//
0N/A// Generate a special Compile2Runtime blob that saves all registers,
0N/A// and setup oopmap.
0N/A//
2578N/ASafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
0N/A assert(StubRoutines::forward_exception_entry() != NULL,
0N/A "must be generated before");
0N/A
0N/A ResourceMark rm;
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map;
0N/A
0N/A // Allocate space for the code. Setup code generation tools.
0N/A CodeBuffer buffer("handler_blob", 2048, 1024);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A address start = __ pc();
0N/A address call_pc = NULL;
0N/A int frame_size_in_words;
0N/A
0N/A // Make room for return address (or push it again)
0N/A if (!cause_return) {
304N/A __ push(rbx);
0N/A }
0N/A
0N/A // Save registers, fpu state, and flags
0N/A map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
0N/A
0N/A // The following is basically a call_VM. However, we need the precise
0N/A // address of the call in order to generate an oopmap. Hence, we do all the
0N/A // work outselves.
0N/A
0N/A __ set_last_Java_frame(noreg, noreg, NULL);
0N/A
0N/A // The return address must always be correct so that frame constructor never
0N/A // sees an invalid pc.
0N/A
0N/A if (!cause_return) {
0N/A // overwrite the dummy value we pushed on entry
304N/A __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
304N/A __ movptr(Address(rbp, wordSize), c_rarg0);
0N/A }
0N/A
0N/A // Do the call
304N/A __ mov(c_rarg0, r15_thread);
0N/A __ call(RuntimeAddress(call_ptr));
0N/A
0N/A // Set an oopmap for the call site. This oopmap will map all
0N/A // oop-registers and debug-info registers as callee-saved. This
0N/A // will allow deoptimization at this safepoint to find all possible
0N/A // debug-info recordings, as well as let GC find all oops.
0N/A
0N/A oop_maps->add_gc_map( __ pc() - start, map);
0N/A
0N/A Label noException;
0N/A
0N/A __ reset_last_Java_frame(false, false);
0N/A
304N/A __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, noException);
0N/A
0N/A // Exception pending
0N/A
0N/A RegisterSaver::restore_live_registers(masm);
0N/A
0N/A __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
0N/A
0N/A // No exception case
0N/A __ bind(noException);
0N/A
0N/A // Normal exit, restore registers and exit.
0N/A RegisterSaver::restore_live_registers(masm);
0N/A
0N/A __ ret(0);
0N/A
0N/A // Make sure all code is generated
0N/A masm->flush();
0N/A
0N/A // Fill-out other meta info
0N/A return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
0N/A}
0N/A
0N/A//
0N/A// generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
0N/A//
0N/A// Generate a stub that calls into vm to find out the proper destination
0N/A// of a java call. All the argument registers are live at this point
0N/A// but since this is generic code we don't know what they are and the caller
0N/A// must do any gc of the args.
0N/A//
2578N/ARuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
0N/A assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
0N/A
0N/A // allocate space for the code
0N/A ResourceMark rm;
0N/A
0N/A CodeBuffer buffer(name, 1000, 512);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A int frame_size_in_words;
0N/A
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map = NULL;
0N/A
0N/A int start = __ offset();
0N/A
0N/A map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
0N/A
0N/A int frame_complete = __ offset();
0N/A
0N/A __ set_last_Java_frame(noreg, noreg, NULL);
0N/A
304N/A __ mov(c_rarg0, r15_thread);
0N/A
0N/A __ call(RuntimeAddress(destination));
0N/A
0N/A
0N/A // Set an oopmap for the call site.
0N/A // We need this not only for callee-saved registers, but also for volatile
0N/A // registers that the compiler might be keeping live across a safepoint.
0N/A
0N/A oop_maps->add_gc_map( __ offset() - start, map);
0N/A
0N/A // rax contains the address we are going to jump to assuming no exception got installed
0N/A
0N/A // clear last_Java_sp
0N/A __ reset_last_Java_frame(false, false);
0N/A // check for pending exceptions
0N/A Label pending;
304N/A __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::notEqual, pending);
0N/A
0N/A // get the returned methodOop
304N/A __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
304N/A __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
304N/A
304N/A __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
0N/A
0N/A RegisterSaver::restore_live_registers(masm);
0N/A
0N/A // We are back the the original state on entry and ready to go.
0N/A
0N/A __ jmp(rax);
0N/A
0N/A // Pending exception after the safepoint
0N/A
0N/A __ bind(pending);
0N/A
0N/A RegisterSaver::restore_live_registers(masm);
0N/A
0N/A // exception pending => remove activation and forward to exception handler
0N/A
0N/A __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
0N/A
304N/A __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
0N/A __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
0N/A
0N/A // -------------
0N/A // make sure all code is generated
0N/A masm->flush();
0N/A
0N/A // return the blob
0N/A // frame_size_words or bytes??
0N/A return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
0N/A}
0N/A
0N/A
0N/A#ifdef COMPILER2
0N/A// This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
0N/A//
0N/A//------------------------------generate_exception_blob---------------------------
0N/A// creates exception blob at the end
0N/A// Using exception blob, this code is jumped from a compiled method.
0N/A// (see emit_exception_handler in x86_64.ad file)
0N/A//
0N/A// Given an exception pc at a call we call into the runtime for the
0N/A// handler in this method. This handler might merely restore state
0N/A// (i.e. callee save registers) unwind the frame and jump to the
0N/A// exception handler for the nmethod if there is no Java level handler
0N/A// for the nmethod.
0N/A//
0N/A// This code is entered with a jmp.
0N/A//
0N/A// Arguments:
0N/A// rax: exception oop
0N/A// rdx: exception pc
0N/A//
0N/A// Results:
0N/A// rax: exception oop
0N/A// rdx: exception pc in caller or ???
0N/A// destination: exception handler of caller
0N/A//
0N/A// Note: the exception pc MUST be at a call (precise debug information)
0N/A// Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
0N/A//
0N/A
0N/Avoid OptoRuntime::generate_exception_blob() {
0N/A assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
0N/A assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
0N/A assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
0N/A
0N/A assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
0N/A
0N/A // Allocate space for the code
0N/A ResourceMark rm;
0N/A // Setup code generation tools
0N/A CodeBuffer buffer("exception_blob", 2048, 1024);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A
0N/A address start = __ pc();
0N/A
0N/A // Exception pc is 'return address' for stack walker
304N/A __ push(rdx);
304N/A __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
0N/A
0N/A // Save callee-saved registers. See x86_64.ad.
0N/A
0N/A // rbp is an implicitly saved callee saved register (i.e. the calling
0N/A // convention will save restore it in prolog/epilog) Other than that
0N/A // there are no callee save registers now that adapter frames are gone.
0N/A
304N/A __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
0N/A
0N/A // Store exception in Thread object. We cannot pass any arguments to the
0N/A // handle_exception call, since we do not want to make any assumption
0N/A // about the size of the frame where the exception happened in.
0N/A // c_rarg0 is either rdi (Linux) or rcx (Windows).
304N/A __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
304N/A __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
0N/A
0N/A // This call does all the hard work. It checks if an exception handler
0N/A // exists in the method.
0N/A // If so, it returns the handler address.
0N/A // If not, it prepares for stack-unwinding, restoring the callee-save
0N/A // registers of the frame being removed.
0N/A //
0N/A // address OptoRuntime::handle_exception_C(JavaThread* thread)
0N/A
0N/A __ set_last_Java_frame(noreg, noreg, NULL);
304N/A __ mov(c_rarg0, r15_thread);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
0N/A
0N/A // Set an oopmap for the call site. This oopmap will only be used if we
0N/A // are unwinding the stack. Hence, all locations will be dead.
0N/A // Callee-saved registers will be the same as the frame above (i.e.,
0N/A // handle_exception_stub), since they were restored when we got the
0N/A // exception.
0N/A
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A
0N/A oop_maps->add_gc_map( __ pc()-start, new OopMap(SimpleRuntimeFrame::framesize, 0));
0N/A
0N/A __ reset_last_Java_frame(false, false);
0N/A
0N/A // Restore callee-saved registers
0N/A
0N/A // rbp is an implicitly saved callee saved register (i.e. the calling
0N/A // convention will save restore it in prolog/epilog) Other than that
0N/A // there are no callee save registers no that adapter frames are gone.
0N/A
304N/A __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
304N/A
304N/A __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
304N/A __ pop(rdx); // No need for exception pc anymore
0N/A
0N/A // rax: exception handler
0N/A
1368N/A // Restore SP from BP if the exception PC is a MethodHandle call site.
1368N/A __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0);
1487N/A __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
1135N/A
0N/A // We have a handler in rax (could be deopt blob).
304N/A __ mov(r8, rax);
0N/A
0N/A // Get the exception oop
304N/A __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
0N/A // Get the exception pc in case we are deoptimized
304N/A __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
0N/A#ifdef ASSERT
0N/A __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
0N/A __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
0N/A#endif
0N/A // Clear the exception oop so GC no longer processes it as a root.
0N/A __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
0N/A
0N/A // rax: exception oop
0N/A // r8: exception handler
0N/A // rdx: exception pc
0N/A // Jump to handler
0N/A
0N/A __ jmp(r8);
0N/A
0N/A // Make sure all code is generated
0N/A masm->flush();
0N/A
0N/A // Set exception blob
0N/A _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
0N/A}
0N/A#endif // COMPILER2