0N/A

1879N/A#include "precompiled.hpp"

1879N/A#include "c1/c1_Instruction.hpp"

1879N/A#include "c1/c1_LinearScan.hpp"

1879N/A#include "utilities/bitMap.inline.hpp"

0N/A

0N/A

0N/A

0N/Avoid LinearScan::allocate_fpu_stack() {

0N/A // First compute which FPU registers are live at the start of each basic block

0N/A // (To minimize the amount of work we have to do if we have to merge FPU stacks)

0N/A if (ComputeExactFPURegisterUsage) {

0N/A Interval* intervals_in_register, *intervals_in_memory;

0N/A create_unhandled_lists(&intervals_in_register, &intervals_in_memory, is_in_fpu_register, NULL);

0N/A

0N/A // ignore memory intervals by overwriting intervals_in_memory

0N/A // the dummy interval is needed to enforce the walker to walk until the given id:

0N/A // without it, the walker stops when the unhandled-list is empty -> live information

0N/A // beyond this point would be incorrect.

0N/A Interval* dummy_interval = new Interval(any_reg);

0N/A dummy_interval->add_range(max_jint - 2, max_jint - 1);

0N/A dummy_interval->set_next(Interval::end());

0N/A intervals_in_memory = dummy_interval;

0N/A

0N/A IntervalWalker iw(this, intervals_in_register, intervals_in_memory);

0N/A

0N/A const int num_blocks = block_count();

0N/A for (int i = 0; i < num_blocks; i++) {

0N/A BlockBegin* b = block_at(i);

0N/A

0N/A // register usage is only needed for merging stacks -> compute only

0N/A // when more than one predecessor.

0N/A // the block must not have any spill moves at the beginning (checked by assertions)

0N/A // spill moves would use intervals that are marked as handled and so the usage bit

0N/A // would been set incorrectly

0N/A

0N/A // NOTE: the check for number_of_preds > 1 is necessary. A block with only one

0N/A // predecessor may have spill moves at the begin of the block.

0N/A // If an interval ends at the current instruction id, it is not possible

0N/A // to decide if the register is live or not at the block begin -> the

0N/A // register information would be incorrect.

0N/A if (b->number_of_preds() > 1) {

0N/A int id = b->first_lir_instruction_id();

0N/A BitMap regs(FrameMap::nof_fpu_regs);

0N/A regs.clear();

0N/A

0N/A iw.walk_to(id); // walk after the first instruction (always a label) of the block

0N/A assert(iw.current_position() == id, "did not walk completely to id");

0N/A

0N/A // Only consider FPU values in registers

0N/A Interval* interval = iw.active_first(fixedKind);

0N/A while (interval != Interval::end()) {

0N/A int reg = interval->assigned_reg();

0N/A assert(reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg, "no fpu register");

0N/A assert(interval->assigned_regHi() == -1, "must not have hi register (doubles stored in one register)");

0N/A assert(interval->from() <= id && id < interval->to(), "interval out of range");

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPURegisterUsage) {

0N/A tty->print("fpu reg %d is live because of ", reg - pd_first_fpu_reg); interval->print();

0N/A }

0N/A#endif

0N/A

0N/A regs.set_bit(reg - pd_first_fpu_reg);

0N/A interval = interval->next();

0N/A }

0N/A

0N/A b->set_fpu_register_usage(regs);

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPURegisterUsage) {

0N/A tty->print("FPU regs for block %d, LIR instr %d): ", b->block_id(), id); regs.print_on(tty); tty->print_cr("");

0N/A }

0N/A#endif

0N/A }

0N/A }

0N/A }

0N/A

0N/A FpuStackAllocator alloc(ir()->compilation(), this);

0N/A _fpu_stack_allocator = &alloc;

0N/A alloc.allocate();

0N/A _fpu_stack_allocator = NULL;

0N/A}

0N/A

0N/A

0N/AFpuStackAllocator::FpuStackAllocator(Compilation* compilation, LinearScan* allocator)

0N/A : _compilation(compilation)

0N/A , _lir(NULL)

0N/A , _pos(-1)

0N/A , _allocator(allocator)

0N/A , _sim(compilation)

0N/A , _temp_sim(compilation)

0N/A{}

0N/A

0N/Avoid FpuStackAllocator::allocate() {

0N/A int num_blocks = allocator()->block_count();

0N/A for (int i = 0; i < num_blocks; i++) {

0N/A // Set up to process block

0N/A BlockBegin* block = allocator()->block_at(i);

0N/A intArray* fpu_stack_state = block->fpu_stack_state();

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->cr();

0N/A tty->print_cr("------- Begin of new Block %d -------", block->block_id());

0N/A }

0N/A#endif

0N/A

0N/A assert(fpu_stack_state != NULL ||

0N/A block->end()->as_Base() != NULL ||

0N/A block->is_set(BlockBegin::exception_entry_flag),

0N/A "FPU stack state must be present due to linear-scan order for FPU stack allocation");

0N/A // note: exception handler entries always start with an empty fpu stack

0N/A // because stack merging would be too complicated

0N/A

0N/A if (fpu_stack_state != NULL) {

0N/A sim()->read_state(fpu_stack_state);

0N/A } else {

0N/A sim()->clear();

0N/A }

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Reading FPU state for block %d:", block->block_id());

0N/A sim()->print();

0N/A tty->cr();

0N/A }

0N/A#endif

0N/A

0N/A allocate_block(block);

0N/A CHECK_BAILOUT();

0N/A }

0N/A}

0N/A

0N/Avoid FpuStackAllocator::allocate_block(BlockBegin* block) {

0N/A bool processed_merge = false;

0N/A LIR_OpList* insts = block->lir()->instructions_list();

0N/A set_lir(block->lir());

0N/A set_pos(0);

0N/A

0N/A

0N/A // Note: insts->length() may change during loop

0N/A while (pos() < insts->length()) {

0N/A LIR_Op* op = insts->at(pos());

0N/A _debug_information_computed = false;

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A op->print();

0N/A }

0N/A check_invalid_lir_op(op);

0N/A#endif

0N/A

0N/A LIR_OpBranch* branch = op->as_OpBranch();

0N/A LIR_Op1* op1 = op->as_Op1();

0N/A LIR_Op2* op2 = op->as_Op2();

0N/A LIR_OpCall* opCall = op->as_OpCall();

0N/A

0N/A if (branch != NULL && branch->block() != NULL) {

0N/A if (!processed_merge) {

0N/A // propagate stack at first branch to a successor

0N/A processed_merge = true;

0N/A bool required_merge = merge_fpu_stack_with_successors(block);

0N/A

0N/A assert(!required_merge || branch->cond() == lir_cond_always, "splitting of critical edges should prevent FPU stack mismatches at cond branches");

0N/A }

0N/A

0N/A } else if (op1 != NULL) {

0N/A handle_op1(op1);

0N/A } else if (op2 != NULL) {

0N/A handle_op2(op2);

0N/A } else if (opCall != NULL) {

0N/A handle_opCall(opCall);

0N/A }

0N/A

0N/A compute_debug_information(op);

0N/A

0N/A set_pos(1 + pos());

0N/A }

0N/A

0N/A // Propagate stack when block does not end with branch

0N/A if (!processed_merge) {

0N/A merge_fpu_stack_with_successors(block);

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::compute_debug_information(LIR_Op* op) {

0N/A if (!_debug_information_computed && op->id() != -1 && allocator()->has_info(op->id())) {

0N/A visitor.visit(op);

0N/A

0N/A // exception handling

0N/A if (allocator()->compilation()->has_exception_handlers()) {

0N/A XHandlers* xhandlers = visitor.all_xhandler();

0N/A int n = xhandlers->length();

0N/A for (int k = 0; k < n; k++) {

0N/A allocate_exception_handler(xhandlers->handler_at(k));

0N/A }

0N/A } else {

0N/A assert(visitor.all_xhandler()->length() == 0, "missed exception handler");

0N/A }

0N/A

0N/A // compute debug information

0N/A int n = visitor.info_count();

0N/A assert(n > 0, "should not visit operation otherwise");

0N/A

0N/A for (int j = 0; j < n; j++) {

0N/A CodeEmitInfo* info = visitor.info_at(j);

0N/A // Compute debug information

0N/A allocator()->compute_debug_info(info, op->id());

0N/A }

0N/A }

0N/A _debug_information_computed = true;

0N/A}

0N/A

0N/Avoid FpuStackAllocator::allocate_exception_handler(XHandler* xhandler) {

0N/A if (!sim()->is_empty()) {

0N/A LIR_List* old_lir = lir();

0N/A int old_pos = pos();

0N/A intArray* old_state = sim()->write_state();

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->cr();

0N/A tty->print_cr("------- begin of exception handler -------");

0N/A }

0N/A#endif

0N/A

0N/A if (xhandler->entry_code() == NULL) {

0N/A // need entry code to clear FPU stack

0N/A LIR_List* entry_code = new LIR_List(_compilation);

0N/A entry_code->jump(xhandler->entry_block());

0N/A xhandler->set_entry_code(entry_code);

0N/A }

0N/A

0N/A LIR_OpList* insts = xhandler->entry_code()->instructions_list();

0N/A set_lir(xhandler->entry_code());

0N/A set_pos(0);

0N/A

0N/A // Note: insts->length() may change during loop

0N/A while (pos() < insts->length()) {

0N/A LIR_Op* op = insts->at(pos());

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A op->print();

0N/A }

0N/A check_invalid_lir_op(op);

0N/A#endif

0N/A

0N/A switch (op->code()) {

0N/A case lir_move:

0N/A assert(op->as_Op1() != NULL, "must be LIR_Op1");

0N/A assert(pos() != insts->length() - 1, "must not be last operation");

0N/A

0N/A handle_op1((LIR_Op1*)op);

0N/A break;

0N/A

0N/A case lir_branch:

0N/A assert(op->as_OpBranch()->cond() == lir_cond_always, "must be unconditional branch");

0N/A assert(pos() == insts->length() - 1, "must be last operation");

0N/A

0N/A // remove all remaining dead registers from FPU stack

0N/A clear_fpu_stack(LIR_OprFact::illegalOpr);

0N/A break;

0N/A

0N/A default:

0N/A // other operations not allowed in exception entry code

0N/A ShouldNotReachHere();

0N/A }

0N/A

0N/A set_pos(pos() + 1);

0N/A }

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->cr();

0N/A tty->print_cr("------- end of exception handler -------");

0N/A }

0N/A#endif

0N/A

0N/A set_lir(old_lir);

0N/A set_pos(old_pos);

0N/A sim()->read_state(old_state);

0N/A }

0N/A}

0N/A

0N/A

0N/Aint FpuStackAllocator::fpu_num(LIR_Opr opr) {

0N/A assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise");

0N/A return opr->is_single_fpu() ? opr->fpu_regnr() : opr->fpu_regnrLo();

0N/A}

0N/A

0N/Aint FpuStackAllocator::tos_offset(LIR_Opr opr) {

0N/A return sim()->offset_from_tos(fpu_num(opr));

0N/A}

0N/A

0N/A

0N/ALIR_Opr FpuStackAllocator::to_fpu_stack(LIR_Opr opr) {

0N/A assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise");

0N/A

0N/A int stack_offset = tos_offset(opr);

0N/A if (opr->is_single_fpu()) {

0N/A return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset();

0N/A } else {

0N/A assert(opr->is_double_fpu(), "shouldn't call this otherwise");

0N/A return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset();

0N/A }

0N/A}

0N/A

0N/ALIR_Opr FpuStackAllocator::to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset) {

0N/A assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise");

0N/A assert(dont_check_offset || tos_offset(opr) == 0, "operand is not on stack top");

0N/A

0N/A int stack_offset = 0;

0N/A if (opr->is_single_fpu()) {

0N/A return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset();

0N/A } else {

0N/A assert(opr->is_double_fpu(), "shouldn't call this otherwise");

0N/A return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset();

0N/A }

0N/A}

0N/A

0N/A

0N/A

0N/Avoid FpuStackAllocator::insert_op(LIR_Op* op) {

0N/A lir()->insert_before(pos(), op);

0N/A set_pos(1 + pos());

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::insert_exchange(int offset) {

0N/A if (offset > 0) {

0N/A LIR_Op1* fxch_op = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr);

0N/A insert_op(fxch_op);

0N/A sim()->swap(offset);

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Exchanged register: %d New state: ", sim()->get_slot(0)); sim()->print(); tty->cr();

0N/A }

0N/A#endif

0N/A

0N/A }

0N/A}

0N/A

0N/Avoid FpuStackAllocator::insert_exchange(LIR_Opr opr) {

0N/A insert_exchange(tos_offset(opr));

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::insert_free(int offset) {

0N/A // move stack slot to the top of stack and then pop it

0N/A insert_exchange(offset);

0N/A

0N/A LIR_Op* fpop = new LIR_Op0(lir_fpop_raw);

0N/A insert_op(fpop);

0N/A sim()->pop();

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Inserted pop New state: "); sim()->print(); tty->cr();

0N/A }

0N/A#endif

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::insert_free_if_dead(LIR_Opr opr) {

0N/A if (sim()->contains(fpu_num(opr))) {

0N/A int res_slot = tos_offset(opr);

0N/A insert_free(res_slot);

0N/A }

0N/A}

0N/A

0N/Avoid FpuStackAllocator::insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore) {

0N/A if (fpu_num(opr) != fpu_num(ignore) && sim()->contains(fpu_num(opr))) {

0N/A int res_slot = tos_offset(opr);

0N/A insert_free(res_slot);

0N/A }

0N/A}

0N/A

0N/Avoid FpuStackAllocator::insert_copy(LIR_Opr from, LIR_Opr to) {

0N/A int offset = tos_offset(from);

0N/A LIR_Op1* fld = new LIR_Op1(lir_fld, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr);

0N/A insert_op(fld);

0N/A

0N/A sim()->push(fpu_num(to));

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Inserted copy (%d -> %d) New state: ", fpu_num(from), fpu_num(to)); sim()->print(); tty->cr();

0N/A }

0N/A#endif

0N/A}

0N/A

0N/Avoid FpuStackAllocator::do_rename(LIR_Opr from, LIR_Opr to) {

0N/A sim()->rename(fpu_num(from), fpu_num(to));

0N/A}

0N/A

0N/Avoid FpuStackAllocator::do_push(LIR_Opr opr) {

0N/A sim()->push(fpu_num(opr));

0N/A}

0N/A

0N/Avoid FpuStackAllocator::pop_if_last_use(LIR_Op* op, LIR_Opr opr) {

0N/A assert(op->fpu_pop_count() == 0, "fpu_pop_count alredy set");

0N/A assert(tos_offset(opr) == 0, "can only pop stack top");

0N/A

0N/A if (opr->is_last_use()) {

0N/A op->set_fpu_pop_count(1);

0N/A sim()->pop();

0N/A }

0N/A}

0N/A

0N/Avoid FpuStackAllocator::pop_always(LIR_Op* op, LIR_Opr opr) {

0N/A assert(op->fpu_pop_count() == 0, "fpu_pop_count alredy set");

0N/A assert(tos_offset(opr) == 0, "can only pop stack top");

0N/A

0N/A op->set_fpu_pop_count(1);

0N/A sim()->pop();

0N/A}

0N/A

0N/Avoid FpuStackAllocator::clear_fpu_stack(LIR_Opr preserve) {

0N/A int result_stack_size = (preserve->is_fpu_register() && !preserve->is_xmm_register() ? 1 : 0);

0N/A while (sim()->stack_size() > result_stack_size) {

0N/A assert(!sim()->slot_is_empty(0), "not allowed");

0N/A

0N/A if (result_stack_size == 0 || sim()->get_slot(0) != fpu_num(preserve)) {

0N/A insert_free(0);

0N/A } else {

0N/A // move "preserve" to bottom of stack so that all other stack slots can be popped

0N/A insert_exchange(sim()->stack_size() - 1);

0N/A }

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::handle_op1(LIR_Op1* op1) {

0N/A LIR_Opr in = op1->in_opr();

0N/A LIR_Opr res = op1->result_opr();

0N/A

0N/A LIR_Opr new_in = in; // new operands relative to the actual fpu stack top

0N/A LIR_Opr new_res = res;

0N/A

0N/A // Note: this switch is processed for all LIR_Op1, regardless if they have FPU-arguments,

0N/A // so checks for is_float_kind() are necessary inside the cases

0N/A switch (op1->code()) {

0N/A

0N/A case lir_return: {

0N/A // FPU-Stack must only contain the (optional) fpu return value.

0N/A // All remaining dead values are popped from the stack

0N/A // If the input operand is a fpu-register, it is exchanged to the bottom of the stack

0N/A

0N/A clear_fpu_stack(in);

0N/A if (in->is_fpu_register() && !in->is_xmm_register()) {

0N/A new_in = to_fpu_stack_top(in);

0N/A }

0N/A

0N/A break;

0N/A }

0N/A

0N/A case lir_move: {

0N/A if (in->is_fpu_register() && !in->is_xmm_register()) {

0N/A if (res->is_xmm_register()) {

0N/A // move from fpu register to xmm register (necessary for operations that

0N/A // are not available in the SSE instruction set)

0N/A insert_exchange(in);

0N/A new_in = to_fpu_stack_top(in);

0N/A pop_always(op1, in);

0N/A

0N/A } else if (res->is_fpu_register() && !res->is_xmm_register()) {

0N/A // move from fpu-register to fpu-register:

0N/A // * input and result register equal:

0N/A // nothing to do

0N/A // * input register is last use:

0N/A // rename the input register to result register -> input register

0N/A // not present on fpu-stack afterwards

0N/A // * input register not last use:

0N/A // duplicate input register to result register to preserve input

0N/A //

0N/A // Note: The LIR-Assembler does not produce any code for fpu register moves,

0N/A // so input and result stack index must be equal

0N/A

0N/A if (fpu_num(in) == fpu_num(res)) {

0N/A // nothing to do

0N/A } else if (in->is_last_use()) {

0N/A insert_free_if_dead(res);//, in);

0N/A do_rename(in, res);

0N/A } else {

0N/A insert_free_if_dead(res);

0N/A insert_copy(in, res);

0N/A }

0N/A new_in = to_fpu_stack(res);

0N/A new_res = new_in;

0N/A

0N/A } else {

0N/A // move from fpu-register to memory

0N/A // input operand must be on top of stack

0N/A

0N/A insert_exchange(in);

0N/A

0N/A // create debug information here because afterwards the register may have been popped

0N/A compute_debug_information(op1);

0N/A

0N/A new_in = to_fpu_stack_top(in);

0N/A pop_if_last_use(op1, in);

0N/A }

0N/A

0N/A } else if (res->is_fpu_register() && !res->is_xmm_register()) {

0N/A // move from memory/constant to fpu register

0N/A // result is pushed on the stack

0N/A

0N/A insert_free_if_dead(res);

0N/A

0N/A // create debug information before register is pushed

0N/A compute_debug_information(op1);

0N/A

0N/A do_push(res);

0N/A new_res = to_fpu_stack_top(res);

0N/A }

0N/A break;

0N/A }

0N/A

0N/A case lir_neg: {

0N/A if (in->is_fpu_register() && !in->is_xmm_register()) {

0N/A assert(res->is_fpu_register() && !res->is_xmm_register(), "must be");

0N/A assert(in->is_last_use(), "old value gets destroyed");

0N/A

0N/A insert_free_if_dead(res, in);

0N/A insert_exchange(in);

0N/A new_in = to_fpu_stack_top(in);

0N/A

0N/A do_rename(in, res);

0N/A new_res = to_fpu_stack_top(res);

0N/A }

0N/A break;

0N/A }

0N/A

0N/A case lir_convert: {

0N/A Bytecodes::Code bc = op1->as_OpConvert()->bytecode();

0N/A switch (bc) {

0N/A case Bytecodes::_d2f:

0N/A case Bytecodes::_f2d:

0N/A assert(res->is_fpu_register(), "must be");

0N/A assert(in->is_fpu_register(), "must be");

0N/A

0N/A if (!in->is_xmm_register() && !res->is_xmm_register()) {

0N/A // this is quite the same as a move from fpu-register to fpu-register

0N/A // Note: input and result operands must have different types

0N/A if (fpu_num(in) == fpu_num(res)) {

0N/A // nothing to do

0N/A new_in = to_fpu_stack(in);

0N/A } else if (in->is_last_use()) {

0N/A insert_free_if_dead(res);//, in);

0N/A new_in = to_fpu_stack(in);

0N/A do_rename(in, res);

0N/A } else {

0N/A insert_free_if_dead(res);

0N/A insert_copy(in, res);

0N/A new_in = to_fpu_stack_top(in, true);

0N/A }

0N/A new_res = to_fpu_stack(res);

0N/A }

0N/A

0N/A break;

0N/A

0N/A case Bytecodes::_i2f:

0N/A case Bytecodes::_l2f:

0N/A case Bytecodes::_i2d:

0N/A case Bytecodes::_l2d:

0N/A assert(res->is_fpu_register(), "must be");

0N/A if (!res->is_xmm_register()) {

0N/A insert_free_if_dead(res);

0N/A do_push(res);

0N/A new_res = to_fpu_stack_top(res);

0N/A }

0N/A break;

0N/A

0N/A case Bytecodes::_f2i:

0N/A case Bytecodes::_d2i:

0N/A assert(in->is_fpu_register(), "must be");

0N/A if (!in->is_xmm_register()) {

0N/A insert_exchange(in);

0N/A new_in = to_fpu_stack_top(in);

0N/A

0N/A // TODO: update registes of stub

0N/A }

0N/A break;

0N/A

0N/A case Bytecodes::_f2l:

0N/A case Bytecodes::_d2l:

0N/A assert(in->is_fpu_register(), "must be");

0N/A if (!in->is_xmm_register()) {

0N/A insert_exchange(in);

0N/A new_in = to_fpu_stack_top(in);

0N/A pop_always(op1, in);

0N/A }

0N/A break;

0N/A

0N/A case Bytecodes::_i2l:

0N/A case Bytecodes::_l2i:

0N/A case Bytecodes::_i2b:

0N/A case Bytecodes::_i2c:

0N/A case Bytecodes::_i2s:

0N/A // no fpu operands

0N/A break;

0N/A

0N/A default:

0N/A ShouldNotReachHere();

0N/A }

0N/A break;

0N/A }

0N/A

0N/A case lir_roundfp: {

0N/A assert(in->is_fpu_register() && !in->is_xmm_register(), "input must be in register");

0N/A assert(res->is_stack(), "result must be on stack");

0N/A

0N/A insert_exchange(in);

0N/A new_in = to_fpu_stack_top(in);

0N/A pop_if_last_use(op1, in);

0N/A break;

0N/A }

0N/A

0N/A default: {

0N/A assert(!in->is_float_kind() && !res->is_float_kind(), "missed a fpu-operation");

0N/A }

0N/A }

0N/A

0N/A op1->set_in_opr(new_in);

0N/A op1->set_result_opr(new_res);

0N/A}

0N/A

0N/Avoid FpuStackAllocator::handle_op2(LIR_Op2* op2) {

0N/A LIR_Opr left = op2->in_opr1();

0N/A if (!left->is_float_kind()) {

0N/A return;

0N/A }

0N/A if (left->is_xmm_register()) {

0N/A return;

0N/A }

0N/A

0N/A LIR_Opr right = op2->in_opr2();

0N/A LIR_Opr res = op2->result_opr();

0N/A LIR_Opr new_left = left; // new operands relative to the actual fpu stack top

0N/A LIR_Opr new_right = right;

0N/A LIR_Opr new_res = res;

0N/A

0N/A assert(!left->is_xmm_register() && !right->is_xmm_register() && !res->is_xmm_register(), "not for xmm registers");

0N/A

0N/A switch (op2->code()) {

0N/A case lir_cmp:

0N/A case lir_cmp_fd2i:

0N/A case lir_ucmp_fd2i: {

0N/A assert(left->is_fpu_register(), "invalid LIR");

0N/A assert(right->is_fpu_register(), "invalid LIR");

0N/A

0N/A // the left-hand side must be on top of stack.

0N/A // the right-hand side is never popped, even if is_last_use is set

0N/A insert_exchange(left);

0N/A new_left = to_fpu_stack_top(left);

0N/A new_right = to_fpu_stack(right);

0N/A pop_if_last_use(op2, left);

0N/A break;

0N/A }

0N/A

0N/A case lir_mul_strictfp:

0N/A case lir_div_strictfp: {

3752N/A assert(op2->tmp1_opr()->is_fpu_register(), "strict operations need temporary fpu stack slot");

3752N/A insert_free_if_dead(op2->tmp1_opr());

0N/A assert(sim()->stack_size() <= 7, "at least one stack slot must be free");

0N/A // fall-through: continue with the normal handling of lir_mul and lir_div

0N/A }

0N/A case lir_add:

0N/A case lir_sub:

0N/A case lir_mul:

0N/A case lir_div: {

0N/A assert(left->is_fpu_register(), "must be");

0N/A assert(res->is_fpu_register(), "must be");

0N/A assert(left->is_equal(res), "must be");

0N/A

0N/A // either the left-hand or the right-hand side must be on top of stack

0N/A // (if right is not a register, left must be on top)

0N/A if (!right->is_fpu_register()) {

0N/A insert_exchange(left);

0N/A new_left = to_fpu_stack_top(left);

0N/A } else {

0N/A // no exchange necessary if right is alredy on top of stack

0N/A if (tos_offset(right) == 0) {

0N/A new_left = to_fpu_stack(left);

0N/A new_right = to_fpu_stack_top(right);

0N/A } else {

0N/A insert_exchange(left);

0N/A new_left = to_fpu_stack_top(left);

0N/A new_right = to_fpu_stack(right);

0N/A }

0N/A

0N/A if (right->is_last_use()) {

0N/A op2->set_fpu_pop_count(1);

0N/A

0N/A if (tos_offset(right) == 0) {

0N/A sim()->pop();

0N/A } else {

0N/A // if left is on top of stack, the result is placed in the stack

0N/A // slot of right, so a renaming from right to res is necessary

0N/A assert(tos_offset(left) == 0, "must be");

0N/A sim()->pop();

0N/A do_rename(right, res);

0N/A }

0N/A }

0N/A }

0N/A new_res = to_fpu_stack(res);

0N/A

0N/A break;

0N/A }

0N/A

0N/A case lir_rem: {

0N/A assert(left->is_fpu_register(), "must be");

0N/A assert(right->is_fpu_register(), "must be");

0N/A assert(res->is_fpu_register(), "must be");

0N/A assert(left->is_equal(res), "must be");

0N/A

0N/A // Must bring both operands to top of stack with following operand ordering:

0N/A // * fpu stack before rem: ... right left

0N/A // * fpu stack after rem: ... left

0N/A if (tos_offset(right) != 1) {

0N/A insert_exchange(right);

0N/A insert_exchange(1);

0N/A }

0N/A insert_exchange(left);

0N/A assert(tos_offset(right) == 1, "check");

0N/A assert(tos_offset(left) == 0, "check");

0N/A

0N/A new_left = to_fpu_stack_top(left);

0N/A new_right = to_fpu_stack(right);

0N/A

0N/A op2->set_fpu_pop_count(1);

0N/A sim()->pop();

0N/A do_rename(right, res);

0N/A

0N/A new_res = to_fpu_stack_top(res);

0N/A break;

0N/A }

0N/A

0N/A case lir_abs:

0N/A case lir_sqrt: {

0N/A // Right argument appears to be unused

0N/A assert(right->is_illegal(), "must be");

0N/A assert(left->is_fpu_register(), "must be");

0N/A assert(res->is_fpu_register(), "must be");

0N/A assert(left->is_last_use(), "old value gets destroyed");

0N/A

0N/A insert_free_if_dead(res, left);

0N/A insert_exchange(left);

0N/A do_rename(left, res);

0N/A

0N/A new_left = to_fpu_stack_top(res);

0N/A new_res = new_left;

0N/A

0N/A op2->set_fpu_stack_size(sim()->stack_size());

0N/A break;

0N/A }

0N/A

953N/A case lir_log:

953N/A case lir_log10: {

3752N/A // log and log10 need one temporary fpu stack slot, so

3752N/A // there is one temporary registers stored in temp of the

3752N/A // operation. the stack allocator must guarantee that the stack

3752N/A // slots are really free, otherwise there might be a stack

3752N/A // overflow.

953N/A assert(right->is_illegal(), "must be");

953N/A assert(left->is_fpu_register(), "must be");

953N/A assert(res->is_fpu_register(), "must be");

3752N/A assert(op2->tmp1_opr()->is_fpu_register(), "must be");

953N/A

3752N/A insert_free_if_dead(op2->tmp1_opr());

953N/A insert_free_if_dead(res, left);

953N/A insert_exchange(left);

953N/A do_rename(left, res);

953N/A

953N/A new_left = to_fpu_stack_top(res);

953N/A new_res = new_left;

953N/A

953N/A op2->set_fpu_stack_size(sim()->stack_size());

953N/A assert(sim()->stack_size() <= 7, "at least one stack slot must be free");

953N/A break;

953N/A }

953N/A

0N/A

0N/A case lir_tan:

0N/A case lir_sin:

3752N/A case lir_cos:

3752N/A case lir_exp: {

3752N/A // sin, cos and exp need two temporary fpu stack slots, so there are two temporary

0N/A // registers (stored in right and temp of the operation).

0N/A // the stack allocator must guarantee that the stack slots are really free,

0N/A // otherwise there might be a stack overflow.

0N/A assert(left->is_fpu_register(), "must be");

0N/A assert(res->is_fpu_register(), "must be");

0N/A // assert(left->is_last_use(), "old value gets destroyed");

0N/A assert(right->is_fpu_register(), "right is used as the first temporary register");

3752N/A assert(op2->tmp1_opr()->is_fpu_register(), "temp is used as the second temporary register");

3752N/A assert(fpu_num(left) != fpu_num(right) && fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers");

0N/A

0N/A insert_free_if_dead(right);

3752N/A insert_free_if_dead(op2->tmp1_opr());

0N/A

0N/A insert_free_if_dead(res, left);

0N/A insert_exchange(left);

0N/A do_rename(left, res);

0N/A

0N/A new_left = to_fpu_stack_top(res);

0N/A new_res = new_left;

0N/A

0N/A op2->set_fpu_stack_size(sim()->stack_size());

0N/A assert(sim()->stack_size() <= 6, "at least two stack slots must be free");

0N/A break;

0N/A }

0N/A

3752N/A case lir_pow: {

3752N/A // pow needs two temporary fpu stack slots, so there are two temporary

3752N/A // registers (stored in tmp1 and tmp2 of the operation).

3752N/A // the stack allocator must guarantee that the stack slots are really free,

3752N/A // otherwise there might be a stack overflow.

3752N/A assert(left->is_fpu_register(), "must be");

3752N/A assert(right->is_fpu_register(), "must be");

3752N/A assert(res->is_fpu_register(), "must be");

3752N/A

3752N/A assert(op2->tmp1_opr()->is_fpu_register(), "tmp1 is the first temporary register");

3752N/A assert(op2->tmp2_opr()->is_fpu_register(), "tmp2 is the second temporary register");

3752N/A assert(fpu_num(left) != fpu_num(right) && fpu_num(left) != fpu_num(op2->tmp1_opr()) && fpu_num(left) != fpu_num(op2->tmp2_opr()) && fpu_num(left) != fpu_num(res), "need distinct temp registers");

3752N/A assert(fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(right) != fpu_num(op2->tmp2_opr()) && fpu_num(right) != fpu_num(res), "need distinct temp registers");

3752N/A assert(fpu_num(op2->tmp1_opr()) != fpu_num(op2->tmp2_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers");

3752N/A assert(fpu_num(op2->tmp2_opr()) != fpu_num(res), "need distinct temp registers");

3752N/A

3752N/A insert_free_if_dead(op2->tmp1_opr());

3752N/A insert_free_if_dead(op2->tmp2_opr());

3752N/A

3752N/A // Must bring both operands to top of stack with following operand ordering:

3752N/A // * fpu stack before pow: ... right left

3752N/A // * fpu stack after pow: ... left

3752N/A

3752N/A insert_free_if_dead(res, right);

3752N/A

3752N/A if (tos_offset(right) != 1) {

3752N/A insert_exchange(right);

3752N/A insert_exchange(1);

3752N/A }

3752N/A insert_exchange(left);

3752N/A assert(tos_offset(right) == 1, "check");

3752N/A assert(tos_offset(left) == 0, "check");

3752N/A

3752N/A new_left = to_fpu_stack_top(left);

3752N/A new_right = to_fpu_stack(right);

3752N/A

3752N/A op2->set_fpu_stack_size(sim()->stack_size());

3752N/A assert(sim()->stack_size() <= 6, "at least two stack slots must be free");

3752N/A

3752N/A sim()->pop();

3752N/A

3752N/A do_rename(right, res);

3752N/A

3752N/A new_res = to_fpu_stack_top(res);

3752N/A break;

3752N/A }

3752N/A

0N/A default: {

0N/A assert(false, "missed a fpu-operation");

0N/A }

0N/A }

0N/A

0N/A op2->set_in_opr1(new_left);

0N/A op2->set_in_opr2(new_right);

0N/A op2->set_result_opr(new_res);

0N/A}

0N/A

0N/Avoid FpuStackAllocator::handle_opCall(LIR_OpCall* opCall) {

0N/A LIR_Opr res = opCall->result_opr();

0N/A

0N/A // clear fpu-stack before call

0N/A // it may contain dead values that could not have been remved by previous operations

0N/A clear_fpu_stack(LIR_OprFact::illegalOpr);

0N/A assert(sim()->is_empty(), "fpu stack must be empty now");

0N/A

0N/A // compute debug information before (possible) fpu result is pushed

0N/A compute_debug_information(opCall);

0N/A

0N/A if (res->is_fpu_register() && !res->is_xmm_register()) {

0N/A do_push(res);

0N/A opCall->set_result_opr(to_fpu_stack_top(res));

0N/A }

0N/A}

0N/A

0N/A#ifndef PRODUCT

0N/Avoid FpuStackAllocator::check_invalid_lir_op(LIR_Op* op) {

0N/A switch (op->code()) {

0N/A case lir_24bit_FPU:

0N/A case lir_reset_FPU:

0N/A case lir_ffree:

0N/A assert(false, "operations not allowed in lir. If one of these operations is needed, check if they have fpu operands");

0N/A break;

0N/A

0N/A case lir_fpop_raw:

0N/A case lir_fxch:

0N/A case lir_fld:

0N/A assert(false, "operations only inserted by FpuStackAllocator");

0N/A break;

0N/A }

0N/A}

0N/A#endif

0N/A

0N/A

0N/Avoid FpuStackAllocator::merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg) {

0N/A LIR_Op1* move = new LIR_Op1(lir_move, LIR_OprFact::doubleConst(0), LIR_OprFact::double_fpu(reg)->make_fpu_stack_offset());

0N/A

0N/A instrs->instructions_list()->push(move);

0N/A

0N/A cur_sim->push(reg);

0N/A move->set_result_opr(to_fpu_stack(move->result_opr()));

0N/A

0N/A #ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Added new register: %d New state: ", reg); cur_sim->print(); tty->cr();

0N/A }

0N/A #endif

0N/A}

0N/A

0N/Avoid FpuStackAllocator::merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot) {

0N/A assert(slot > 0, "no exchange necessary");

0N/A

0N/A LIR_Op1* fxch = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(slot));

0N/A instrs->instructions_list()->push(fxch);

0N/A cur_sim->swap(slot);

0N/A

0N/A #ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Exchanged register: %d New state: ", cur_sim->get_slot(slot)); cur_sim->print(); tty->cr();

0N/A }

0N/A #endif

0N/A}

0N/A

0N/Avoid FpuStackAllocator::merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim) {

0N/A int reg = cur_sim->get_slot(0);

0N/A

0N/A LIR_Op* fpop = new LIR_Op0(lir_fpop_raw);

0N/A instrs->instructions_list()->push(fpop);

0N/A cur_sim->pop(reg);

0N/A

0N/A #ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Removed register: %d New state: ", reg); cur_sim->print(); tty->cr();

0N/A }

0N/A #endif

0N/A}

0N/A

0N/Abool FpuStackAllocator::merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot) {

0N/A int reg = cur_sim->get_slot(change_slot);

0N/A

0N/A for (int slot = start_slot; slot >= 0; slot--) {

0N/A int new_reg = sux_sim->get_slot(slot);

0N/A

0N/A if (!cur_sim->contains(new_reg)) {

0N/A cur_sim->set_slot(change_slot, new_reg);

0N/A

0N/A #ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("Renamed register %d to %d New state: ", reg, new_reg); cur_sim->print(); tty->cr();

0N/A }

0N/A #endif

0N/A

0N/A return true;

0N/A }

0N/A }

0N/A return false;

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim) {

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->cr();

0N/A tty->print("before merging: pred: "); cur_sim->print(); tty->cr();

0N/A tty->print(" sux: "); sux_sim->print(); tty->cr();

0N/A }

0N/A

0N/A int slot;

0N/A for (slot = 0; slot < cur_sim->stack_size(); slot++) {

0N/A assert(!cur_sim->slot_is_empty(slot), "not handled by algorithm");

0N/A }

0N/A for (slot = 0; slot < sux_sim->stack_size(); slot++) {

0N/A assert(!sux_sim->slot_is_empty(slot), "not handled by algorithm");

0N/A }

0N/A#endif

0N/A

0N/A // size difference between cur and sux that must be resolved by adding or removing values form the stack

0N/A int size_diff = cur_sim->stack_size() - sux_sim->stack_size();

0N/A

0N/A if (!ComputeExactFPURegisterUsage) {

0N/A // add slots that are currently free, but used in successor

0N/A // When the exact FPU register usage is computed, the stack does

0N/A // not contain dead values at merging -> no values must be added

0N/A

0N/A int sux_slot = sux_sim->stack_size() - 1;

0N/A while (size_diff < 0) {

0N/A assert(sux_slot >= 0, "slot out of bounds -> error in algorithm");

0N/A

0N/A int reg = sux_sim->get_slot(sux_slot);

0N/A if (!cur_sim->contains(reg)) {

0N/A merge_insert_add(instrs, cur_sim, reg);

0N/A size_diff++;

0N/A

0N/A if (sux_slot + size_diff != 0) {

0N/A merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff);

0N/A }

0N/A }

0N/A sux_slot--;

0N/A }

0N/A }

0N/A

0N/A assert(cur_sim->stack_size() >= sux_sim->stack_size(), "stack size must be equal or greater now");

0N/A assert(size_diff == cur_sim->stack_size() - sux_sim->stack_size(), "must be");

0N/A

0N/A // stack merge algorithm:

0N/A // 1) as long as the current stack top is not in the right location (that meens

0N/A // it should not be on the stack top), exchange it into the right location

0N/A // 2) if the stack top is right, but the remaining stack is not ordered correctly,

0N/A // the stack top is exchanged away to get another value on top ->

0N/A // now step 1) can be continued

0N/A // the stack can also contain unused items -> these items are removed from stack

0N/A

0N/A int finished_slot = sux_sim->stack_size() - 1;

0N/A while (finished_slot >= 0 || size_diff > 0) {

0N/A while (size_diff > 0 || (cur_sim->stack_size() > 0 && cur_sim->get_slot(0) != sux_sim->get_slot(0))) {

0N/A int reg = cur_sim->get_slot(0);

0N/A if (sux_sim->contains(reg)) {

0N/A int sux_slot = sux_sim->offset_from_tos(reg);

0N/A merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff);

0N/A

0N/A } else if (!merge_rename(cur_sim, sux_sim, finished_slot, 0)) {

0N/A assert(size_diff > 0, "must be");

0N/A

0N/A merge_insert_pop(instrs, cur_sim);

0N/A size_diff--;

0N/A }

0N/A assert(cur_sim->stack_size() == 0 || cur_sim->get_slot(0) != reg, "register must have been changed");

0N/A }

0N/A

0N/A while (finished_slot >= 0 && cur_sim->get_slot(finished_slot) == sux_sim->get_slot(finished_slot)) {

0N/A finished_slot--;

0N/A }

0N/A

0N/A if (finished_slot >= 0) {

0N/A int reg = cur_sim->get_slot(finished_slot);

0N/A

0N/A if (sux_sim->contains(reg) || !merge_rename(cur_sim, sux_sim, finished_slot, finished_slot)) {

0N/A assert(sux_sim->contains(reg) || size_diff > 0, "must be");

0N/A merge_insert_xchg(instrs, cur_sim, finished_slot);

0N/A }

0N/A assert(cur_sim->get_slot(finished_slot) != reg, "register must have been changed");

0N/A }

0N/A }

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("after merging: pred: "); cur_sim->print(); tty->cr();

0N/A tty->print(" sux: "); sux_sim->print(); tty->cr();

0N/A tty->cr();

0N/A }

0N/A#endif

0N/A assert(cur_sim->stack_size() == sux_sim->stack_size(), "stack size must be equal now");

0N/A}

0N/A

0N/A

0N/Avoid FpuStackAllocator::merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs) {

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->cr();

0N/A tty->print("before cleanup: state: "); cur_sim->print(); tty->cr();

0N/A tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr();

0N/A }

0N/A#endif

0N/A

0N/A int slot = 0;

0N/A while (slot < cur_sim->stack_size()) {

0N/A int reg = cur_sim->get_slot(slot);

0N/A if (!live_fpu_regs.at(reg)) {

0N/A if (slot != 0) {

0N/A merge_insert_xchg(instrs, cur_sim, slot);

0N/A }

0N/A merge_insert_pop(instrs, cur_sim);

0N/A } else {

0N/A slot++;

0N/A }

0N/A }

0N/A

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print("after cleanup: state: "); cur_sim->print(); tty->cr();

0N/A tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr();

0N/A tty->cr();

0N/A }

0N/A

0N/A // check if fpu stack only contains live registers

0N/A for (unsigned int i = 0; i < live_fpu_regs.size(); i++) {

0N/A if (live_fpu_regs.at(i) != cur_sim->contains(i)) {

0N/A tty->print_cr("mismatch between required and actual stack content");

0N/A break;

0N/A }

0N/A }

0N/A#endif

0N/A}

0N/A

0N/A

0N/Abool FpuStackAllocator::merge_fpu_stack_with_successors(BlockBegin* block) {

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print_cr("Propagating FPU stack state for B%d at LIR_Op position %d to successors:",

0N/A block->block_id(), pos());

0N/A sim()->print();

0N/A tty->cr();

0N/A }

0N/A#endif

0N/A

0N/A bool changed = false;

0N/A int number_of_sux = block->number_of_sux();

0N/A

0N/A if (number_of_sux == 1 && block->sux_at(0)->number_of_preds() > 1) {

0N/A // The successor has at least two incoming edges, so a stack merge will be necessary

0N/A // If this block is the first predecessor, cleanup the current stack and propagate it

0N/A // If this block is not the first predecessor, a stack merge will be necessary

0N/A

0N/A BlockBegin* sux = block->sux_at(0);

0N/A intArray* state = sux->fpu_stack_state();

0N/A LIR_List* instrs = new LIR_List(_compilation);

0N/A

0N/A if (state != NULL) {

0N/A // Merge with a successors that already has a FPU stack state

0N/A // the block must only have one successor because critical edges must been split

0N/A FpuStackSim* cur_sim = sim();

0N/A FpuStackSim* sux_sim = temp_sim();

0N/A sux_sim->read_state(state);

0N/A

0N/A merge_fpu_stack(instrs, cur_sim, sux_sim);

0N/A

0N/A } else {

0N/A // propagate current FPU stack state to successor without state

0N/A // clean up stack first so that there are no dead values on the stack

0N/A if (ComputeExactFPURegisterUsage) {

0N/A FpuStackSim* cur_sim = sim();

0N/A BitMap live_fpu_regs = block->sux_at(0)->fpu_register_usage();

0N/A assert(live_fpu_regs.size() == FrameMap::nof_fpu_regs, "missing register usage");

0N/A

0N/A merge_cleanup_fpu_stack(instrs, cur_sim, live_fpu_regs);

0N/A }

0N/A

0N/A intArray* state = sim()->write_state();

0N/A if (TraceFPUStack) {

0N/A tty->print_cr("Setting FPU stack state of B%d (merge path)", sux->block_id());

0N/A sim()->print(); tty->cr();

0N/A }

0N/A sux->set_fpu_stack_state(state);

0N/A }

0N/A

0N/A if (instrs->instructions_list()->length() > 0) {

0N/A lir()->insert_before(pos(), instrs);

0N/A set_pos(instrs->instructions_list()->length() + pos());

0N/A changed = true;

0N/A }

0N/A

0N/A } else {

0N/A // Propagate unmodified Stack to successors where a stack merge is not necessary

0N/A intArray* state = sim()->write_state();

0N/A for (int i = 0; i < number_of_sux; i++) {

0N/A BlockBegin* sux = block->sux_at(i);

0N/A

0N/A#ifdef ASSERT

0N/A for (int j = 0; j < sux->number_of_preds(); j++) {

0N/A assert(block == sux->pred_at(j), "all critical edges must be broken");

0N/A }

0N/A

0N/A // check if new state is same

0N/A if (sux->fpu_stack_state() != NULL) {

0N/A intArray* sux_state = sux->fpu_stack_state();

0N/A assert(state->length() == sux_state->length(), "overwriting existing stack state");

0N/A for (int j = 0; j < state->length(); j++) {

0N/A assert(state->at(j) == sux_state->at(j), "overwriting existing stack state");

0N/A }

0N/A }

0N/A#endif

0N/A#ifndef PRODUCT

0N/A if (TraceFPUStack) {

0N/A tty->print_cr("Setting FPU stack state of B%d", sux->block_id());

0N/A sim()->print(); tty->cr();

0N/A }

0N/A#endif

0N/A

0N/A sux->set_fpu_stack_state(state);

0N/A }

0N/A }

0N/A

0N/A#ifndef PRODUCT

0N/A // assertions that FPU stack state conforms to all successors' states

0N/A intArray* cur_state = sim()->write_state();

0N/A for (int i = 0; i < number_of_sux; i++) {

0N/A BlockBegin* sux = block->sux_at(i);

0N/A intArray* sux_state = sux->fpu_stack_state();

0N/A

0N/A assert(sux_state != NULL, "no fpu state");

0N/A assert(cur_state->length() == sux_state->length(), "incorrect length");

0N/A for (int i = 0; i < cur_state->length(); i++) {

0N/A assert(cur_state->at(i) == sux_state->at(i), "element not equal");

0N/A }

0N/A }

0N/A#endif

0N/A

0N/A return changed;

0N/A}