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0N/A
1879N/A#ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1879N/A#define CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1879N/A
0N/A// On i486 the frame looks as follows:
0N/A//
0N/A// +-----------------------------+---------+----------------------------------------+----------------+-----------
0N/A// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
0N/A// +-----------------------------+---------+----------------------------------------+----------------+-----------
0N/A//
0N/A// The FPU registers are mapped with their offset from TOS; therefore the
0N/A// status of FPU stack must be updated during code emission.
0N/A
0N/A public:
0N/A static const int pd_c_runtime_reserved_arg_size;
0N/A
0N/A enum {
0N/A nof_xmm_regs = pd_nof_xmm_regs_frame_map,
0N/A nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
0N/A first_available_sp_in_frame = 0,
304N/A#ifndef _LP64
0N/A frame_pad_in_bytes = 8,
0N/A nof_reg_args = 2
304N/A#else
304N/A frame_pad_in_bytes = 16,
304N/A nof_reg_args = 6
304N/A#endif // _LP64
0N/A };
0N/A
0N/A private:
0N/A static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs];
0N/A
0N/A static XMMRegister _xmm_regs[nof_xmm_regs];
0N/A
0N/A public:
0N/A static LIR_Opr receiver_opr;
0N/A
0N/A static LIR_Opr rsi_opr;
0N/A static LIR_Opr rdi_opr;
0N/A static LIR_Opr rbx_opr;
0N/A static LIR_Opr rax_opr;
0N/A static LIR_Opr rdx_opr;
0N/A static LIR_Opr rcx_opr;
0N/A static LIR_Opr rsp_opr;
0N/A static LIR_Opr rbp_opr;
0N/A
0N/A static LIR_Opr rsi_oop_opr;
0N/A static LIR_Opr rdi_oop_opr;
0N/A static LIR_Opr rbx_oop_opr;
0N/A static LIR_Opr rax_oop_opr;
0N/A static LIR_Opr rdx_oop_opr;
0N/A static LIR_Opr rcx_oop_opr;
304N/A#ifdef _LP64
0N/A
304N/A static LIR_Opr r8_opr;
304N/A static LIR_Opr r9_opr;
304N/A static LIR_Opr r10_opr;
304N/A static LIR_Opr r11_opr;
304N/A static LIR_Opr r12_opr;
304N/A static LIR_Opr r13_opr;
304N/A static LIR_Opr r14_opr;
304N/A static LIR_Opr r15_opr;
304N/A
304N/A static LIR_Opr r8_oop_opr;
304N/A static LIR_Opr r9_oop_opr;
304N/A
304N/A static LIR_Opr r11_oop_opr;
304N/A static LIR_Opr r12_oop_opr;
304N/A static LIR_Opr r13_oop_opr;
304N/A static LIR_Opr r14_oop_opr;
304N/A
304N/A#endif // _LP64
304N/A
304N/A static LIR_Opr long0_opr;
304N/A static LIR_Opr long1_opr;
0N/A static LIR_Opr fpu0_float_opr;
0N/A static LIR_Opr fpu0_double_opr;
0N/A static LIR_Opr xmm0_float_opr;
0N/A static LIR_Opr xmm0_double_opr;
0N/A
304N/A#ifdef _LP64
304N/A static LIR_Opr as_long_opr(Register r) {
304N/A return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
304N/A }
304N/A static LIR_Opr as_pointer_opr(Register r) {
304N/A return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
304N/A }
304N/A#else
0N/A static LIR_Opr as_long_opr(Register r, Register r2) {
0N/A return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
0N/A }
304N/A static LIR_Opr as_pointer_opr(Register r) {
304N/A return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
304N/A }
304N/A#endif // _LP64
0N/A
0N/A // VMReg name for spilled physical FPU stack slot n
0N/A static VMReg fpu_regname (int n);
0N/A
0N/A static XMMRegister nr2xmmreg(int rnr);
0N/A
0N/A static bool is_caller_save_register (LIR_Opr opr) { return true; }
0N/A static bool is_caller_save_register (Register r) { return true; }
0N/A
0N/A static LIR_Opr caller_save_xmm_reg_at(int i) {
0N/A assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
0N/A return _caller_save_xmm_regs[i];
0N/A }
1879N/A
1909N/A static int adjust_reg_range(int range) {
1909N/A // Reduce the number of available regs (to free r12) in case of compressed oops
1909N/A if (UseCompressedOops) return range - 1;
1909N/A return range;
1909N/A }
1909N/A
1909N/A static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }
1909N/A static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); }
1909N/A static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); }
1909N/A
1879N/A#endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1909N/A