0N/A

1879N/A#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP

1879N/A#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP

1879N/A

1879N/A#include "runtime/globals_extension.hpp"

1879N/A#include "runtime/vm_version.hpp"

1879N/A

0N/Aclass VM_Version: public Abstract_VM_Version {

0N/Aprotected:

0N/A enum Feature_Flag {

2664N/A v8_instructions = 0,

2664N/A hardware_mul32 = 1,

2664N/A hardware_div32 = 2,

2664N/A hardware_fsmuld = 3,

2664N/A hardware_popc = 4,

2664N/A v9_instructions = 5,

2664N/A vis1_instructions = 6,

2664N/A vis2_instructions = 7,

2664N/A sun4v_instructions = 8,

1834N/A blk_init_instructions = 9,

2664N/A fmaf_instructions = 10,

2664N/A fmau_instructions = 11,

2664N/A vis3_instructions = 12,

3935N/A cbcond_instructions = 13,

3935N/A sparc64_family = 14,

3935N/A M_family = 15,

3935N/A T_family = 16,

3935N/A T1_model = 17

0N/A };

0N/A

0N/A enum Feature_Flag_Set {

641N/A unknown_m = 0,

641N/A all_features_m = -1,

0N/A

2664N/A v8_instructions_m = 1 << v8_instructions,

2664N/A hardware_mul32_m = 1 << hardware_mul32,

2664N/A hardware_div32_m = 1 << hardware_div32,

2664N/A hardware_fsmuld_m = 1 << hardware_fsmuld,

2664N/A hardware_popc_m = 1 << hardware_popc,

2664N/A v9_instructions_m = 1 << v9_instructions,

2664N/A vis1_instructions_m = 1 << vis1_instructions,

2664N/A vis2_instructions_m = 1 << vis2_instructions,

2664N/A sun4v_m = 1 << sun4v_instructions,

1834N/A blk_init_instructions_m = 1 << blk_init_instructions,

2664N/A fmaf_instructions_m = 1 << fmaf_instructions,

2664N/A fmau_instructions_m = 1 << fmau_instructions,

2664N/A vis3_instructions_m = 1 << vis3_instructions,

3935N/A cbcond_instructions_m = 1 << cbcond_instructions,

2664N/A sparc64_family_m = 1 << sparc64_family,

3935N/A M_family_m = 1 << M_family,

2664N/A T_family_m = 1 << T_family,

2664N/A T1_model_m = 1 << T1_model,

0N/A

641N/A generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,

641N/A generic_v9_m = generic_v8_m | v9_instructions_m,

641N/A ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,

0N/A

0N/A // Temporary until we have something more accurate

641N/A niagara1_unique_m = sun4v_m,

641N/A niagara1_m = generic_v9_m | niagara1_unique_m

0N/A };

0N/A

0N/A static int _features;

0N/A static const char* _features_str;

0N/A

0N/A static void print_features();

0N/A static int determine_features();

0N/A static int platform_features(int features);

0N/A

1968N/A // Returns true if the platform is in the niagara line (T series)

3935N/A static bool is_M_family(int features) { return (features & M_family_m) != 0; }

1968N/A static bool is_T_family(int features) { return (features & T_family_m) != 0; }

1968N/A static bool is_niagara() { return is_T_family(_features); }

1968N/A DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } )

1968N/A

1968N/A // Returns true if it is niagara1 (T1).

1968N/A static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }

0N/A

10N/A static int maximum_niagara1_processor_count() { return 32; }

10N/A

0N/Apublic:

0N/A // Initialization

0N/A static void initialize();

0N/A

0N/A // Instruction support

0N/A static bool has_v8() { return (_features & v8_instructions_m) != 0; }

0N/A static bool has_v9() { return (_features & v9_instructions_m) != 0; }

641N/A static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }

641N/A static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }

0N/A static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }

643N/A static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }

0N/A static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }

0N/A static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }

1968N/A static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }

1834N/A static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }

2664N/A static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }

0N/A

0N/A static bool supports_compare_and_exchange()

0N/A { return has_v9(); }

0N/A

1968N/A // Returns true if the platform is in the niagara line (T series)

1968N/A // and newer than the niagara1.

1968N/A static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }

4017N/A

4017N/A static bool is_M_series() { return is_M_family(_features); }

2679N/A static bool is_T4() { return is_T_family(_features) && has_cbcond(); }

2664N/A

1968N/A // Fujitsu SPARC64

1968N/A static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }

0N/A

2664N/A static bool is_sun4v() { return (_features & sun4v_m) != 0; }

2664N/A static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }

2664N/A

1968N/A static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }

1968N/A static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }

2679N/A

2664N/A // T4 and newer Sparc have fast RDPC instruction.

2679N/A static bool has_fast_rdpc() { return is_T4(); }

2679N/A

2726N/A // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.

2726N/A static bool has_block_zeroing() { return has_blk_init() && is_T4(); }

0N/A

0N/A static const char* cpu_features() { return _features_str; }

0N/A

2679N/A static intx prefetch_data_size() {

2679N/A return is_T4() ? 32 : 64; // default prefetch block size on sparc

0N/A }

0N/A

0N/A // Prefetch

0N/A static intx prefetch_copy_interval_in_bytes() {

0N/A intx interval = PrefetchCopyIntervalInBytes;

0N/A return interval >= 0 ? interval : (has_v9() ? 512 : 0);

0N/A }

0N/A static intx prefetch_scan_interval_in_bytes() {

0N/A intx interval = PrefetchScanIntervalInBytes;

0N/A return interval >= 0 ? interval : (has_v9() ? 512 : 0);

0N/A }

0N/A static intx prefetch_fields_ahead() {

0N/A intx count = PrefetchFieldsAhead;

0N/A return count >= 0 ? count : (is_ultra3() ? 1 : 0);

0N/A }

0N/A

0N/A static intx allocate_prefetch_distance() {

0N/A // This method should be called before allocate_prefetch_style().

0N/A intx count = AllocatePrefetchDistance;

0N/A if (count < 0) { // default is not defined ?

0N/A count = 512;

0N/A }

0N/A return count;

0N/A }

0N/A static intx allocate_prefetch_style() {

0N/A assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");

0N/A // Return 0 if AllocatePrefetchDistance was not defined.

0N/A return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;

0N/A }

0N/A

0N/A // Legacy

0N/A static bool v8_instructions_work() { return has_v8() && !has_v9(); }

0N/A static bool v9_instructions_work() { return has_v9(); }

0N/A

0N/A // Assembler testing

0N/A static void allow_all();

0N/A static void revert();

0N/A

0N/A // Override the Abstract_VM_Version implementation.

0N/A static uint page_size_count() { return is_sun4v() ? 4 : 2; }

10N/A

10N/A // Calculates the number of parallel threads

10N/A static unsigned int calc_parallel_worker_threads();

0N/A};

1879N/A

1879N/A#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP