vm_version_sparc.cpp revision 2664
0N/A/*
1558N/A * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "assembler_sparc.inline.hpp"
1879N/A#include "memory/resourceArea.hpp"
1879N/A#include "runtime/java.hpp"
1879N/A#include "runtime/stubCodeGenerator.hpp"
1879N/A#include "vm_version_sparc.hpp"
1879N/A#ifdef TARGET_OS_FAMILY_linux
1879N/A# include "os_linux.inline.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_OS_FAMILY_solaris
1879N/A# include "os_solaris.inline.hpp"
1879N/A#endif
1879N/A
1879N/Aint VM_Version::_features = VM_Version::unknown_m;
1879N/Aconst char* VM_Version::_features_str = "";
1879N/A
1879N/Avoid VM_Version::initialize() {
1879N/A _features = determine_features();
1879N/A PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1879N/A PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1879N/A PrefetchFieldsAhead = prefetch_fields_ahead();
1879N/A
1879N/A // Allocation prefetch settings
1879N/A intx cache_line_size = L1_data_cache_line_size();
1879N/A if( cache_line_size > AllocatePrefetchStepSize )
1879N/A AllocatePrefetchStepSize = cache_line_size;
1585N/A if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
1585N/A AllocatePrefetchLines = 3; // Optimistic value
1585N/A assert( AllocatePrefetchLines > 0, "invalid value");
1585N/A if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1585N/A AllocatePrefetchLines = 1; // Conservative value
1585N/A
1585N/A AllocatePrefetchDistance = allocate_prefetch_distance();
1585N/A AllocatePrefetchStyle = allocate_prefetch_style();
1585N/A
1585N/A assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
1585N/A
1585N/A if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
1585N/A warning("BIS instructions are not available on this CPU");
1585N/A FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
1585N/A }
1585N/A
1585N/A UseSSE = 0; // Only on x86 and x64
1585N/A
1585N/A _supports_cx8 = has_v9();
1585N/A
1585N/A if (is_niagara()) {
1585N/A // Indirect branch is the same cost as direct
1585N/A if (FLAG_IS_DEFAULT(UseInlineCaches)) {
1585N/A FLAG_SET_DEFAULT(UseInlineCaches, false);
1585N/A }
1585N/A // Align loops on a single instruction boundary.
1585N/A if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
1585N/A FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
1585N/A }
1585N/A // When using CMS, we cannot use memset() in BOT updates because
1585N/A // the sun4v/CMT version in libc_psr uses BIS which exposes
1585N/A // "phantom zeros" to concurrent readers. See 6948537.
1585N/A if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
1585N/A FLAG_SET_DEFAULT(UseMemSetInBOT, false);
1585N/A }
1585N/A#ifdef _LP64
1585N/A // 32-bit oops don't make sense for the 64-bit VM on sparc
1629N/A // since the 32-bit VM has the same registers and smaller objects.
1629N/A Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
1585N/A#endif // _LP64
1585N/A#ifdef COMPILER2
1585N/A // Indirect branch is the same cost as direct
1585N/A if (FLAG_IS_DEFAULT(UseJumpTables)) {
1585N/A FLAG_SET_DEFAULT(UseJumpTables, true);
1629N/A }
1585N/A // Single-issue, so entry and loop tops are
1585N/A // aligned on a single instruction boundary
1629N/A if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
1585N/A FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
1585N/A }
1629N/A if (is_niagara_plus()) {
1629N/A if (has_blk_init() && AllocatePrefetchStyle > 0 &&
1585N/A FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1585N/A // Use BIS instruction for allocation prefetch.
1585N/A FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
1585N/A if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1585N/A // Use smaller prefetch distance on N2 with BIS
1585N/A FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
1585N/A }
1585N/A }
1585N/A if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1585N/A // Use different prefetch distance without BIS
1585N/A FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
1585N/A }
1585N/A }
1585N/A#endif
1585N/A }
1585N/A
1585N/A // Use hardware population count instruction if available.
1585N/A if (has_hardware_popc()) {
1585N/A if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1585N/A FLAG_SET_DEFAULT(UsePopCountInstruction, true);
1311N/A }
0N/A } else if (UsePopCountInstruction) {
0N/A warning("POPC instruction is not available on this CPU");
907N/A FLAG_SET_DEFAULT(UsePopCountInstruction, false);
907N/A }
907N/A
907N/A // T4 and newer Sparc cpus have new compare and branch instruction.
541N/A if (has_cbcond()) {
0N/A if (FLAG_IS_DEFAULT(UseCBCond)) {
1311N/A FLAG_SET_DEFAULT(UseCBCond, true);
907N/A }
907N/A } else if (UseCBCond) {
907N/A warning("CBCOND instruction is not available on this CPU");
907N/A FLAG_SET_DEFAULT(UseCBCond, false);
907N/A }
907N/A
0N/A#ifdef COMPILER2
907N/A // T4 and newer Sparc cpus have fast RDPC.
907N/A if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
907N/A// FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
907N/A }
907N/A
0N/A // Currently not supported anywhere.
907N/A FLAG_SET_DEFAULT(UseFPUForSpilling, false);
907N/A#endif
907N/A
907N/A char buf[512];
907N/A jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
0N/A (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
907N/A (has_hardware_popc() ? ", popc" : ""),
907N/A (has_vis1() ? ", vis1" : ""),
907N/A (has_vis2() ? ", vis2" : ""),
907N/A (has_vis3() ? ", vis3" : ""),
907N/A (has_blk_init() ? ", blk_init" : ""),
907N/A (has_cbcond() ? ", cbcond" : ""),
907N/A (is_ultra3() ? ", ultra3" : ""),
0N/A (is_sun4v() ? ", sun4v" : ""),
907N/A (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
907N/A (is_sparc64() ? ", sparc64" : ""),
907N/A (!has_hardware_mul32() ? ", no-mul32" : ""),
907N/A (!has_hardware_div32() ? ", no-div32" : ""),
907N/A (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
907N/A
907N/A // buf is started with ", " or is empty
907N/A _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
907N/A
0N/A // UseVIS is set to the smallest of what hardware supports and what
907N/A // the command line requires. I.e., you cannot set UseVIS to 3 on
907N/A // older UltraSparc which do not support it.
907N/A if (UseVIS > 3) UseVIS=3;
907N/A if (UseVIS < 0) UseVIS=0;
907N/A if (!has_vis3()) // Drop to 2 if no VIS3 support
907N/A UseVIS = MIN2((intx)2,UseVIS);
0N/A if (!has_vis2()) // Drop to 1 if no VIS2 support
907N/A UseVIS = MIN2((intx)1,UseVIS);
907N/A if (!has_vis1()) // Drop to 0 if no VIS1 support
0N/A UseVIS = 0;
0N/A
907N/A#ifndef PRODUCT
907N/A if (PrintMiscellaneous && Verbose) {
1311N/A tty->print("Allocation: ");
907N/A if (AllocatePrefetchStyle <= 0) {
0N/A tty->print_cr("no prefetching");
0N/A } else {
0N/A if (AllocatePrefetchLines > 1) {
1311N/A tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
541N/A } else {
907N/A tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance);
907N/A }
907N/A }
907N/A if (PrefetchCopyIntervalInBytes > 0) {
907N/A tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
907N/A }
907N/A if (PrefetchScanIntervalInBytes > 0) {
907N/A tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
907N/A }
907N/A if (PrefetchFieldsAhead > 0) {
907N/A tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
907N/A }
907N/A }
907N/A#endif // PRODUCT
907N/A}
0N/A
0N/Avoid VM_Version::print_features() {
0N/A tty->print_cr("Version:%s", cpu_features());
0N/A}
0N/A
1558N/Aint VM_Version::determine_features() {
1558N/A if (UseV8InstrsOnly) {
1558N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
0N/A return generic_v8_m;
0N/A }
0N/A
0N/A int features = platform_features(unknown_m); // platform_features() is os_arch specific
1311N/A
907N/A if (features == unknown_m) {
0N/A features = generic_v9_m;
0N/A warning("Cannot recognize SPARC version. Default to V9");
1311N/A }
907N/A
0N/A assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
0N/A if (UseNiagaraInstrs) { // Force code generation for Niagara
342N/A if (is_T_family(features)) {
342N/A // Happy to accomodate...
907N/A } else {
342N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
342N/A features |= T_family_m;
0N/A }
0N/A } else {
1311N/A if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
1284N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
1284N/A features &= ~(T_family_m | T1_model_m);
1284N/A } else {
1585N/A // Happy to accomodate...
1585N/A }
0N/A }
0N/A
1311N/A return features;
1311N/A}
1311N/A
1311N/Astatic int saved_features = 0;
1311N/A
1311N/Avoid VM_Version::allow_all() {
1311N/A saved_features = _features;
1311N/A _features = all_features_m;
1311N/A}
1311N/A
1311N/Avoid VM_Version::revert() {
1311N/A _features = saved_features;
1311N/A}
1311N/A
1311N/Aunsigned int VM_Version::calc_parallel_worker_threads() {
1585N/A unsigned int result;
1311N/A if (is_niagara_plus()) {
0N/A result = nof_parallel_worker_threads(5, 16, 8);
0N/A } else {
541N/A result = nof_parallel_worker_threads(5, 8, 8);
541N/A }
0N/A return result;
0N/A}
1311N/A