vm_version_sparc.cpp revision 2664
1558N/A * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. 0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 0N/A * This code is free software; you can redistribute it and/or modify it 0N/A * under the terms of the GNU General Public License version 2 only, as 0N/A * published by the Free Software Foundation. 0N/A * This code is distributed in the hope that it will be useful, but WITHOUT 0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 0N/A * version 2 for more details (a copy is included in the LICENSE file that 0N/A * accompanied this code). 0N/A * You should have received a copy of the GNU General Public License version 0N/A * 2 along with this work; if not, write to the Free Software Foundation, 0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 1879N/A // Allocation prefetch settings 1585N/A // Indirect branch is the same cost as direct 1585N/A // Align loops on a single instruction boundary. 1585N/A // When using CMS, we cannot use memset() in BOT updates because 1585N/A // "phantom zeros" to concurrent readers. See 6948537. 1585N/A // 32-bit oops don't make sense for the 64-bit VM on sparc 1629N/A // since the 32-bit VM has the same registers and smaller objects. 1585N/A // Indirect branch is the same cost as direct 1585N/A // Single-issue, so entry and loop tops are 1585N/A // aligned on a single instruction boundary 1585N/A // Use BIS instruction for allocation prefetch. 1585N/A // Use smaller prefetch distance on N2 with BIS 1585N/A // Use different prefetch distance without BIS 1585N/A // Use hardware population count instruction if available. 0N/A warning(
"POPC instruction is not available on this CPU");
907N/A // T4 and newer Sparc cpus have new compare and branch instruction. 907N/A warning(
"CBCOND instruction is not available on this CPU");
907N/A // T4 and newer Sparc cpus have fast RDPC. 907N/A// FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 0N/A // Currently not supported anywhere. 907N/A // buf is started with ", " or is empty 0N/A // UseVIS is set to the smallest of what hardware supports and what 907N/A // the command line requires. I.e., you cannot set UseVIS to 3 on 907N/A // older UltraSparc which do not support it. 0N/A warning(
"Cannot recognize SPARC version. Default to V9");
342N/A // Happy to accomodate...