0N/A/*
3845N/A * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "assembler_sparc.inline.hpp"
1879N/A#include "memory/resourceArea.hpp"
1879N/A#include "runtime/java.hpp"
1879N/A#include "runtime/stubCodeGenerator.hpp"
1879N/A#include "vm_version_sparc.hpp"
1879N/A#ifdef TARGET_OS_FAMILY_linux
1879N/A# include "os_linux.inline.hpp"
1879N/A#endif
1879N/A#ifdef TARGET_OS_FAMILY_solaris
1879N/A# include "os_solaris.inline.hpp"
1879N/A#endif
0N/A
0N/Aint VM_Version::_features = VM_Version::unknown_m;
0N/Aconst char* VM_Version::_features_str = "";
0N/A
0N/Avoid VM_Version::initialize() {
0N/A _features = determine_features();
0N/A PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
0N/A PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
0N/A PrefetchFieldsAhead = prefetch_fields_ahead();
0N/A
2679N/A assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
2679N/A if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
2679N/A if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
2679N/A
0N/A // Allocation prefetch settings
2679N/A intx cache_line_size = prefetch_data_size();
0N/A if( cache_line_size > AllocatePrefetchStepSize )
0N/A AllocatePrefetchStepSize = cache_line_size;
2679N/A
2679N/A assert(AllocatePrefetchLines > 0, "invalid value");
2679N/A if( AllocatePrefetchLines < 1 ) // set valid value in product VM
2679N/A AllocatePrefetchLines = 3;
2679N/A assert(AllocateInstancePrefetchLines > 0, "invalid value");
2679N/A if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
2679N/A AllocateInstancePrefetchLines = 1;
0N/A
0N/A AllocatePrefetchDistance = allocate_prefetch_distance();
0N/A AllocatePrefetchStyle = allocate_prefetch_style();
0N/A
2679N/A assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
2679N/A (AllocatePrefetchDistance > 0), "invalid value");
2679N/A if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
2679N/A (AllocatePrefetchDistance <= 0)) {
2679N/A AllocatePrefetchDistance = AllocatePrefetchStepSize;
2679N/A }
0N/A
2664N/A if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
2664N/A warning("BIS instructions are not available on this CPU");
2664N/A FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
2664N/A }
2664N/A
2737N/A if (has_v9()) {
2737N/A assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
2737N/A if (ArraycopySrcPrefetchDistance >= 4096)
2737N/A ArraycopySrcPrefetchDistance = 4064;
2737N/A assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
2737N/A if (ArraycopyDstPrefetchDistance >= 4096)
2737N/A ArraycopyDstPrefetchDistance = 4064;
2737N/A } else {
2737N/A if (ArraycopySrcPrefetchDistance > 0) {
2737N/A warning("prefetch instructions are not available on this CPU");
2737N/A FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0);
2737N/A }
2737N/A if (ArraycopyDstPrefetchDistance > 0) {
2737N/A warning("prefetch instructions are not available on this CPU");
2737N/A FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0);
2737N/A }
2737N/A }
2737N/A
0N/A UseSSE = 0; // Only on x86 and x64
0N/A
2679N/A _supports_cx8 = has_v9();
4015N/A _supports_atomic_getset4 = true; // swap instruction
0N/A
1968N/A if (is_niagara()) {
0N/A // Indirect branch is the same cost as direct
0N/A if (FLAG_IS_DEFAULT(UseInlineCaches)) {
675N/A FLAG_SET_DEFAULT(UseInlineCaches, false);
0N/A }
1968N/A // Align loops on a single instruction boundary.
1968N/A if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
1968N/A FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
1968N/A }
3960N/A // When using CMS or G1, we cannot use memset() in BOT updates
3960N/A // because the sun4v/CMT version in libc_psr uses BIS which
3960N/A // exposes "phantom zeros" to concurrent readers. See 6948537.
3960N/A if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
1968N/A FLAG_SET_DEFAULT(UseMemSetInBOT, false);
1968N/A }
113N/A#ifdef _LP64
642N/A // 32-bit oops don't make sense for the 64-bit VM on sparc
642N/A // since the 32-bit VM has the same registers and smaller objects.
642N/A Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
113N/A#endif // _LP64
0N/A#ifdef COMPILER2
0N/A // Indirect branch is the same cost as direct
0N/A if (FLAG_IS_DEFAULT(UseJumpTables)) {
675N/A FLAG_SET_DEFAULT(UseJumpTables, true);
0N/A }
0N/A // Single-issue, so entry and loop tops are
0N/A // aligned on a single instruction boundary
0N/A if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
675N/A FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
0N/A }
1968N/A if (is_niagara_plus()) {
2679N/A if (has_blk_init() && UseTLAB &&
2679N/A FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
2679N/A // Use BIS instruction for TLAB allocation prefetch.
2679N/A FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
2679N/A if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
2679N/A FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
2679N/A }
1367N/A if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
2679N/A // Use smaller prefetch distance with BIS
1367N/A FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
1367N/A }
1367N/A }
2679N/A if (is_T4()) {
2679N/A // Double number of prefetched cache lines on T4
2679N/A // since L2 cache line size is smaller (32 bytes).
2679N/A if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
2679N/A FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
2679N/A }
2679N/A if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
2679N/A FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
2679N/A }
2679N/A }
1367N/A if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1367N/A // Use different prefetch distance without BIS
1367N/A FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
1367N/A }
2679N/A if (AllocatePrefetchInstr == 1) {
2679N/A // Need a space at the end of TLAB for BIS since it
2679N/A // will fault when accessing memory outside of heap.
2679N/A
2679N/A // +1 for rounding up to next cache line, +1 to be safe
2679N/A int lines = AllocatePrefetchLines + 2;
2679N/A int step_size = AllocatePrefetchStepSize;
2679N/A int distance = AllocatePrefetchDistance;
2679N/A _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
2679N/A }
0N/A }
0N/A#endif
0N/A }
0N/A
643N/A // Use hardware population count instruction if available.
643N/A if (has_hardware_popc()) {
643N/A if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
675N/A FLAG_SET_DEFAULT(UsePopCountInstruction, true);
643N/A }
2664N/A } else if (UsePopCountInstruction) {
2664N/A warning("POPC instruction is not available on this CPU");
2664N/A FLAG_SET_DEFAULT(UsePopCountInstruction, false);
2664N/A }
2664N/A
2664N/A // T4 and newer Sparc cpus have new compare and branch instruction.
2664N/A if (has_cbcond()) {
2664N/A if (FLAG_IS_DEFAULT(UseCBCond)) {
2664N/A FLAG_SET_DEFAULT(UseCBCond, true);
2664N/A }
2664N/A } else if (UseCBCond) {
2664N/A warning("CBCOND instruction is not available on this CPU");
2664N/A FLAG_SET_DEFAULT(UseCBCond, false);
643N/A }
643N/A
2726N/A assert(BlockZeroingLowLimit > 0, "invalid value");
2726N/A if (has_block_zeroing()) {
2726N/A if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
2726N/A FLAG_SET_DEFAULT(UseBlockZeroing, true);
2726N/A }
2726N/A } else if (UseBlockZeroing) {
2726N/A warning("BIS zeroing instructions are not available on this CPU");
2726N/A FLAG_SET_DEFAULT(UseBlockZeroing, false);
2726N/A }
2726N/A
2737N/A assert(BlockCopyLowLimit > 0, "invalid value");
2737N/A if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
2737N/A if (FLAG_IS_DEFAULT(UseBlockCopy)) {
2737N/A FLAG_SET_DEFAULT(UseBlockCopy, true);
2737N/A }
2737N/A } else if (UseBlockCopy) {
2737N/A warning("BIS instructions are not available or expensive on this CPU");
2737N/A FLAG_SET_DEFAULT(UseBlockCopy, false);
2737N/A }
2737N/A
1650N/A#ifdef COMPILER2
2664N/A // T4 and newer Sparc cpus have fast RDPC.
2664N/A if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
2891N/A FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
2664N/A }
2664N/A
1650N/A // Currently not supported anywhere.
1650N/A FLAG_SET_DEFAULT(UseFPUForSpilling, false);
2676N/A
3845N/A MaxVectorSize = 8;
3845N/A
2676N/A assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
1650N/A#endif
1650N/A
2676N/A assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
2676N/A assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
2676N/A
0N/A char buf[512];
2664N/A jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
2664N/A (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
643N/A (has_hardware_popc() ? ", popc" : ""),
2664N/A (has_vis1() ? ", vis1" : ""),
2664N/A (has_vis2() ? ", vis2" : ""),
2664N/A (has_vis3() ? ", vis3" : ""),
2664N/A (has_blk_init() ? ", blk_init" : ""),
2664N/A (has_cbcond() ? ", cbcond" : ""),
2664N/A (is_ultra3() ? ", ultra3" : ""),
2664N/A (is_sun4v() ? ", sun4v" : ""),
2664N/A (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
2664N/A (is_sparc64() ? ", sparc64" : ""),
641N/A (!has_hardware_mul32() ? ", no-mul32" : ""),
641N/A (!has_hardware_div32() ? ", no-div32" : ""),
0N/A (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
0N/A
0N/A // buf is started with ", " or is empty
0N/A _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
0N/A
2629N/A // UseVIS is set to the smallest of what hardware supports and what
2629N/A // the command line requires. I.e., you cannot set UseVIS to 3 on
2629N/A // older UltraSparc which do not support it.
2629N/A if (UseVIS > 3) UseVIS=3;
2629N/A if (UseVIS < 0) UseVIS=0;
2629N/A if (!has_vis3()) // Drop to 2 if no VIS3 support
2629N/A UseVIS = MIN2((intx)2,UseVIS);
2629N/A if (!has_vis2()) // Drop to 1 if no VIS2 support
2629N/A UseVIS = MIN2((intx)1,UseVIS);
2629N/A if (!has_vis1()) // Drop to 0 if no VIS1 support
2629N/A UseVIS = 0;
2629N/A
0N/A#ifndef PRODUCT
0N/A if (PrintMiscellaneous && Verbose) {
2679N/A tty->print("Allocation");
0N/A if (AllocatePrefetchStyle <= 0) {
2679N/A tty->print_cr(": no prefetching");
0N/A } else {
2679N/A tty->print(" prefetching: ");
2679N/A if (AllocatePrefetchInstr == 0) {
2679N/A tty->print("PREFETCH");
2679N/A } else if (AllocatePrefetchInstr == 1) {
2679N/A tty->print("BIS");
2679N/A }
0N/A if (AllocatePrefetchLines > 1) {
2679N/A tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
0N/A } else {
2679N/A tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
0N/A }
0N/A }
0N/A if (PrefetchCopyIntervalInBytes > 0) {
0N/A tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
0N/A }
0N/A if (PrefetchScanIntervalInBytes > 0) {
0N/A tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
0N/A }
0N/A if (PrefetchFieldsAhead > 0) {
0N/A tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
0N/A }
0N/A }
0N/A#endif // PRODUCT
0N/A}
0N/A
0N/Avoid VM_Version::print_features() {
0N/A tty->print_cr("Version:%s", cpu_features());
0N/A}
0N/A
0N/Aint VM_Version::determine_features() {
0N/A if (UseV8InstrsOnly) {
0N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
0N/A return generic_v8_m;
0N/A }
0N/A
0N/A int features = platform_features(unknown_m); // platform_features() is os_arch specific
0N/A
0N/A if (features == unknown_m) {
0N/A features = generic_v9_m;
0N/A warning("Cannot recognize SPARC version. Default to V9");
0N/A }
0N/A
1968N/A assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
1968N/A if (UseNiagaraInstrs) { // Force code generation for Niagara
1968N/A if (is_T_family(features)) {
0N/A // Happy to accomodate...
0N/A } else {
0N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
1968N/A features |= T_family_m;
0N/A }
0N/A } else {
1968N/A if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
0N/A NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
1968N/A features &= ~(T_family_m | T1_model_m);
0N/A } else {
0N/A // Happy to accomodate...
0N/A }
0N/A }
0N/A
0N/A return features;
0N/A}
0N/A
0N/Astatic int saved_features = 0;
0N/A
0N/Avoid VM_Version::allow_all() {
0N/A saved_features = _features;
0N/A _features = all_features_m;
0N/A}
0N/A
0N/Avoid VM_Version::revert() {
0N/A _features = saved_features;
0N/A}
10N/A
10N/Aunsigned int VM_Version::calc_parallel_worker_threads() {
10N/A unsigned int result;
4017N/A if (is_M_series()) {
4017N/A // for now, use same gc thread calculation for M-series as for niagara-plus
4017N/A // in future, we may want to tweak parameters for nof_parallel_worker_thread
4017N/A result = nof_parallel_worker_threads(5, 16, 8);
4017N/A } else if (is_niagara_plus()) {
10N/A result = nof_parallel_worker_threads(5, 16, 8);
10N/A } else {
10N/A result = nof_parallel_worker_threads(5, 8, 8);
10N/A }
10N/A return result;
10N/A}