2006N/A// Copyright (c) 1998, 2011, Oracle
and/or its affiliates. All rights reserved.
0N/A// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A// This code is free software; you can redistribute it
and/or modify it
0N/A// under the terms of the GNU General Public License version 2 only, as
0N/A// published by the Free Software Foundation.
0N/A// This code is distributed in the hope that it will be useful, but WITHOUT
0N/A// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A// version 2 for more details (a copy is included in the LICENSE file that
0N/A// accompanied this code).
0N/A// You should have received a copy of the GNU General Public License version
0N/A// 2 along with this work; if not, write to the Free Software Foundation,
0N/A// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1472N/A// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
0N/A// SPARC Architecture Description File
0N/A//----------REGISTER DEFINITION BLOCK------------------------------------------
0N/A// This information is used by the matcher and the register allocator to
0N/A// describe individual registers and classes of registers within the target
0N/A//----------Architecture Description Register Definitions----------------------
0N/A// "reg_def" name ( register save type, C convention save type,
0N/A// ideal register type, encoding, vm name );
0N/A// Register Save Types:
0N/A// NS = No-Save: The register allocator assumes that these registers
0N/A// can be used without saving upon entry to the method, &
0N/A// that they do not need to be saved at call sites.
0N/A// SOC = Save-On-Call: The register allocator assumes that these registers
0N/A// can be used without saving upon entry to the method,
0N/A// but that they must be saved at call sites.
0N/A// SOE = Save-On-Entry: The register allocator assumes that these registers
0N/A// must be saved before using them upon entry to the
0N/A// method, but they do not need to be saved at call
0N/A// AS = Always-Save: The register allocator assumes that these registers
0N/A// must be saved before using them upon entry to the
0N/A// method, & that they must be saved at call sites.
0N/A// Ideal Register Type is used to determine how to save & restore a
0N/A// The encoding number is the actual bit-pattern placed into the opcodes.
0N/A// ----------------------------
0N/A// ----------------------------
0N/A// Need to expose the
hi/lo aspect of 64-bit registers
0N/A// This register set is used for both the 64-bit build and
0N/A// the 32-bit build with 1-register longs.
0N/A// Global Registers 0-7
0N/Areg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
0N/Areg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
0N/Areg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
0N/Areg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
0N/Areg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
0N/Areg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
0N/Areg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
0N/Areg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
0N/Areg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
0N/Areg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
0N/Areg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
0N/Areg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
0N/Areg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
0N/Areg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
0N/Areg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
0N/Areg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
0N/A// Output Registers 0-7
0N/Areg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
0N/Areg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
0N/Areg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
0N/Areg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
0N/Areg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
0N/Areg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
0N/Areg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
0N/Areg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
0N/Areg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
0N/Areg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
0N/Areg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
0N/Areg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
0N/Areg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
0N/Areg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
0N/Areg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
0N/Areg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
0N/A// Local Registers 0-7
0N/Areg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
0N/Areg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
0N/Areg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
0N/Areg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
0N/Areg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
0N/Areg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
0N/Areg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
0N/Areg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
0N/Areg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
0N/Areg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
0N/Areg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
0N/Areg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
0N/Areg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
0N/Areg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
0N/Areg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
0N/Areg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
0N/A// Input Registers 0-7
0N/Areg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
0N/Areg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
0N/Areg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
0N/Areg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
0N/Areg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
0N/Areg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
0N/Areg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
0N/Areg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
0N/Areg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
0N/Areg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
0N/Areg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
0N/Areg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
0N/Areg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
0N/Areg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
0N/Areg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
0N/Areg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
0N/A// ----------------------------
0N/A// ----------------------------
0N/Areg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
0N/Areg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
0N/Areg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
0N/Areg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
0N/Areg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
0N/Areg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
0N/Areg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
0N/Areg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
0N/Areg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
0N/Areg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
0N/Areg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
0N/Areg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
0N/Areg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
0N/Areg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
0N/Areg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
0N/Areg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
0N/Areg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
0N/Areg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
0N/Areg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
0N/Areg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
0N/Areg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
0N/Areg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
0N/Areg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
0N/Areg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
0N/Areg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
0N/Areg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
0N/Areg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
0N/Areg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
0N/Areg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
0N/Areg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
0N/Areg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
0N/Areg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
0N/A// The rules of ADL require that double registers be defined in pairs.
0N/A// Each pair must be two 32-bit values, but not necessarily a pair of
0N/A// single float registers. In each pair, ADLC-assigned register numbers
0N/A// must be adjacent, with the lower number even. Finally, when the
0N/A// CPU stores such a register pair to memory, the word associated with
0N/A// the lower ADLC-assigned number must be stored to the lower address.
0N/A// These definitions specify the actual bit encodings of the sparc
0N/A// wants 0-63, so we have to convert every time we want to use fp regs
0N/A// with the macroassembler, using reg_to_DoubleFloatRegister_object().
605N/A// 255 is a flag meaning "don't go here".
0N/A// I believe we can't handle callee-save doubles D32 and up until
0N/A// the place in the sparc stack crawler that asserts on the 255 is
1007N/Areg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
1007N/Areg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
1007N/Areg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
1007N/Areg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
1007N/Areg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
1007N/Areg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
1007N/Areg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
1007N/Areg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
1007N/Areg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
1007N/Areg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
1007N/Areg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
1007N/Areg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
1007N/Areg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
1007N/Areg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
1007N/Areg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
1007N/Areg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
1007N/Areg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
1007N/Areg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
1007N/Areg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
1007N/Areg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
1007N/Areg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
1007N/Areg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
1007N/Areg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
1007N/Areg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
1007N/Areg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
1007N/Areg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
1007N/Areg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
1007N/Areg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
1007N/Areg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
1007N/Areg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
1007N/Areg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
1007N/Areg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
0N/A// ----------------------------
0N/A// Condition Codes Flag Registers
0N/A// I tried to break out ICC and XCC but it's not very pretty.
0N/A// Every Sparc instruction which
defs/kills one also kills the other.
0N/A// Hence every compare instruction which defs one kind of flags ends
0N/A// up needing a kill of the other.
0N/Areg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
0N/Areg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
0N/Areg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
0N/Areg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
0N/Areg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
0N/A// ----------------------------
0N/A// Specify the enum values for the registers. These enums are only used by the
0N/A// OptoReg "class". We can convert these enum values at will to VMReg when needed
0N/A// for visibility to the rest of the vm. The order of this enum influences the
0N/A// register allocator so having the freedom to set this order and not be stuck
0N/A// with the order that is natural for the rest of the vm is worth it.
0N/A R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
0N/A R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
0N/A R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
0N/A R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
0N/A// Note that a register is not allocatable unless it is also mentioned
0N/A// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
0N/A // The first registers listed here are those most likely to be used
0N/A // as temporaries. We move
F0..F7 away from the front of the list,
0N/A // to reduce the likelihood of interferences with parameters and
0N/A // return values. Likewise, we avoid using
F0/F1 for parameters,
0N/A // since they are used for return values.
0N/A // This FPU fine-tuning is worth about 1% on the SPEC geomean.
0N/A R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
0N/A R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
0N/A R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
0N/A R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
0N/A R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
0N/A R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
0N/A R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
0N/A R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
0N/Aalloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
0N/A//----------Architecture Description Register Classes--------------------------
0N/A// Several register classes are automatically defined based upon information in
0N/A// this architecture description.
0N/A// 1) reg_class inline_cache_reg ( as defined in frame section )
0N/A// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
0N/A// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
0N/A// G0 is not included in integer class since it has special meaning.
0N/Areg_class g0_reg(R_G0);
0N/A// ----------------------------
0N/A// Integer Register Classes
0N/A// ----------------------------
0N/A// Exclusions from i_reg:
0N/A// R_G0: hardwired zero
0N/A// R_G2: reserved by HotSpot to the TLS register (invariant within Java)
0N/A// R_G6: reserved by Solaris ABI to tools
0N/A// R_G7: reserved by Solaris ABI to libthread
0N/A// R_O7: Used as a temp in many encodings
0N/Areg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
0N/A// Class for all integer registers, except the G registers. This is used for
0N/A// encodings which use G registers as temps. The regular inputs to such
0N/A// instructions use a "notemp_" prefix, as a hack to ensure that the allocator
0N/A// will not put an input into a temp register.
0N/Areg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
0N/Areg_class g1_regI(R_G1);
0N/Areg_class g3_regI(R_G3);
0N/Areg_class g4_regI(R_G4);
0N/Areg_class o0_regI(R_O0);
0N/Areg_class o7_regI(R_O7);
0N/A// ----------------------------
0N/A// Pointer Register Classes
0N/A// ----------------------------
0N/A// 64-bit build means 64-bit pointers means
hi/lo pairs
0N/Areg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
0N/A R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
0N/A R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
0N/A R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
0N/A// Lock encodings use G3 and G4 internally
0N/Areg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
0N/A R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
0N/A R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
0N/A R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
0N/A// Special class for storeP instructions, which can store SP or RPC to TLS.
0N/A// It is also used for memory addressing, allowing direct TLS addressing.
0N/Areg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
0N/A R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
0N/A R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
0N/A R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
0N/A// R_L7 is the lowest-priority callee-save (
i.e., NS) register
0N/A// We use it to save R_G2 across calls out of Java.
0N/Areg_class l7_regP(R_L7H,R_L7);
0N/A// Other special pointer regs
0N/Areg_class g1_regP(R_G1H,R_G1);
0N/Areg_class g2_regP(R_G2H,R_G2);
0N/Areg_class g3_regP(R_G3H,R_G3);
0N/Areg_class g4_regP(R_G4H,R_G4);
0N/Areg_class g5_regP(R_G5H,R_G5);
0N/Areg_class i0_regP(R_I0H,R_I0);
0N/Areg_class o0_regP(R_O0H,R_O0);
0N/Areg_class o1_regP(R_O1H,R_O1);
0N/Areg_class o2_regP(R_O2H,R_O2);
0N/Areg_class o7_regP(R_O7H,R_O7);
0N/A// 32-bit build means 32-bit pointers means 1 register.
0N/Areg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
0N/A R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
0N/A R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
0N/A R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
0N/A// Lock encodings use G3 and G4 internally
0N/Areg_class lock_ptr_reg(R_G1, R_G5,
0N/A R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
0N/A R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
0N/A R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
0N/A// Special class for storeP instructions, which can store SP or RPC to TLS.
0N/A// It is also used for memory addressing, allowing direct TLS addressing.
0N/Areg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
0N/A R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
0N/A R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
0N/A R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
0N/A// R_L7 is the lowest-priority callee-save (
i.e., NS) register
0N/A// We use it to save R_G2 across calls out of Java.
0N/Areg_class l7_regP(R_L7);
0N/A// Other special pointer regs
0N/Areg_class g1_regP(R_G1);
0N/Areg_class g2_regP(R_G2);
0N/Areg_class g3_regP(R_G3);
0N/Areg_class g4_regP(R_G4);
0N/Areg_class g5_regP(R_G5);
0N/Areg_class i0_regP(R_I0);
0N/Areg_class o0_regP(R_O0);
0N/Areg_class o1_regP(R_O1);
0N/Areg_class o2_regP(R_O2);
0N/Areg_class o7_regP(R_O7);
0N/A// ----------------------------
0N/A// Long Register Classes
0N/A// ----------------------------
0N/A// Longs in 1 register. Aligned adjacent
hi/lo pairs.
0N/A// Note: O7 is never in this class; it is sometimes used as an encoding temp.
0N/Areg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
0N/A ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
0N/A// 64-bit, longs in 1 register: use all 64-bit integer registers
0N/A// 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
0N/A ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
0N/A ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
0N/Areg_class g1_regL(R_G1H,R_G1);
420N/Areg_class g3_regL(R_G3H,R_G3);
0N/Areg_class o2_regL(R_O2H,R_O2);
0N/Areg_class o7_regL(R_O7H,R_O7);
0N/A// ----------------------------
0N/A// Special Class for Condition Code Flags Register
0N/Areg_class int_flags(CCR);
0N/Areg_class float_flags(FCC0,FCC1,FCC2,FCC3);
0N/Areg_class float_flag0(FCC0);
0N/A// ----------------------------
0N/A// Float Point Register Classes
0N/A// ----------------------------
0N/A// Skip
F30/F31, they are reserved for mem-mem copies
0N/Areg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
0N/A// Paired floating point registers--they show up in the same order as the floats,
0N/A// but they are used with the "Op_RegD" type, and always occur in
even/odd pairs.
0N/Areg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
0N/A R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
0N/A /* Use extra V9 double registers; this AD file does not support V8 */
0N/A R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
0N/A R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
0N/A// Paired floating point registers--they show up in the same order as the floats,
0N/A// but they are used with the "Op_RegD" type, and always occur in
even/odd pairs.
0N/A// This class is usable for mis-aligned loads as happen in I2C adapters.
0N/Areg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
2629N/A R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
0N/A//----------DEFINITION BLOCK---------------------------------------------------
0N/A// Define name --> value mappings to inform the ADLC of an integer valued name
0N/A// Current support includes integer values in the range [0, 0x7FFFFFFF]
0N/A// int_def <name> ( <int_value>, <expression>);
0N/A// Generated Code in ad_<arch>.hpp
0N/A// #define <name> (<expression>)
0N/A// // value == <int_value>
0N/A// Generated code in ad_<arch>.cpp adlc_verification()
0N/A// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
0N/A// The default cost (of an ALU instruction).
0N/A int_def DEFAULT_COST ( 100, 100);
0N/A int_def HUGE_COST (1000000, 1000000);
0N/A// Memory refs are twice as expensive as run-of-the-mill.
0N/A int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
0N/A// Branches are even more expensive.
0N/A int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
0N/A int_def CALL_COST ( 300, DEFAULT_COST * 3);
0N/A//----------SOURCE BLOCK-------------------------------------------------------
0N/A// This is a block of C++ code which provides values, functions, and
0N/A// definitions necessary in the rest of the architecture description
0N/Aextern bool can_branch_register( Node *bol, Node *cmp );
2726N/Aextern bool use_block_zeroing(Node* count);
0N/A// Macros to extract hi & lo halves from a long pair.
0N/A// G0 is not part of any long pair, so assert on that.
605N/A// Prevents accidentally using G1 instead of G0.
0N/A#define LONG_HI_REG(x) (x)
0N/A#define LONG_LO_REG(x) (x)
0N/A// tertiary op of a LoadP or StoreP encoding
0N/Astatic FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
0N/Astatic FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
0N/Astatic Register reg_to_register_object(int register_encoding);
0N/A// Check for being able to use a V9 branch-on-register. Requires a
0N/A// extended. Doesn't work following an integer ADD, for example, because of
0N/A// overflow (-1 incremented yields 0 plus a carry in the high-order word). On
0N/A// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
0N/A// replace them with zero, which could become sign-extension in a different OS
0N/A// release. There's no obvious reason why an interrupt will ever fill these
0N/A// bits with non-zero junk (the registers are reloaded with standard LD
0N/A// instructions which either zero-fill or sign-fill).
0N/Abool can_branch_register( Node *bol, Node *cmp ) {
0N/A if( !BranchOnRegister ) return false;
0N/A if( cmp->Opcode() == Op_CmpP )
0N/A return true; // No problems with pointer compares
0N/A if( cmp->Opcode() == Op_CmpL )
0N/A return true; // No problems with long compares
0N/A if( !SparcV9RegsHiBitsZero ) return false;
0N/A if( bol->as_Bool()->_test._test != BoolTest::ne &&
0N/A bol->as_Bool()->_test._test != BoolTest::eq )
0N/A // Check for comparing against a 'safe' value. Any operation which
0N/A // clears out the high word is safe. Thus, loads and certain shifts
0N/A // are safe, as are non-negative constants. Any operation which
0N/A // preserves zero bits in the high word is safe as long as each of its
0N/A // inputs are safe. Thus, phis and bitwise booleans are safe if their
0N/A // inputs are safe. At present, the only important case to recognize
0N/A // seems to be loads. Constants should fold away, and shifts &
0N/A // logicals can use the 'cc' forms.
0N/A Node *x = cmp->in(1);
0N/A if( x->is_Load() ) return true;
0N/A for( uint i = 1; i < x->req(); i++ )
0N/A if( !x->in(i)->is_Load() )
2726N/Abool use_block_zeroing(Node* count) {
2726N/A // Use BIS for zeroing if count is not constant
2726N/A // or it is >= BlockZeroingLowLimit.
2726N/A return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
0N/A// ****************************************************************************
0N/A// REQUIRED FUNCTIONALITY
0N/A// !!!!! Special hack to get all type of calls to specify the byte offset
0N/A// from the start of the call to the point where the return address
0N/A// The "return address" is the address of the call instruction, plus 8.
0N/Aint MachCallStaticJavaNode::ret_addr_offset() {
1487N/A int offset = NativeCall::instruction_size; // call; delay slot
0N/Aint MachCallDynamicJavaNode::ret_addr_offset() {
0N/A int vtable_index = this->_vtable_index;
0N/A if (vtable_index < 0) {
0N/A // must be invalid_vtable_index, not nonvirtual_vtable_index
0N/A assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
0N/A return (NativeMovConstReg::instruction_size +
0N/A NativeCall::instruction_size); // sethi; setlo; call; delay slot
0N/A assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
0N/A int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
0N/A int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
113N/A if (UseCompressedOops) {
642N/A assert(Universe::heap() != NULL, "java heap should be initialized");
642N/A if (Universe::narrow_oop_base() == NULL)
642N/A klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
642N/A klass_load_size = 3*BytesPerInstWord;
113N/A klass_load_size = 1*BytesPerInstWord;
2957N/A if (Assembler::is_simm13(v_off)) {
113N/A return klass_load_size +
113N/A (2*BytesPerInstWord + // ld_ptr, ld_ptr
0N/A NativeCall::instruction_size); // call; delay slot
113N/A return klass_load_size +
113N/A (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
0N/A NativeCall::instruction_size); // call; delay slot
0N/Aint MachCallRuntimeNode::ret_addr_offset() {
2006N/A if (MacroAssembler::is_far_target(entry_point())) {
2006N/A return NativeFarCall::instruction_size;
2006N/A return NativeCall::instruction_size;
0N/A return NativeCall::instruction_size; // call; delay slot
0N/A// Indicate if the safepoint node needs the polling page as an input.
0N/A// Since Sparc does not have absolute addressing, it does.
0N/Abool SafePointNode::needs_polling_address_input() {
0N/A// emit an interrupt that is caught by the debugger (for debugging compiler)
0N/Avoid emit_break(CodeBuffer &cbuf) {
0N/A MacroAssembler _masm(&cbuf);
0N/A __ breakpoint_trap();
0N/Avoid MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
0N/Avoid MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/Auint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
0N/A return MachNode::size(ra_);
0N/Avoid emit_jmpl(CodeBuffer &cbuf, int jump_target) {
0N/A MacroAssembler _masm(&cbuf);
0N/A Register rdest = reg_to_register_object(jump_target);
0N/A __ delayed()->nop();
0N/A// Traceable jump and set exception pc
0N/Avoid emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
0N/A MacroAssembler _masm(&cbuf);
0N/A Register rdest = reg_to_register_object(jump_target);
0N/A __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
0N/Avoid emit_nop(CodeBuffer &cbuf) {
0N/A MacroAssembler _masm(&cbuf);
0N/Avoid emit_illtrap(CodeBuffer &cbuf) {
0N/A MacroAssembler _masm(&cbuf);
0N/Aintptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
0N/A assert(n->rule() != loadUB_rule, "");
0N/A intptr_t offset = 0;
0N/A const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
0N/A const Node* addr = n->get_base_and_disp(offset, adr_type);
0N/A assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
0N/A assert(addr != NULL && addr != (Node*)-1, "invalid addr");
0N/A assert(addr->bottom_type()->isa_oopptr() == atype, "");
0N/A atype = atype->add_offset(offset);
0N/A assert(disp32 == offset, "wrong disp32");
0N/A return atype->_offset;
0N/Aintptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
0N/A assert(n->rule() != loadUB_rule, "");
0N/A intptr_t offset = 0;
0N/A Node* addr = n->in(2);
0N/A assert(addr->bottom_type()->isa_oopptr() == atype, "");
0N/A if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
0N/A Node* a = addr->in(2/*AddPNode::Address*/);
0N/A Node* o = addr->in(3/*AddPNode::Offset*/);
0N/A offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
0N/A atype = a->bottom_type()->is_ptr()->add_offset(offset);
0N/A assert(atype->isa_oop_ptr(), "still an oop");
0N/A offset = atype->is_ptr()->_offset;
0N/A if (offset != Type::OffsetBot) offset += disp32;
1915N/Astatic inline jdouble replicate_immI(int con, int count, int width) {
1915N/A // Load a constant replicated "count" times with width "width"
1915N/A elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
1915N/A for (int i = 0; i < count - 1; i++) {
1915N/A jdouble dval = *((jdouble*) &val); // coerce to double type
0N/A// Standard Sparc opcode form2 field breakdown
0N/Astatic inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
0N/A f0 &= (1<<19)-1; // Mask displacement to 19 bits
0N/A int op = (f30 << 30) |
0N/A// Standard Sparc opcode form2 field breakdown
0N/Astatic inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
0N/A f0 >>= 10; // Drop 10 bits
0N/A f0 &= (1<<22)-1; // Mask displacement to 22 bits
0N/A int op = (f30 << 30) |
0N/A// Standard Sparc opcode form3 field breakdown
0N/Astatic inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
0N/A int op = (f30 << 30) |
0N/A// Standard Sparc opcode form3 field breakdown
0N/Astatic inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
0N/A simm13 &= (1<<13)-1; // Mask to 13 bits
0N/A int op = (f30 << 30) |
0N/A (1 << 13) | // bit to indicate immediate-mode
0N/Astatic inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
0N/A simm10 &= (1<<10)-1; // Mask to 10 bits
0N/A emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
0N/A// Helper function for VerifyOops in emit_form3_mem_reg
0N/Avoid verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
0N/A warning("VerifyOops encountered unexpected instruction:");
0N/A warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
0N/Avoid emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
0N/A int src1_enc, int disp32, int src2_enc, int dst_enc) {
0N/A // The following code implements the +VerifyOops feature.
0N/A // It verifies oop values which are loaded into or stored out of
0N/A // the current method activation. +VerifyOops complements techniques
0N/A // like ScavengeALot, because it eagerly inspects oops in transit,
0N/A // as they enter or leave the stack, as opposed to ScavengeALot,
0N/A // which inspects oops "at rest", in the stack or heap, at safepoints.
0N/A // For this reason, +VerifyOops can sometimes detect bugs very close
0N/A // to their point of creation. It can also serve as a cross-check
0N/A // on the validity of oop maps, when used toegether with ScavengeALot.
0N/A // It would be good to verify oops at other points, especially
0N/A // when an oop is used as a base pointer for a load or store.
0N/A // This is presently difficult, because it is hard to know when
0N/A // a base address is biased or not. (If we had such information,
0N/A // it would be easy and useful to make a two-argument version of
0N/A // verify_oop which unbiases the base, and performs verification.)
0N/A assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
0N/A bool is_verified_oop_base = false;
0N/A bool is_verified_oop_load = false;
0N/A bool is_verified_oop_store = false;
0N/A if (VerifyOops && src1_enc != R_SP_enc) {
0N/A // classify the op, mainly for an assert check
0N/A int st_op = 0, ld_op = 0;
0N/A case Assembler::stb_op3: st_op = Op_StoreB; break;
0N/A case Assembler::sth_op3: st_op = Op_StoreC; break;
0N/A case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
0N/A case Assembler::stw_op3: st_op = Op_StoreI; break;
0N/A case Assembler::std_op3: st_op = Op_StoreL; break;
0N/A case Assembler::stf_op3: st_op = Op_StoreF; break;
0N/A case Assembler::stdf_op3: st_op = Op_StoreD; break;
0N/A case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
558N/A case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
0N/A case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
0N/A case Assembler::ldx_op3: // may become LoadP or stay LoadI
0N/A case Assembler::ldsw_op3: // may become LoadP or stay LoadI
0N/A case Assembler::lduw_op3: ld_op = Op_LoadI; break;
0N/A case Assembler::ldd_op3: ld_op = Op_LoadL; break;
0N/A case Assembler::ldf_op3: ld_op = Op_LoadF; break;
0N/A case Assembler::lddf_op3: ld_op = Op_LoadD; break;
0N/A case Assembler::ldub_op3: ld_op = Op_LoadB; break;
0N/A case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
0N/A default: ShouldNotReachHere();
0N/A if (tertiary == REGP_OP) {
0N/A if (st_op == Op_StoreI) st_op = Op_StoreP;
0N/A else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
0N/A else ShouldNotReachHere();
0N/A // inputs are (0:control, 1:memory, 2:address, 3:value)
0N/A Node* n2 = n->in(3);
0N/A const Type* t = n2->bottom_type();
0N/A is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
0N/A const Type* t = n->bottom_type();
0N/A is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
0N/A // inputs are (0:control, 1:memory, 2:address)
0N/A if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
0N/A !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
0N/A !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
0N/A !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
0N/A !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
0N/A !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
0N/A !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
0N/A !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
0N/A !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
2732N/A !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
1491N/A !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
1491N/A !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
1491N/A !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
1491N/A !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
0N/A !(n->rule() == loadUB_rule)) {
0N/A verify_oops_warning(n, n->ideal_Opcode(), ld_op);
0N/A // inputs are (0:control, 1:memory, 2:address, 3:value)
0N/A if (!(n->ideal_Opcode()==st_op) && // Following are special cases
0N/A !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
0N/A !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
0N/A !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
0N/A !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
1491N/A !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
1491N/A !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
1491N/A !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
0N/A !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
0N/A verify_oops_warning(n, n->ideal_Opcode(), st_op);
0N/A if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
0N/A Node* addr = n->in(2);
0N/A if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
0N/A const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
0N/A if (atype != NULL) {
0N/A intptr_t offset = get_offset_from_base(n, atype, disp32);
0N/A intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
0N/A if (offset != offset_2) {
0N/A get_offset_from_base(n, atype, disp32);
0N/A get_offset_from_base_2(n, atype, disp32);
0N/A assert(offset == offset_2, "different offsets");
0N/A if (offset == disp32) {
0N/A // we now know that src1 is a true oop pointer
0N/A is_verified_oop_base = true;
0N/A if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
0N/A if( primary == Assembler::ldd_op3 ) {
0N/A is_verified_oop_base = false; // Cannot 'ldd' into O7
0N/A dst_enc = R_O7_enc; // Load into O7; preserve source oop
0N/A assert(src1_enc != dst_enc, "");
0N/A if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
0N/A || offset == oopDesc::mark_offset_in_bytes())) {
0N/A // loading the mark should not be allowed either, but
0N/A // we don't check this since it conflicts with InlineObjectHash
0N/A // usage of LoadINode to get the mark. We could keep the
0N/A // check if we create a new LoadMarkNode
0N/A // but do not verify the object before its header is initialized
0N/A ShouldNotReachHere();
0N/A instr = (Assembler::ldst_op << 30)
0N/A uint index = src2_enc;
0N/A if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
0N/A // We should have a compiler bailout here rather than a guarantee.
0N/A // Better yet would be some mechanism to handle variable-size matches correctly.
0N/A guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
0N/A // bit 13 is already zero
0N/A instr |= 0x00002000; // set bit 13 to one
0N/A instr |= disp & 0x1FFF;
0N/A MacroAssembler _masm(&cbuf);
0N/A if (is_verified_oop_base) {
0N/A __ verify_oop(reg_to_register_object(src1_enc));
0N/A if (is_verified_oop_store) {
0N/A __ verify_oop(reg_to_register_object(dst_enc));
0N/A if (tmp_enc != -1) {
0N/A __ mov(O7, reg_to_register_object(tmp_enc));
0N/A if (is_verified_oop_load) {
0N/A __ verify_oop(reg_to_register_object(dst_enc));
2006N/Avoid emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
0N/A // The method which records debug information at every safepoint
0N/A // expects the call to be the first instruction in the snippet as
0N/A // it creates a PcDesc structure which tracks the offset of a call
0N/A // from the start of the codeBlob. This offset is computed as
0N/A // code_end() - code_begin() of the code which has been emitted
0N/A // In this particular case we have skirted around the problem by
0N/A // putting the "mov" instruction in the delay slot but the problem
0N/A // solution using relocations would be needed.
0N/A MacroAssembler _masm(&cbuf);
0N/A // We flush the current window just so that there is a valid stack copy
0N/A // the fact that the current window becomes active again instantly is
0N/A // not a problem there is nothing live in it.
0N/A int startpos = __ offset();
2006N/A __ call((address)entry_point, rtype);
0N/A if (preserve_g2) __ delayed()->mov(G2, L7);
0N/A else __ delayed()->nop();
0N/A if (preserve_g2) __ mov(L7, G2);
0N/A if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
0N/A // Trash argument dump slots.
0N/A __ set(0xb0b8ac0db0b8ac0d, G1);
0N/A __ stx(G1, SP, STACK_BIAS + 0x80);
0N/A __ stx(G1, SP, STACK_BIAS + 0x88);
0N/A __ stx(G1, SP, STACK_BIAS + 0x90);
0N/A __ stx(G1, SP, STACK_BIAS + 0x98);
0N/A __ stx(G1, SP, STACK_BIAS + 0xA0);
0N/A __ stx(G1, SP, STACK_BIAS + 0xA8);
0N/A // this is also a native call, so smash the first 7 stack locations,
0N/A // and the various registers
0N/A // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
0N/A // while [SP+0x44..0x58] are the argument dump slots.
0N/A __ set((intptr_t)0xbaadf00d, G1);
0N/A __ sllx(G1, 32, G1);
0N/A __ stx(G1, SP, 0x40);
0N/A __ stx(G1, SP, 0x48);
0N/A __ stx(G1, SP, 0x50);
0N/A __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
0N/A//=============================================================================
0N/A// REQUIRED FUNCTIONALITY for encoding
0N/Avoid emit_lo(CodeBuffer &cbuf, int val) { }
0N/Avoid emit_hi(CodeBuffer &cbuf, int val) { }
0N/A//=============================================================================
2964N/Aconst RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
2957N/Aint Compile::ConstantTable::calculate_table_base_offset() const {
2957N/A if (UseRDPCForConstantTableBase) {
2957N/A // The table base offset might be less but then it fits into
2957N/A // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
2957N/A return Assembler::min_simm13();
2957N/A int offset = -(size() / 2);
2957N/A if (!Assembler::is_simm13(offset)) {
2957N/A offset = Assembler::min_simm13();
1915N/Avoid MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1915N/A Compile::ConstantTable& constant_table = C->constant_table();
1915N/A MacroAssembler _masm(&cbuf);
1915N/A Register r = as_Register(ra_->get_encode(this));
2957N/A CodeSection* consts_section = __ code()->consts();
2957N/A int consts_size = consts_section->align_at_start(consts_section->size());
1915N/A if (UseRDPCForConstantTableBase) {
1915N/A // For the following RDPC logic to work correctly the consts
1915N/A // section must be allocated right before the insts section. This
1915N/A // assert checks for that. The layout and the SECT_* constants
1915N/A assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
2957N/A int insts_offset = __ offset();
2957N/A // |----------- consts section ------------|----------- insts section -----------...
2957N/A // |------ constant table -----|- padding -|------------------x----
2957N/A // \ current PC (RDPC instruction)
2957N/A // |<------------- consts_size ----------->|<- insts_offset ->|
2957N/A // The table base offset is later added to the load displacement
2957N/A // so it has to be negative.
2957N/A int table_base_offset = -(consts_size + insts_offset);
1915N/A // If the displacement from the current PC to the constant table
1915N/A // base fits into simm13 we set the constant table base to the
2957N/A if (Assembler::is_simm13(table_base_offset)) {
2957N/A // Otherwise we set the constant table base offset to the
2957N/A // maximum negative displacement of load instructions to keep
2957N/A // the disp as small as possible:
2957N/A // |<------------- consts_size ----------->|<- insts_offset ->|
2957N/A // |<--------- min_simm13 --------->|<-------- disp --------->|
2957N/A table_base_offset = Assembler::min_simm13();
2957N/A disp = (consts_size + insts_offset) + table_base_offset;
1915N/A assert(r != O7, "need temporary");
1915N/A __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1915N/A // Materialize the constant table base.
1915N/A RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1915N/A AddressLiteral base(baseaddr, rspec);
1915N/Auint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1915N/A if (UseRDPCForConstantTableBase) {
1915N/A // This is really the worst case but generally it's only 1 instruction.
1964N/A return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1964N/A return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1915N/Avoid MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1915N/A ra_->dump_register(this, reg);
1915N/A if (UseRDPCForConstantTableBase) {
1915N/A st->print("RDPC %s\t! constant table base", reg);
1915N/A st->print("SET &constanttable,%s\t! constant table base", reg);
1915N/A//=============================================================================
0N/Avoid MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
0N/A Compile* C = ra_->C;
0N/A for (int i = 0; i < OptoPrologueNops; i++) {
0N/A st->print_cr("NOP"); st->print("\t");
0N/A if( VerifyThread ) {
0N/A st->print_cr("Verify_Thread"); st->print("\t");
0N/A size_t framesize = C->frame_slots() << LogBytesPerInt;
0N/A // Calls to C2R adapters often do not accept exceptional returns.
0N/A // We require that their callers must bang for them. But be careful, because
0N/A // some VM calls (such as call site linkage) can use several kilobytes of
0N/A // stack. But the stack safety zone should account for that.
0N/A // See bugs 4446381, 4468289, 4497237.
0N/A if (C->need_stack_bang(framesize)) {
0N/A st->print_cr("! stack bang"); st->print("\t");
0N/A if (Assembler::is_simm13(-framesize)) {
0N/A st->print ("SAVE R_SP,-%d,R_SP",framesize);
0N/A st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
0N/A st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
0N/A st->print ("SAVE R_SP,R_G3,R_SP");
0N/Avoid MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/A Compile* C = ra_->C;
0N/A MacroAssembler _masm(&cbuf);
0N/A for (int i = 0; i < OptoPrologueNops; i++) {
0N/A size_t framesize = C->frame_slots() << LogBytesPerInt;
0N/A assert(framesize >= 16*wordSize, "must have room for reg. save area");
0N/A assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
0N/A // Calls to C2R adapters often do not accept exceptional returns.
0N/A // We require that their callers must bang for them. But be careful, because
0N/A // some VM calls (such as call site linkage) can use several kilobytes of
0N/A // stack. But the stack safety zone should account for that.
0N/A // See bugs 4446381, 4468289, 4497237.
0N/A if (C->need_stack_bang(framesize)) {
0N/A __ generate_stack_overflow_check(framesize);
0N/A if (Assembler::is_simm13(-framesize)) {
0N/A __ save(SP, -framesize, SP);
0N/A __ sethi(-framesize & ~0x3ff, G3);
0N/A __ add(G3, -framesize & 0x3ff, G3);
0N/A __ save(SP, G3, SP);
0N/A C->set_frame_complete( __ offset() );
2957N/A if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
2957N/A // NOTE: We set the table base offset here because users might be
2957N/A // emitted before MachConstantBaseNode.
2957N/A Compile::ConstantTable& constant_table = C->constant_table();
0N/Auint MachPrologNode::size(PhaseRegAlloc *ra_) const {
0N/A return MachNode::size(ra_);
0N/Aint MachPrologNode::reloc() const {
0N/A return 10; // a large enough number
0N/A//=============================================================================
0N/Avoid MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
0N/A Compile* C = ra_->C;
0N/A if( do_polling() && ra_->C->is_method_compilation() ) {
0N/A st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
0N/A st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
0N/A st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
0N/A st->print("RET\n\t");
0N/A st->print("RESTORE");
0N/Avoid MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A Compile* C = ra_->C;
0N/A // If this does safepoint polling, then do it here
0N/A if( do_polling() && ra_->C->is_method_compilation() ) {
727N/A AddressLiteral polling_page(os::get_polling_page());
727N/A __ sethi(polling_page, L0);
0N/A __ relocate(relocInfo::poll_return_type);
0N/A __ ld_ptr( L0, 0, G0 );
0N/A // If this is a return, then stuff the restore in the delay slot
0N/A if( do_polling() ) {
0N/A __ delayed()->restore();
0N/Auint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
0N/A return MachNode::size(ra_);
0N/Aint MachEpilogNode::reloc() const {
0N/A return 16; // a large enough number
0N/Aconst Pipeline * MachEpilogNode::pipeline() const {
0N/A return MachNode::pipeline_class();
0N/Aint MachEpilogNode::safepoint_offset() const {
0N/A assert( do_polling(), "no return for this epilog node");
1964N/A return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
0N/A//=============================================================================
0N/A// Figure out which register class each belongs in: rc_int, rc_float, rc_stack
0N/Aenum RC { rc_bad, rc_int, rc_float, rc_stack };
0N/Astatic enum RC rc_class( OptoReg::Name reg ) {
0N/A if( !OptoReg::is_valid(reg) ) return rc_bad;
0N/A if (OptoReg::is_stack(reg)) return rc_stack;
0N/A VMReg r = OptoReg::as_VMReg(reg);
0N/A if (r->is_Register()) return rc_int;
0N/A assert(r->is_FloatRegister(), "must be");
0N/Astatic int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
0N/A // Better yet would be some mechanism to handle variable-size matches correctly
0N/A if (!Assembler::is_simm13(offset + STACK_BIAS)) {
0N/A ra_->C->record_method_not_compilable("unable to handle large constant offsets");
0N/A emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
0N/A else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t");
0N/A if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
0N/A else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
0N/Astatic int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
0N/A if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
0N/A else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t");
0N/A st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
0N/Auint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
0N/A outputStream* st ) const {
0N/A // Get registers to move
0N/A OptoReg::Name src_second = ra_->get_reg_second(in(1));
0N/A OptoReg::Name src_first = ra_->get_reg_first(in(1));
0N/A OptoReg::Name dst_second = ra_->get_reg_second(this );
0N/A OptoReg::Name dst_first = ra_->get_reg_first(this );
0N/A enum RC src_second_rc = rc_class(src_second);
0N/A enum RC src_first_rc = rc_class(src_first);
0N/A enum RC dst_second_rc = rc_class(dst_second);
0N/A enum RC dst_first_rc = rc_class(dst_first);
0N/A assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
0N/A // Generate spill code!
0N/A if( src_first == dst_first && src_second == dst_second )
0N/A return size; // Self copy, no move
0N/A // --------------------------------------
0N/A // Check for mem-mem move. Load into unused float registers and fall into
0N/A // the float-store case.
0N/A if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(src_first);
0N/A // Further check for aligned-adjacent pair, so we can use a double load
0N/A if( (src_first&1)==0 && src_first+1 == src_second ) {
0N/A src_second = OptoReg::Name(R_F31_num);
0N/A src_second_rc = rc_float;
0N/A size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
0N/A size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
0N/A src_first = OptoReg::Name(R_F30_num);
0N/A src_first_rc = rc_float;
0N/A if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(src_second);
0N/A size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
0N/A src_second = OptoReg::Name(R_F31_num);
0N/A src_second_rc = rc_float;
0N/A // --------------------------------------
0N/A // Check for float->int copy; requires a trip through memory
2629N/A if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
0N/A int offset = frame::register_save_words*wordSize;
0N/A emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
0N/A impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
0N/A impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
0N/A emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
2629N/A if (size != 0) st->print("\n\t");
0N/A st->print( "SUB R_SP,16,R_SP\n");
0N/A impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
0N/A impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
0N/A st->print("\tADD R_SP,16,R_SP\n");
2629N/A // Check for float->int copy on T4
2629N/A if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
2629N/A // Further check for aligned-adjacent pair, so we can use a double move
2629N/A if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
2629N/A return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
2629N/A size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
2629N/A // Check for int->float copy on T4
2629N/A if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
2629N/A // Further check for aligned-adjacent pair, so we can use a double move
2629N/A if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
2629N/A return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
2629N/A size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
0N/A // --------------------------------------
0N/A // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
0N/A // In such cases, I have to do the big-endian swap. For aligned targets, the
0N/A // hardware does the flop for me. Doubles are always aligned, so no problem
0N/A // there. Misaligned sources only come from native-long-returns (handled
0N/A if( src_first_rc == rc_int && // source is already big-endian
0N/A src_second_rc != rc_bad && // 64-bit move
0N/A ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
0N/A assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
0N/A // Do the big-endian flop.
0N/A OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
0N/A enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
0N/A // --------------------------------------
0N/A // Check for integer reg-reg copy
0N/A if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
0N/A if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil
O0/O1 native long-return case
0N/A // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
0N/A // as stored in memory. On a big-endian machine like SPARC, this means that the _second
0N/A // operand contains the least significant word of the 64-bit value and vice versa.
0N/A OptoReg::Name tmp = OptoReg::Name(R_O7_num);
0N/A assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native
O0/O1 long to an aligned-adjacent 64-bit reg" );
0N/A // Shift O0 left in-place, zero-extend O1, then OR them into the dst
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
0N/A emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
0N/A } else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t");
0N/A st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
0N/A st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
0N/A st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
0N/A else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
0N/A // a SpillCopy must be able to target a return instruction's reg_class
0N/A // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
0N/A // as stored in memory. On a big-endian machine like SPARC, this means that the _second
0N/A // operand contains the least significant word of the 64-bit value and vice versa.
0N/A OptoReg::Name tdest = dst_first;
0N/A if (src_first == dst_first) {
0N/A tdest = OptoReg::Name(R_O7_num);
0N/A assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
0N/A // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
0N/A // ShrR_reg_imm6 src, 0, dst
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
0N/A if (tdest != dst_first) {
0N/A emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
0N/A else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
0N/A st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
0N/A st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
0N/A if (tdest != dst_first) {
0N/A st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
0N/A // Else normal reg-reg copy
0N/A assert( src_second != dst_first, "smashed second before evacuating it" );
0N/A size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
0N/A assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
0N/A // This moves an aligned adjacent pair.
0N/A // See if we are done.
0N/A if( src_first+1 == src_second && dst_first+1 == dst_second )
0N/A // Check for integer store
0N/A if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(dst_first);
0N/A // Further check for aligned-adjacent pair, so we can use a double store
0N/A if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
0N/A return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
0N/A size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
0N/A // Check for integer load
0N/A if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(src_first);
0N/A // Further check for aligned-adjacent pair, so we can use a double load
0N/A if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
0N/A return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
0N/A size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
0N/A // Check for float reg-reg copy
0N/A if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
0N/A // Further check for aligned-adjacent pair, so we can use a double move
0N/A if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
0N/A return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
0N/A size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
0N/A // Check for float store
0N/A if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(dst_first);
0N/A // Further check for aligned-adjacent pair, so we can use a double store
0N/A if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
0N/A return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
0N/A size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
0N/A // Check for float load
0N/A if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
0N/A int offset = ra_->reg2offset(src_first);
0N/A // Further check for aligned-adjacent pair, so we can use a double load
0N/A if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
0N/A return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
0N/A size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
0N/A // --------------------------------------------------------------------
0N/A // Check for hi bits still needing moving. Only happens for misaligned
0N/A // arguments to native calls.
0N/A if( src_second == dst_second )
0N/A return size; // Self copy; no move
0N/A assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
605N/A // pairs, so there's never any need to move the high bits separately.
0N/A // The 32-bit builds have to deal with the 32-bit ABI which can force
0N/A // all sorts of silly alignment problems.
0N/A // Check for integer reg-reg copy. Hi bits are stuck up in the top
0N/A // 32-bits of a 64-bit register, but are needed in low bits of another
0N/A // register (else it's a hi-bits-to-hi-bits copy which should have
0N/A // happened already as part of a 64-bit move)
0N/A if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
0N/A assert( (src_second&1)==1, "its the evil
O0/O1 native return case" );
0N/A assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
0N/A // Shift src_second down to dst_second's low bits.
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
0N/A } else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t");
0N/A st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
0N/A // Check for high word integer store. Must down-shift the hi bits
0N/A // into a temp register, then fall into the case of storing int bits.
0N/A if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
0N/A // Shift src_second down to dst_second's low bits.
0N/A emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
0N/A } else if( !do_size ) {
0N/A if( size != 0 ) st->print("\n\t");
0N/A st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
0N/A src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
0N/A // Check for high word integer load
0N/A if( dst_second_rc == rc_int && src_second_rc == rc_stack )
0N/A return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
0N/A // Check for high word integer store
0N/A if( src_second_rc == rc_int && dst_second_rc == rc_stack )
0N/A return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
0N/A // Check for high word float store
0N/A if( src_second_rc == rc_float && dst_second_rc == rc_stack )
0N/A return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
0N/Avoid MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
0N/A implementation( NULL, ra_, false, st );
0N/Avoid MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/A implementation( &cbuf, ra_, false, NULL );
0N/Auint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
0N/A return implementation( NULL, ra_, true, NULL );
0N/A//=============================================================================
0N/Avoid MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
0N/A st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
0N/Avoid MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A for(int i = 0; i < _count; i += 1) {
0N/Auint MachNopNode::size(PhaseRegAlloc *ra_) const {
0N/A//=============================================================================
0N/Avoid BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
0N/A int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
0N/A int reg = ra_->get_reg_first(this);
0N/A st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
0N/Avoid BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
0N/A int reg = ra_->get_encode(this);
0N/A if (Assembler::is_simm13(offset)) {
0N/A __ add(SP, offset, reg_to_register_object(reg));
0N/A __ add(SP, O7, reg_to_register_object(reg));
0N/Auint BoxLockNode::size(PhaseRegAlloc *ra_) const {
0N/A // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
0N/A assert(ra_ == ra_->C->regalloc(), "sanity");
0N/A return ra_->C->scratch_emit_size(this);
0N/A//=============================================================================
0N/A// emit call stub, compiled java to interpretor
0N/Avoid emit_java_to_interp(CodeBuffer &cbuf ) {
0N/A // Stub is fixed up when the corresponding call is converted from calling
0N/A // compiled code to calling interpreted code.
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(Compile::MAX_stubs_size);
0N/A if (base == NULL) return; // CodeBuffer::expand failed
0N/A // static stub relocation stores the instruction address of the call
0N/A __ relocate(static_stub_Relocation::spec(mark));
0N/A __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
727N/A AddressLiteral addrlit(-1);
727N/A __ JUMP(addrlit, G3, 0);
0N/A __ delayed()->nop();
0N/A // Update current stubs pointer and restore code_end.
0N/A// size of call stub, compiled java to interpretor
0N/Auint size_java_to_interp() {
0N/A // This doesn't need to be accurate but it must be larger or equal to
0N/A // the real size of the stub.
0N/A NativeJump::instruction_size + // sethi; jmp; nop
0N/A (TraceJumps ? 20 * BytesPerInstWord : 0) );
0N/A// relocation entries for call stub, compiled java to interpretor
0N/Auint reloc_java_to_interp() {
0N/A return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
0N/A//=============================================================================
0N/Avoid MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
0N/A st->print_cr("\nUEP:");
113N/A if (UseCompressedOops) {
642N/A assert(Universe::heap() != NULL, "java heap should be initialized");
113N/A st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
113N/A st->print_cr("\tSLL R_G5,3,R_G5");
642N/A if (Universe::narrow_oop_base() != NULL)
642N/A st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
113N/A st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
0N/A st->print_cr("\tCMP R_G5,R_G3" );
0N/A st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
0N/A st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
0N/A st->print_cr("\tCMP R_G5,R_G3" );
0N/A st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
0N/Avoid MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0N/A MacroAssembler _masm(&cbuf);
0N/A Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
0N/A Register temp_reg = G3;
0N/A assert( G5_ic_reg != temp_reg, "conflicting registers" );
605N/A // Load klass from receiver
113N/A __ load_klass(O0, temp_reg);
0N/A // Compare against expected klass
0N/A __ cmp(temp_reg, G5_ic_reg);
0N/A // Branch to miss code, checks xcc or icc depending
0N/A __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
0N/Auint MachUEPNode::size(PhaseRegAlloc *ra_) const {
0N/A return MachNode::size(ra_);
0N/A//=============================================================================
0N/Auint size_exception_handler() {
0N/A return (400); // just a guess
0N/A return ( NativeJump::instruction_size ); // sethi;jmp;nop
0N/Auint size_deopt_handler() {
0N/A return (400); // just a guess
0N/A return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
0N/A// Emit exception handler code.
0N/Aint emit_exception_handler(CodeBuffer& cbuf) {
0N/A Register temp_reg = G3;
1668N/A AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(size_exception_handler());
0N/A if (base == NULL) return 0; // CodeBuffer::expand failed
0N/A int offset = __ offset();
727N/A __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
0N/A __ delayed()->nop();
0N/A assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
0N/Aint emit_deopt_handler(CodeBuffer& cbuf) {
0N/A // Can't use any of the current frame's registers as we may have deopted
0N/A // at a poll and everything (including G3) can be live.
0N/A Register temp_reg = L0;
727N/A AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
0N/A MacroAssembler _masm(&cbuf);
0N/A __ start_a_stub(size_deopt_handler());
0N/A if (base == NULL) return 0; // CodeBuffer::expand failed
0N/A int offset = __ offset();
727N/A __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
0N/A __ delayed()->restore();
0N/A assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
0N/A// Given a register encoding, produce a Integer Register object
0N/Astatic Register reg_to_register_object(int register_encoding) {
0N/A assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
0N/A return as_Register(register_encoding);
0N/A// Given a register encoding, produce a single-precision Float Register object
0N/Astatic FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
0N/A assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
0N/A return as_SingleFloatRegister(register_encoding);
0N/A// Given a register encoding, produce a double-precision Float Register object
0N/Astatic FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
0N/A assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
0N/A assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
0N/A return as_DoubleFloatRegister(register_encoding);
775N/Aconst bool Matcher::match_rule_supported(int opcode) {
775N/A if (!has_match_rule(opcode))
775N/A case Op_CountLeadingZerosI:
775N/A case Op_CountLeadingZerosL:
775N/A case Op_CountTrailingZerosI:
775N/A case Op_CountTrailingZerosL:
775N/A if (!UsePopCountInstruction)
775N/A return true; // Per default match rules are supported.
0N/Aint Matcher::regnum_to_fpu_offset(int regnum) {
0N/A return regnum - 32; // The FP registers are in the second chunk
0N/Aaddress last_rethrow = NULL; // debugging aid for Rethrow encoding
0N/A// Vector width in bytes
0N/Aconst uint Matcher::vector_width_in_bytes(void) {
0N/Aconst uint Matcher::vector_ideal_reg(void) {
0N/A// USII supports fxtof through the whole range of number, USIII doesn't
0N/Aconst bool Matcher::convL2FSupported(void) {
0N/A return VM_Version::has_fast_fxtof();
0N/A// Is this branch offset short enough that a short branch can be used?
0N/A// NOTE: If the platform does not provide any short branch variants, then
0N/A// this method should return false for offset 0.
2676N/Abool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2676N/A // The passed offset is relative to address of the branch.
2676N/A // Don't need to adjust the offset.
2957N/A return UseCBCond && Assembler::is_simm12(offset);
0N/Aconst bool Matcher::isSimpleConstant64(jlong value) {
0N/A // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
0N/A // Depends on optimizations in MacroAssembler::setx.
0N/A int hi = (int)(value >> 32);
0N/A int lo = (int)(value & ~0);
0N/A return (hi == 0) || (hi == -1) || (lo == 0);
0N/A// No scaling for the parameter the ClearArray node.
0N/Aconst bool Matcher::init_array_count_is_in_bytes = true;
0N/A// Threshold size for cleararray.
0N/Aconst int Matcher::init_array_short_size = 8 * BytesPerLong;
2885N/A// No additional cost for CMOVL.
2885N/Aconst int Matcher::long_cmove_cost() { return 0; }
2885N/Aconst int Matcher::float_cmove_cost() {
2885N/A return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
0N/A// Should the Matcher clone shifts on addressing modes, expecting them to
0N/A// be subsumed into complex addressing expressions or compute them into
0N/A// registers? True for Intel but false for most RISCs
0N/Aconst bool Matcher::clone_shift_expressions = false;
2248N/A// Do we need to mask the count passed to shift instructions or does
2248N/A// the cpu only look at the lower 5/6 bits anyway?
2248N/Aconst bool Matcher::need_masked_shift_count = false;
1495N/Abool Matcher::narrow_oop_use_complex_address() {
1495N/A NOT_LP64(ShouldNotCallThis());
1495N/A assert(UseCompressedOops, "only for compressed oops code");
0N/A// Is it better to copy float constants, or load them directly from memory?
0N/A// Intel can load a float constant from a direct address, requiring no
0N/A// extra registers. Most RISCs will have to materialize an address into a
0N/A// register first, so they would do better to copy the constant from stack.
0N/Aconst bool Matcher::rematerialize_float_constants = false;
0N/A// If CPU can load and store mis-aligned doubles directly then no fixup is
0N/A// needed. Else we split the double into 2 integer pieces and move it
0N/A// piece-by-piece. Only happens when passing doubles into C code as the
0N/A// Java calling convention forces doubles to be aligned.
0N/Aconst bool Matcher::misaligned_doubles_ok = true;
0N/Aconst bool Matcher::misaligned_doubles_ok = false;
0N/Avoid Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
0N/A// Advertise here if the CPU requires explicit rounding operations
0N/A// to implement the UseStrictFP mode.
0N/Aconst bool Matcher::strict_fp_requires_explicit_rounding = false;
1274N/A// Are floats conerted to double when stored to stack during deoptimization?
1274N/A// Sparc does not handle callee-save floats.
1274N/Abool Matcher::float_in_double() { return false; }
0N/A// Do ints take an entire long register or just half?
0N/A// Note that we if-def off of _LP64.
0N/A// The relevant question is how the int is callee-saved. In _LP64
0N/A// the whole long is written but de-opt'ing will have to extract
0N/A// the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
0N/Aconst bool Matcher::int_in_long = true;
0N/Aconst bool Matcher::int_in_long = false;
0N/A// Return whether or not this register is ever used as an argument. This
0N/A// function is used on startup to build the trampoline stubs in generateOptoStub.
0N/A// Registers not mentioned will be killed by the VM call in the trampoline, and
0N/A// arguments in those registers not be available to the callee.
0N/Abool Matcher::can_be_java_arg( int reg ) {
0N/A // Standard sparc 6 args in registers
0N/A if( reg == R_I0_num ||
0N/A reg == R_I5_num ) return true;
0N/A // 64-bit builds can pass 64-bit pointers and longs in
0N/A // the high I registers
0N/A if( reg == R_I0H_num ||
0N/A reg == R_I5H_num ) return true;
113N/A if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
0N/A // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
0N/A // Longs cannot be passed in O regs, because O regs become I regs
0N/A // after a 'save' and I regs get their high bits chopped off on
0N/A if( reg == R_G1H_num || reg == R_G1_num ) return true;
0N/A if( reg == R_G4H_num || reg == R_G4_num ) return true;
0N/A // A few float args in registers
0N/A if( reg >= R_F0_num && reg <= R_F7_num ) return true;
0N/Abool Matcher::is_spillable_arg( int reg ) {
0N/A return can_be_java_arg(reg);
1834N/Abool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1834N/A // Use hardware SDIVX instruction when it is
1834N/A // faster than a code which use multiply.
1834N/A return VM_Version::has_fast_idiv();
0N/A// Register for DIVI projection of divmodI
0N/ARegMask Matcher::divI_proj_mask() {
0N/A ShouldNotReachHere();
0N/A// Register for MODI projection of divmodI
0N/ARegMask Matcher::modI_proj_mask() {
0N/A ShouldNotReachHere();
0N/A// Register for DIVL projection of divmodL
0N/ARegMask Matcher::divL_proj_mask() {
0N/A ShouldNotReachHere();
0N/A// Register for MODL projection of divmodL
0N/ARegMask Matcher::modL_proj_mask() {
0N/A ShouldNotReachHere();
1137N/Aconst RegMask Matcher::method_handle_invoke_SP_save_mask() {
0N/A// The intptr_t operand types, defined by textual substitution.
824N/A#define immX13m7 immL13m7
824N/A#define immX13m7 immI13m7
0N/A//----------ENCODING BLOCK-----------------------------------------------------
0N/A// This block specifies the encoding classes used by the compiler to output
0N/A// byte streams. Encoding classes are parameterized macros used by
0N/A// Machine Instruction Nodes in order to generate the bit encoding of the
0N/A// instruction. Operands specify their base encoding interface with the
0N/A// interface keyword. There are currently supported four interfaces,
0N/A// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
0N/A// operand to generate a function which returns its register number when
0N/A// queried. CONST_INTER causes an operand to generate a function which
0N/A// returns the value of the constant when queried. MEMORY_INTER causes an
0N/A// operand to generate four functions which return the Base Register, the
0N/A// Index Register, the Scale Value, and the Offset Value of the operand when
0N/A// queried. COND_INTER causes an operand to generate six functions which
0N/A// return the encoding code (ie - encoding bits for the instruction)
0N/A// associated with each basic boolean condition for a conditional instruction.
0N/A// Instructions specify two basic values for encoding. Again, a function
0N/A// is available to check if the constant displacement is an oop. They use the
0N/A// ins_encode keyword to specify their encoding classes (which must be
0N/A// a sequence of enc_class names, and their parameters, specified in
0N/A// the encoding block), and they use the
0N/A// opcode keyword to specify, in order, their primary, secondary, and
0N/A// tertiary opcode. Only the opcode sections which a particular instruction
0N/A// needs for encoding need to be specified.
0N/A enc_class enc_untested %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ untested("encoding");
0N/A enc_class form3_mem_reg( memory mem, iRegI dst ) %{
0N/A emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
0N/A $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
415N/A enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1,
415N/A $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
0N/A enc_class form3_mem_prefetch_read( memory mem ) %{
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1,
0N/A $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
0N/A enc_class form3_mem_prefetch_write( memory mem ) %{
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1,
0N/A $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
0N/A enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2957N/A assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2957N/A assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
0N/A guarantee($mem$$index == R_G0_enc, "double index?");
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
0N/A emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
0N/A emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
0N/A enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2957N/A assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2957N/A assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
0N/A guarantee($mem$$index == R_G0_enc, "double index?");
0N/A // Load long with 2 instructions
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
0N/A //%%% form3_mem_plus_4_reg is a hack--get rid of it
0N/A enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
0N/A guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
415N/A emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
0N/A enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
0N/A // Encode a reg-reg copy. If it is useless, then empty encoding.
0N/A if( $rs2$$reg != $rd$$reg )
0N/A emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
0N/A // Target lo half of long
0N/A enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
0N/A // Encode a reg-reg copy. If it is useless, then empty encoding.
0N/A if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
0N/A emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
0N/A // Source lo half of long
0N/A enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
0N/A // Encode a reg-reg copy. If it is useless, then empty encoding.
0N/A if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
0N/A emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
0N/A // Target hi half of long
0N/A enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
0N/A emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
0N/A // Source lo half of long, and leave it sign extended.
0N/A enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
0N/A // Sign extend low half
0N/A emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
0N/A // Source hi half of long, and leave it sign extended.
0N/A enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
0N/A // Shift high half to low half
0N/A emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
0N/A // Source hi half of long
0N/A enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
0N/A // Encode a reg-reg copy. If it is useless, then empty encoding.
0N/A if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
0N/A emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
0N/A enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
0N/A emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
0N/A enc_class enc_to_bool( iRegI src, iRegI dst ) %{
0N/A emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
0N/A emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
0N/A enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
0N/A emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
0N/A // clear if nothing else is happening
0N/A emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
0N/A emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
0N/A // mov dst,-1 in delay slot
0N/A emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
0N/A enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
0N/A emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
0N/A enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
0N/A emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
0N/A enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
0N/A emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
0N/A enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
0N/A emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
0N/A enc_class move_return_pc_to_o1() %{
0N/A emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
0N/A /* %%% merge with enc_to_bool */
0N/A enc_class enc_convP2B( iRegI dst, iRegP src ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register src_reg = reg_to_register_object($src$$reg);
0N/A Register dst_reg = reg_to_register_object($dst$$reg);
0N/A __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
0N/A enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
0N/A // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
0N/A MacroAssembler _masm(&cbuf);
0N/A Register p_reg = reg_to_register_object($p$$reg);
0N/A Register q_reg = reg_to_register_object($q$$reg);
0N/A Register y_reg = reg_to_register_object($y$$reg);
0N/A Register tmp_reg = reg_to_register_object($tmp$$reg);
0N/A __ subcc( p_reg, q_reg, p_reg );
0N/A __ add ( p_reg, y_reg, tmp_reg );
0N/A __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
0N/A enc_class form_d2i_helper(regD src, regF dst) %{
0N/A // fcmp %fcc0,$src,$src
0N/A emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
0N/A // branch %fcc0 not-nan, predict taken
0N/A emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
0N/A // fitos $dst,$dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
0N/A // clear $dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
0N/A enc_class form_d2l_helper(regD src, regD dst) %{
0N/A // fcmp %fcc0,$src,$src check for NAN
0N/A emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
0N/A // branch %fcc0 not-nan, predict taken
0N/A emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
0N/A // fdtox $src,$dst convert in delay slot
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
0N/A // fxtod $dst,$dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
0N/A // clear $dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
0N/A enc_class form_f2i_helper(regF src, regF dst) %{
0N/A // fcmps %fcc0,$src,$src
0N/A emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
0N/A // branch %fcc0 not-nan, predict taken
0N/A emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
0N/A // fitos $dst,$dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
0N/A // clear $dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
0N/A enc_class form_f2l_helper(regF src, regD dst) %{
0N/A // fcmps %fcc0,$src,$src
0N/A emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
0N/A // branch %fcc0 not-nan, predict taken
0N/A emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
0N/A // fxtod $dst,$dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
0N/A // clear $dst (if nan)
0N/A emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
0N/A enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
0N/A enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
0N/A enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
0N/A enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
0N/A enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
0N/A enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
0N/A enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
0N/A enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
0N/A emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
0N/A enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
0N/A emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
0N/A enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
0N/A emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
0N/A enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
0N/A emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
0N/A enc_class form3_convI2F(regF rs2, regF rd) %{
0N/A emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
0N/A // Encloding class for traceable jumps
0N/A enc_class form_jmpl(g3RegP dest) %{
0N/A emit_jmpl(cbuf, $dest$$reg);
0N/A enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
0N/A emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
0N/A enc_class form2_nop() %{
0N/A enc_class form2_illtrap() %{
0N/A // Compare longs and convert into -1, 0, 1.
0N/A enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
0N/A emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
0N/A emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
0N/A // mov dst,-1 in delay slot
0N/A emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
0N/A emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
0N/A // mov dst,1 in delay slot
0N/A emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
0N/A emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
0N/A enc_class enc_PartialSubtypeCheck() %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
2664N/A enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Assembler::Predict predict_taken =
2664N/A __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
0N/A __ delayed()->nop();
2664N/A enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Assembler::Predict predict_taken =
2664N/A __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
0N/A __ delayed()->nop();
0N/A enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (1 << 18) | // cc2 bit for 'icc'
0N/A ($cmp$$cmpcode << 14) |
0N/A (0 << 13) | // select register move
0N/A ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
0N/A enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
0N/A int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (1 << 18) | // cc2 bit for 'icc'
0N/A ($cmp$$cmpcode << 14) |
0N/A (1 << 13) | // select immediate move
0N/A ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
0N/A enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (0 << 18) | // cc2 bit for 'fccX'
0N/A ($cmp$$cmpcode << 14) |
0N/A (0 << 13) | // select register move
0N/A ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
0N/A enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
0N/A int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (0 << 18) | // cc2 bit for 'fccX'
0N/A ($cmp$$cmpcode << 14) |
0N/A (1 << 13) | // select immediate move
0N/A ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
0N/A enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::fpop2_op3 << 19) |
0N/A ($cmp$$cmpcode << 14) |
0N/A (1 << 13) | // select register move
0N/A ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
0N/A ($primary << 5) | // select single, double or quad
0N/A enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::fpop2_op3 << 19) |
0N/A ($cmp$$cmpcode << 14) |
0N/A ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
0N/A ($primary << 5) | // select single, double or quad
0N/A // Used by the
MIN/MAX encodings. Same as a CMOV, but
0N/A // the condition comes from opcode-field instead of an argument.
0N/A enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (1 << 18) | // cc2 bit for 'icc'
0N/A (0 << 13) | // select register move
0N/A (0 << 11) | // cc1, cc0 bits for 'icc'
0N/A enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
0N/A int op = (Assembler::arith_op << 30) |
0N/A (Assembler::movcc_op3 << 19) |
0N/A (6 << 16) | // cc2 bit for 'xcc'
0N/A (0 << 13) | // select register move
0N/A (0 << 11) | // cc1, cc0 bits for 'icc'
0N/A enc_class Set13( immI13 src, iRegI rd ) %{
0N/A emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
0N/A enc_class SetHi22( immI src, iRegI rd ) %{
0N/A emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
0N/A enc_class Set32( immI src, iRegI rd ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ set($src$$constant, reg_to_register_object($rd$$reg));
0N/A enc_class call_epilog %{
0N/A if( VerifyStackAtCalls ) {
0N/A MacroAssembler _masm(&cbuf);
0N/A int framesize = ra_->C->frame_slots() << LogBytesPerInt;
0N/A Register temp_reg = G3;
0N/A __ add(SP, framesize, temp_reg);
0N/A __ cmp(temp_reg, FP);
0N/A __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
0N/A // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
0N/A // to G1 so the register allocator will not have to deal with the misaligned register
0N/A enc_class adjust_long_from_native_call %{
0N/A if (returns_long()) {
0N/A emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
0N/A emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
0N/A emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
0N/A enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
0N/A // CALL directly to the runtime
0N/A // The user of this is responsible for ensuring that R_L7 is empty (killed).
0N/A emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
1487N/A MacroAssembler _masm(&cbuf);
1487N/A MacroAssembler _masm(&cbuf);
0N/A enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
0N/A // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
0N/A // who we intended to call.
0N/A emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
0N/A } else if (_optimized_virtual) {
0N/A emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
0N/A emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
0N/A if( _method ) { // Emit stub for static call
0N/A emit_java_to_interp(cbuf);
0N/A enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
0N/A MacroAssembler _masm(&cbuf);
0N/A int vtable_index = this->_vtable_index;
0N/A // MachCallDynamicJavaNode::ret_addr_offset uses this same test
0N/A if (vtable_index < 0) {
0N/A // must be invalid_vtable_index, not nonvirtual_vtable_index
0N/A assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
0N/A Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
0N/A assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
0N/A assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
0N/A // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
0N/A // emit_call_dynamic_prologue( cbuf );
0N/A __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
0N/A address virtual_call_oop_addr = __ inst_mark();
0N/A // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
0N/A // who we intended to call.
0N/A __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
0N/A emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
0N/A assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
0N/A // Just go thru the vtable
0N/A // get receiver klass (receiver already checked for non-null)
0N/A // If we end up going thru a c2i adapter interpreter expects method in G5
0N/A int off = __ offset();
113N/A __ load_klass(O0, G3_scratch);
113N/A if (UseCompressedOops) {
642N/A assert(Universe::heap() != NULL, "java heap should be initialized");
642N/A if (Universe::narrow_oop_base() == NULL)
642N/A klass_load_size = 2*BytesPerInstWord;
642N/A klass_load_size = 3*BytesPerInstWord;
113N/A klass_load_size = 1*BytesPerInstWord;
0N/A int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
0N/A int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2957N/A if (Assembler::is_simm13(v_off)) {
0N/A __ ld_ptr(G3, v_off, G5_method);
0N/A // Generate 2 instructions
0N/A __ Assembler::sethi(v_off & ~0x3ff, G5_method);
0N/A __ or3(G5_method, v_off & 0x3ff, G5_method);
0N/A // ld_ptr, set_hi, set
113N/A assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
113N/A "Unexpected instruction size(s)");
0N/A __ ld_ptr(G3, G5_method, G5_method);
0N/A // NOTE: for vtable dispatches, the vtable entry will never be null.
0N/A // However it may very well end up in handle_wrong_method if the
0N/A // method is abstract for the particular class.
0N/A __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
0N/A // jump to target (either compiled code or c2iadapter)
0N/A __ jmpl(G3_scratch, G0, O7);
0N/A __ delayed()->nop();
0N/A enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
0N/A MacroAssembler _masm(&cbuf);
0N/A Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
0N/A Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
0N/A // we might be calling a C2I adapter which needs it.
0N/A assert(temp_reg != G5_ic_reg, "conflicting registers");
0N/A __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
0N/A // CALL to compiled java, indirect the contents of G3
0N/A __ callr(temp_reg, G0);
0N/A __ delayed()->nop();
0N/Aenc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rdividend = reg_to_register_object($src1$$reg);
0N/A Register Rdivisor = reg_to_register_object($src2$$reg);
0N/A Register Rresult = reg_to_register_object($dst$$reg);
0N/A __ sra(Rdivisor, 0, Rdivisor);
0N/A __ sra(Rdividend, 0, Rdividend);
0N/A __ sdivx(Rdividend, Rdivisor, Rresult);
0N/Aenc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rdividend = reg_to_register_object($src1$$reg);
0N/A int divisor = $imm$$constant;
0N/A Register Rresult = reg_to_register_object($dst$$reg);
0N/A __ sra(Rdividend, 0, Rdividend);
0N/A __ sdivx(Rdividend, divisor, Rresult);
0N/Aenc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rsrc1 = reg_to_register_object($src1$$reg);
0N/A Register Rsrc2 = reg_to_register_object($src2$$reg);
0N/A Register Rdst = reg_to_register_object($dst$$reg);
0N/A __ sra( Rsrc1, 0, Rsrc1 );
0N/A __ sra( Rsrc2, 0, Rsrc2 );
0N/A __ mulx( Rsrc1, Rsrc2, Rdst );
0N/A __ srlx( Rdst, 32, Rdst );
0N/Aenc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rdividend = reg_to_register_object($src1$$reg);
0N/A Register Rdivisor = reg_to_register_object($src2$$reg);
0N/A Register Rresult = reg_to_register_object($dst$$reg);
0N/A Register Rscratch = reg_to_register_object($scratch$$reg);
0N/A assert(Rdividend != Rscratch, "");
0N/A assert(Rdivisor != Rscratch, "");
0N/A __ sra(Rdividend, 0, Rdividend);
0N/A __ sra(Rdivisor, 0, Rdivisor);
0N/A __ sdivx(Rdividend, Rdivisor, Rscratch);
0N/A __ mulx(Rscratch, Rdivisor, Rscratch);
0N/A __ sub(Rdividend, Rscratch, Rresult);
0N/Aenc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rdividend = reg_to_register_object($src1$$reg);
0N/A int divisor = $imm$$constant;
0N/A Register Rresult = reg_to_register_object($dst$$reg);
0N/A Register Rscratch = reg_to_register_object($scratch$$reg);
0N/A assert(Rdividend != Rscratch, "");
0N/A __ sra(Rdividend, 0, Rdividend);
0N/A __ sdivx(Rdividend, divisor, Rscratch);
0N/A __ mulx(Rscratch, divisor, Rscratch);
0N/A __ sub(Rdividend, Rscratch, Rresult);
0N/Aenc_class fabss (sflt_reg dst, sflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
0N/A __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
0N/Aenc_class fabsd (dflt_reg dst, dflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
0N/A __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
0N/Aenc_class fnegd (dflt_reg dst, dflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
0N/A __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
0N/Aenc_class fsqrts (sflt_reg dst, sflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
0N/A __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
0N/Aenc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
0N/A __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
0N/Aenc_class fmovs (dflt_reg dst, dflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
0N/A __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
0N/Aenc_class fmovd (dflt_reg dst, dflt_reg src) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
0N/A FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
0N/A __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
0N/Aenc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Roop = reg_to_register_object($oop$$reg);
0N/A Register Rbox = reg_to_register_object($box$$reg);
0N/A Register Rscratch = reg_to_register_object($scratch$$reg);
0N/A Register Rmark = reg_to_register_object($scratch2$$reg);
0N/A assert(Roop != Rscratch, "");
0N/A assert(Roop != Rmark, "");
0N/A assert(Rbox != Rscratch, "");
0N/A assert(Rbox != Rmark, "");
420N/A __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
0N/Aenc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Roop = reg_to_register_object($oop$$reg);
0N/A Register Rbox = reg_to_register_object($box$$reg);
0N/A Register Rscratch = reg_to_register_object($scratch$$reg);
0N/A Register Rmark = reg_to_register_object($scratch2$$reg);
0N/A assert(Roop != Rscratch, "");
0N/A assert(Roop != Rmark, "");
0N/A assert(Rbox != Rscratch, "");
0N/A assert(Rbox != Rmark, "");
420N/A __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
0N/A enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rmem = reg_to_register_object($mem$$reg);
0N/A Register Rold = reg_to_register_object($old$$reg);
0N/A Register Rnew = reg_to_register_object($new$$reg);
0N/A // casx_under_lock picks 1 of 3 encodings:
0N/A // For 32-bit pointers you get a 32-bit CAS
0N/A // For 64-bit pointers you get a 64-bit CASX
420N/A __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
0N/A __ cmp( Rold, Rnew );
0N/A enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
0N/A Register Rmem = reg_to_register_object($mem$$reg);
0N/A Register Rold = reg_to_register_object($old$$reg);
0N/A Register Rnew = reg_to_register_object($new$$reg);
0N/A MacroAssembler _masm(&cbuf);
0N/A __ casx(Rmem, Rold, O7);
0N/A // raw int cas, used for compareAndSwap
0N/A enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
0N/A Register Rmem = reg_to_register_object($mem$$reg);
0N/A Register Rold = reg_to_register_object($old$$reg);
0N/A Register Rnew = reg_to_register_object($new$$reg);
0N/A MacroAssembler _masm(&cbuf);
0N/A __ cas(Rmem, Rold, O7);
0N/A enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
0N/A Register Rres = reg_to_register_object($res$$reg);
0N/A MacroAssembler _masm(&cbuf);
0N/A __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
0N/A enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
0N/A Register Rres = reg_to_register_object($res$$reg);
0N/A MacroAssembler _masm(&cbuf);
0N/A __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
0N/A enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register Rdst = reg_to_register_object($dst$$reg);
0N/A FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
0N/A : reg_to_DoubleFloatRegister_object($src1$$reg);
0N/A FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
0N/A : reg_to_DoubleFloatRegister_object($src2$$reg);
0N/A // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
0N/A __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
986N/A enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register str1_reg = reg_to_register_object($str1$$reg);
0N/A Register str2_reg = reg_to_register_object($str2$$reg);
986N/A Register cnt1_reg = reg_to_register_object($cnt1$$reg);
986N/A Register cnt2_reg = reg_to_register_object($cnt2$$reg);
0N/A Register result_reg = reg_to_register_object($result$$reg);
986N/A assert(result_reg != str1_reg &&
986N/A result_reg != str2_reg &&
986N/A result_reg != cnt1_reg &&
986N/A result_reg != cnt2_reg ,
986N/A "need different registers");
0N/A // Compute the minimum of the string lengths(str1_reg) and the
0N/A // difference of the string lengths (stack)
0N/A // See if the lengths are different, and calculate min in str1_reg.
0N/A // Stash diff in O7 in case we need it for a tie-breaker.
986N/A __ subcc(cnt1_reg, cnt2_reg, O7);
986N/A __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
0N/A __ br(Assembler::greater, true, Assembler::pt, Lskip);
986N/A // cnt2 is shorter, so use its count:
986N/A __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
986N/A // reallocate cnt1_reg, cnt2_reg, result_reg
0N/A // Note: limit_reg holds the string length pre-scaled by 2
986N/A Register limit_reg = cnt1_reg;
986N/A Register chr2_reg = cnt2_reg;
0N/A Register chr1_reg = result_reg;
986N/A // str{12} are the base pointers
0N/A // Is the minimum length zero?
0N/A __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
0N/A __ br(Assembler::equal, true, Assembler::pn, Ldone);
0N/A __ delayed()->mov(O7, result_reg); // result is difference in lengths
0N/A // Load first characters
986N/A __ lduh(str1_reg, 0, chr1_reg);
986N/A __ lduh(str2_reg, 0, chr2_reg);
0N/A // Compare first characters
0N/A __ subcc(chr1_reg, chr2_reg, chr1_reg);
0N/A __ br(Assembler::notZero, false, Assembler::pt, Ldone);
0N/A assert(chr1_reg == result_reg, "result must be pre-placed");
0N/A __ delayed()->nop();
0N/A // Check after comparing first character to see if strings are equivalent
0N/A // Check if the strings start at same location
986N/A __ cmp(str1_reg, str2_reg);
0N/A __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
0N/A __ delayed()->nop();
0N/A // Check if the length difference is zero (in O7)
0N/A __ br(Assembler::equal, true, Assembler::pn, Ldone);
0N/A __ delayed()->mov(G0, result_reg); // result is zero
0N/A // Strings might not be equal
0N/A __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
0N/A __ br(Assembler::equal, true, Assembler::pn, Ldone);
0N/A __ delayed()->mov(O7, result_reg); // result is difference in lengths
986N/A // Shift str1_reg and str2_reg to the end of the arrays, negate limit
986N/A __ add(str1_reg, limit_reg, str1_reg);
986N/A __ add(str2_reg, limit_reg, str2_reg);
0N/A __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
0N/A // Compare the rest of the characters
986N/A __ lduh(str1_reg, limit_reg, chr1_reg);
986N/A // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
986N/A __ lduh(str2_reg, limit_reg, chr2_reg);
0N/A __ subcc(chr1_reg, chr2_reg, chr1_reg);
0N/A __ br(Assembler::notZero, false, Assembler::pt, Ldone);
0N/A assert(chr1_reg == result_reg, "result must be pre-placed");
0N/A __ delayed()->inccc(limit_reg, sizeof(jchar));
0N/A // annul LDUH if branch is not taken to prevent access past end of string
0N/A __ br(Assembler::notZero, true, Assembler::pt, Lloop);
986N/A __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
0N/A // If strings are equal up to min length, return the length difference.
0N/A __ mov(O7, result_reg);
0N/A // Otherwise, return the difference between the first mismatched chars.
986N/Aenc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
986N/A Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
681N/A MacroAssembler _masm(&cbuf);
681N/A Register str1_reg = reg_to_register_object($str1$$reg);
681N/A Register str2_reg = reg_to_register_object($str2$$reg);
986N/A Register cnt_reg = reg_to_register_object($cnt$$reg);
986N/A Register tmp1_reg = O7;
681N/A Register result_reg = reg_to_register_object($result$$reg);
986N/A assert(result_reg != str1_reg &&
986N/A result_reg != str2_reg &&
986N/A result_reg != cnt_reg &&
986N/A result_reg != tmp1_reg ,
986N/A "need different registers");
986N/A __ cmp(str1_reg, str2_reg); //same char[] ?
681N/A __ brx(Assembler::equal, true, Assembler::pn, Ldone);
681N/A __ delayed()->add(G0, 1, result_reg);
2664N/A __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
986N/A __ delayed()->add(G0, 1, result_reg); // count == 0
986N/A Register limit_reg = cnt_reg;
681N/A Register chr1_reg = result_reg;
986N/A Register chr2_reg = tmp1_reg;
681N/A //check for alignment and position the pointers to the ends
986N/A __ or3(str1_reg, str2_reg, chr1_reg);
986N/A __ andcc(chr1_reg, 0x3, chr1_reg);
986N/A // notZero means at least one not 4-byte aligned.
986N/A // We could optimize the case when both arrays are not aligned
986N/A // but it is not frequent case and it requires additional checks.
986N/A __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
986N/A __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
986N/A // Compare char[] arrays aligned to 4 bytes.
986N/A __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
986N/A chr1_reg, chr2_reg, Ldone);
681N/A __ delayed()->add(G0, 1, result_reg);
986N/A // char by char compare
986N/A __ add(str1_reg, limit_reg, str1_reg);
986N/A __ add(str2_reg, limit_reg, str2_reg);
681N/A __ neg(limit_reg); //negate count
986N/A __ lduh(str1_reg, limit_reg, chr1_reg);
986N/A __ lduh(str2_reg, limit_reg, chr2_reg);
681N/A __ cmp(chr1_reg, chr2_reg);
681N/A __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
681N/A __ delayed()->mov(G0, result_reg); //not equal
681N/A __ inccc(limit_reg, sizeof(jchar));
681N/A // annul LDUH if branch is not taken to prevent access past end of string
986N/A __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
986N/A __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
681N/A __ add(G0, 1, result_reg); //equal
986N/Aenc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
681N/A Label Lvector, Ldone, Lloop;
681N/A MacroAssembler _masm(&cbuf);
681N/A Register ary1_reg = reg_to_register_object($ary1$$reg);
681N/A Register ary2_reg = reg_to_register_object($ary2$$reg);
681N/A Register tmp1_reg = reg_to_register_object($tmp1$$reg);
986N/A Register tmp2_reg = O7;
681N/A Register result_reg = reg_to_register_object($result$$reg);
681N/A int length_offset = arrayOopDesc::length_offset_in_bytes();
681N/A int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
681N/A // return true if the same array
681N/A __ cmp(ary1_reg, ary2_reg);
1016N/A __ brx(Assembler::equal, true, Assembler::pn, Ldone);
681N/A __ delayed()->add(G0, 1, result_reg); // equal
681N/A __ br_null(ary1_reg, true, Assembler::pn, Ldone);
681N/A __ delayed()->mov(G0, result_reg); // not equal
681N/A __ br_null(ary2_reg, true, Assembler::pn, Ldone);
681N/A __ delayed()->mov(G0, result_reg); // not equal
681N/A //load the lengths of arrays
727N/A __ ld(Address(ary1_reg, length_offset), tmp1_reg);
727N/A __ ld(Address(ary2_reg, length_offset), tmp2_reg);
681N/A // return false if the two arrays are not equal length
681N/A __ cmp(tmp1_reg, tmp2_reg);
681N/A __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
681N/A __ delayed()->mov(G0, result_reg); // not equal
2664N/A __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
681N/A __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
681N/A // load array addresses
681N/A __ add(ary1_reg, base_offset, ary1_reg);
681N/A __ add(ary2_reg, base_offset, ary2_reg);
986N/A Register chr1_reg = result_reg; // for characters in ary1
986N/A Register chr2_reg = tmp2_reg; // for characters in ary2
681N/A Register limit_reg = tmp1_reg; // length
681N/A __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
986N/A // Compare char[] arrays aligned to 4 bytes.
986N/A __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
986N/A chr1_reg, chr2_reg, Ldone);
681N/A __ add(G0, 1, result_reg); // equals
0N/A enc_class enc_rethrow() %{
0N/A Register temp_reg = G3;
727N/A AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
0N/A assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
0N/A MacroAssembler _masm(&cbuf);
727N/A AddressLiteral last_rethrow_addrlit(&last_rethrow);
727N/A __ sethi(last_rethrow_addrlit, L1);
0N/A __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
727N/A __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
0N/A __ delayed()->nop();
0N/A enc_class emit_mem_nop() %{
0N/A // Generates the instruction LDUXA [o6,g0],#0x82,g0
0N/A enc_class emit_fadd_nop() %{
0N/A // Generates the instruction FMOVS f31,f31
0N/A enc_class emit_br_nop() %{
0N/A // Generates the instruction BPN,PN .
0N/A enc_class enc_membar_acquire %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
0N/A enc_class enc_membar_release %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
0N/A enc_class enc_membar_volatile %{
0N/A MacroAssembler _masm(&cbuf);
0N/A __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
0N/A enc_class enc_repl8b( iRegI src, iRegL dst ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register src_reg = reg_to_register_object($src$$reg);
0N/A Register dst_reg = reg_to_register_object($dst$$reg);
0N/A __ sllx(src_reg, 56, dst_reg);
0N/A __ srlx(dst_reg, 8, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A __ srlx(dst_reg, 16, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A __ srlx(dst_reg, 32, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A enc_class enc_repl4b( iRegI src, iRegL dst ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register src_reg = reg_to_register_object($src$$reg);
0N/A Register dst_reg = reg_to_register_object($dst$$reg);
0N/A __ sll(src_reg, 24, dst_reg);
0N/A __ srl(dst_reg, 8, O7);
0N/A __ or3(dst_reg, O7, dst_reg);
0N/A __ srl(dst_reg, 16, O7);
0N/A __ or3(dst_reg, O7, dst_reg);
0N/A enc_class enc_repl4s( iRegI src, iRegL dst ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register src_reg = reg_to_register_object($src$$reg);
0N/A Register dst_reg = reg_to_register_object($dst$$reg);
0N/A __ sllx(src_reg, 48, dst_reg);
0N/A __ srlx(dst_reg, 16, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A __ srlx(dst_reg, 32, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A enc_class enc_repl2i( iRegI src, iRegL dst ) %{
0N/A MacroAssembler _masm(&cbuf);
0N/A Register src_reg = reg_to_register_object($src$$reg);
0N/A Register dst_reg = reg_to_register_object($dst$$reg);
0N/A __ sllx(src_reg, 32, dst_reg);
0N/A __ srlx(dst_reg, 32, O7);
0N/A __ or3 (dst_reg, O7, dst_reg);
0N/A//----------FRAME--------------------------------------------------------------
0N/A// Definition of frame structure and management information.
0N/A// S T A C K L A Y O U T Allocators stack-slot number
0N/A// | (to get allocators register number
0N/A// G Owned by | | v add VMRegImpl::stack0)
0N/A// o | +--------+ pad to even-align allocators stack-slot
0N/A// w V | pad0 | numbers; owned by CALLER
0N/A// t -----------+--------+----> Matcher::_in_arg_limit, unaligned
0N/A// | | args | 4 Holes in incoming args owned by SELF
0N/A// V | | old out| Empty on Intel, window on Sparc
0N/A// | old |preserve| Must be even aligned.
0N/A// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
0N/A// | | in | 3 area for Intel ret address
0N/A// Owned by |preserve| Empty on Sparc.
0N/A// | | pad2 | 2 pad to align old SP
0N/A// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
0N/A// | | pad1 | 11 pad to align new SP
0N/A// | | spills | 9 spills
0N/A// V | | 8 (pad0 slot for callee)
0N/A// -----------+--------+----> Matcher::_out_arg_limit, unaligned
0N/A// | | args | 6 Holes in outgoing args owned by CALLEE
0N/A// Owned by +--------+
0N/A// CALLEE | new out| 6 Empty on Intel, window on Sparc
0N/A// | new |preserve| Must be even-aligned.
0N/A// | SP-+--------+----> Matcher::_new_SP, even aligned
0N/A// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
0N/A// known from SELF's arguments and the Java calling convention.
0N/A// Region 6-7 is determined per call site.
0N/A// Note 2: If the calling convention leaves holes in the incoming argument
0N/A// area, those holes are owned by SELF. Holes in the outgoing area
0N/A// are owned by the CALLEE. Holes should not be nessecary in the
0N/A// incoming area, as the Java calling convention is completely under
0N/A// the control of the AD file. Doubles can be sorted and packed to
0N/A// avoid holes. Holes in the outgoing arguments may be nessecary for
0N/A// varargs C calling conventions.
0N/A// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
0N/A// even aligned with pad0 as needed.
0N/A// Region 6 is even aligned. Region 6-7 is NOT even aligned;
0N/A// region 6-11 is even aligned; it may be padded out more so that
0N/A// the region from SP to FP meets the minimum stack alignment.
0N/A // What direction does stack grow in (assumed to be same for native & Java)
0N/A stack_direction(TOWARDS_LOW);
0N/A // These two registers define part of the calling convention
0N/A // between compiled code and the interpreter.
0N/A inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
0N/A interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
0N/A // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
0N/A cisc_spilling_operand_name(indOffset);
0N/A // Number of stack slots consumed by a Monitor enter
0N/A sync_stack_slots(2);
0N/A sync_stack_slots(1);
0N/A // Compiled code's Frame Pointer
0N/A frame_pointer(R_SP);
0N/A // Stack alignment requirement
0N/A stack_alignment(StackAlignmentInBytes);
0N/A // LP64: Alignment size in bytes (128-bit -> 16 bytes)
0N/A // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
0N/A // Number of stack slots between incoming argument block and the start of
0N/A // a new frame. The PROLOG must add this many slots to the stack. The
0N/A // EPILOG must remove this many slots.
0N/A in_preserve_stack_slots(0);
0N/A // Number of outgoing stack slots killed above the out_preserve_stack_slots
0N/A // for calls to C. Supports the var-args backing area for register parms.
0N/A // ADLC doesn't support parsing expressions, so I folded the math by hand.
0N/A // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
0N/A varargs_C_out_slots_killed(12);
0N/A // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
0N/A varargs_C_out_slots_killed( 7);
0N/A // The after-PROLOG location of the return address. Location of
0N/A // return address specifies a type (REG or STACK) and a number
0N/A // representing the register number (
i.e. - use a register name) or
0N/A return_addr(REG R_I7); // Ret Addr is in register I7
0N/A // Body of function which returns an OptoRegs array locating
0N/A // arguments either in registers or in stack slots for calling
0N/A calling_convention %{
0N/A (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
0N/A // Body of function which returns an OptoRegs array locating
0N/A // arguments either in registers or in stack slots for callin
0N/A c_calling_convention %{
0N/A // This is obviously always outgoing
0N/A (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
0N/A // Location of native (C/C++) and interpreter return values. This is specified to
0N/A // be the same as Java. In the 32-bit VM, long values are actually returned from
0N/A // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
0N/A // to and from the register pairs is done by the appropriate call and epilog
0N/A // opcodes. This simplifies the register allocator.
0N/A assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
113N/A static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
113N/A static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
113N/A static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
113N/A static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
113N/A static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
113N/A static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
113N/A static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
113N/A static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
0N/A return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
0N/A (is_outgoing?lo_out:lo_in)[ideal_reg] );
0N/A // Location of compiled Java return values. Same as C
0N/A assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
113N/A static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
113N/A static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
113N/A static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
113N/A static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
113N/A static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
113N/A static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
113N/A static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
113N/A static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
0N/A return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
0N/A (is_outgoing?lo_out:lo_in)[ideal_reg] );
0N/A//----------ATTRIBUTES---------------------------------------------------------
0N/A//----------Operand Attributes-------------------------------------------------
0N/Aop_attrib op_cost(1); // Required cost attribute
0N/A//----------Instruction Attributes---------------------------------------------
0N/Ains_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2667N/Ains_attrib ins_size(32); // Required size attribute (in bits)
2676N/Ains_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
2667N/Ains_attrib ins_short_branch(0); // Required flag: is this instruction a
2667N/A // non-matching short branch variant of some
0N/A//----------OPERANDS-----------------------------------------------------------
0N/A// Operand definitions must precede instruction definitions for correct parsing
0N/A// in the ADLC because operands constitute user defined types which are used in
0N/A// instruction definitions.
0N/A//----------Simple Operands----------------------------------------------------
0N/A// Immediate Operands
0N/A// Integer Immediate: 32-bit
0N/A // formats are generated automatically for constants and base registers
0N/A interface(CONST_INTER);
824N/A// Integer Immediate: 8-bit
2957N/A predicate(Assembler::is_simm8(n->get_int()));
824N/A interface(CONST_INTER);
0N/A// Integer Immediate: 13-bit
0N/A predicate(Assembler::is_simm13(n->get_int()));
0N/A interface(CONST_INTER);
785N/A// Integer Immediate: 13-bit minus 7
785N/A predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
785N/A interface(CONST_INTER);
824N/A// Integer Immediate: 16-bit
2957N/A predicate(Assembler::is_simm16(n->get_int()));
824N/A interface(CONST_INTER);
0N/A// Unsigned (positive) Integer Immediate: 13-bit
0N/A predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: 6-bit
0N/A predicate(n->get_int() >= 0 && n->get_int() <= 63);
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: 11-bit
2957N/A predicate(Assembler::is_simm11(n->get_int()));
0N/A interface(CONST_INTER);
2957N/A predicate(Assembler::is_simm5(n->get_int()));
0N/A// Integer Immediate: 0-bit
0N/A predicate(n->get_int() == 0);
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: the value 10
0N/A predicate(n->get_int() == 10);
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: the values 0-31
0N/A predicate(n->get_int() >= 0 && n->get_int() <= 31);
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: the values 1-31
0N/Aoperand immI_1_31() %{
0N/A predicate(n->get_int() >= 1 && n->get_int() <= 31);
0N/A interface(CONST_INTER);
0N/A// Integer Immediate: the values 32-63
0N/Aoperand immI_32_63() %{
0N/A predicate(n->get_int() >= 32 && n->get_int() <= 63);
0N/A interface(CONST_INTER);
785N/A// Immediates for special shifts (sign extend)
785N/A// Integer Immediate: the value 16
785N/A predicate(n->get_int() == 16);
785N/A interface(CONST_INTER);
785N/A// Integer Immediate: the value 24
785N/A predicate(n->get_int() == 24);
785N/A interface(CONST_INTER);
0N/A// Integer Immediate: the value 255
0N/Aoperand immI_255() %{
0N/A predicate( n->get_int() == 255 );
0N/A interface(CONST_INTER);
785N/A// Integer Immediate: the value 65535
785N/A predicate(n->get_int() == 65535);
785N/A interface(CONST_INTER);
0N/A// Long Immediate: the value FF
0N/A predicate( n->get_long() == 0xFFL );
0N/A interface(CONST_INTER);
0N/A// Long Immediate: the value FFFF
0N/Aoperand immL_FFFF() %{
0N/A predicate( n->get_long() == 0xFFFFL );
0N/A interface(CONST_INTER);
0N/A// Pointer Immediate: 32 or 64-bit
0N/A // formats are generated automatically for constants and base registers
0N/A interface(CONST_INTER);
1964N/A// Pointer Immediate: 64-bit
1968N/A predicate(!VM_Version::is_niagara_plus());
1915N/A // formats are generated automatically for constants and base registers
1964N/A// Pointer Immediate: 64-bit
1915N/A// From Niagara2 processors on a load should be better than materializing.
1968N/A predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
1915N/A // formats are generated automatically for constants and base registers
1964N/A// Pointer Immediate: 64-bit
1964N/Aoperand immP_no_oop_cheap() %{
1968N/A predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
1964N/A // formats are generated automatically for constants and base registers
0N/A predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
0N/A interface(CONST_INTER);
0N/A predicate(n->get_ptr() == 0);
0N/A interface(CONST_INTER);
0N/Aoperand immP_poll() %{
0N/A predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
0N/A // formats are generated automatically for constants and base registers
0N/A interface(CONST_INTER);
113N/A interface(CONST_INTER);
113N/A// NULL Pointer Immediate
113N/A predicate(n->get_narrowcon() == 0);
113N/A interface(CONST_INTER);
0N/A // formats are generated automatically for constants and base registers
0N/A interface(CONST_INTER);
0N/A predicate(n->get_long() == 0L);
0N/A // formats are generated automatically for constants and base registers
0N/A interface(CONST_INTER);
2957N/A predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
0N/A// Long Immediate: 13-bit
0N/A predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
0N/A interface(CONST_INTER);
785N/A// Long Immediate: 13-bit minus 7
785N/A predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
785N/A interface(CONST_INTER);
0N/A// Long Immediate: low 32-bit mask
0N/Aoperand immL_32bits() %{
0N/A predicate(n->get_long() == 0xFFFFFFFFL);
0N/A interface(CONST_INTER);
1915N/A// Long Immediate: cheap (materialize in <= 3 instructions)
1968N/A predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
1915N/A// Long Immediate: expensive (materialize in > 3 instructions)
1968N/A predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
0N/A interface(CONST_INTER);
0N/A // on 64-bit architectures this comparision is faster
0N/A predicate(jlong_cast(n->getd()) == 0);
0N/A predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
0N/A interface(CONST_INTER);
0N/A interface(CONST_INTER);
0N/A// Float Immediate: 0
0N/A predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
0N/A interface(CONST_INTER);
0N/A// Integer Register Operands
0N/A constraint(ALLOC_IN_RC(int_reg));
0N/A match(notemp_iRegI);
0N/A interface(REG_INTER);
0N/Aoperand notemp_iRegI() %{
0N/A constraint(ALLOC_IN_RC(notemp_int_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o0_regI));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(lock_ptr_RegP);
0N/A interface(REG_INTER);
0N/Aoperand sp_ptr_RegP() %{
0N/A constraint(ALLOC_IN_RC(sp_ptr_reg));
0N/A interface(REG_INTER);
0N/Aoperand lock_ptr_RegP() %{
0N/A constraint(ALLOC_IN_RC(lock_ptr_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g1_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g2_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g3_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g1_regI));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g3_regI));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g4_regI));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g4_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(i0_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o0_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o1_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o2_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o7_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(l7_regP));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o7_regI));
0N/A interface(REG_INTER);
113N/A constraint(ALLOC_IN_RC(int_reg));
0N/A constraint(ALLOC_IN_RC(long_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o2_regL));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(o7_regL));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(g1_regL));
0N/A interface(REG_INTER);
420N/A constraint(ALLOC_IN_RC(g3_regL));
0N/A// This is 64bit safe
0N/Aoperand iRegIsafe() %{
0N/A constraint(ALLOC_IN_RC(long_reg));
0N/A interface(REG_INTER);
0N/A// Condition Code Flag Register
0N/Aoperand flagsReg() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "ccr" %} // both ICC and XCC
0N/A interface(REG_INTER);
0N/A// Condition Code Register, unsigned comparisons.
0N/Aoperand flagsRegU() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "icc_U" %}
0N/A interface(REG_INTER);
0N/A// Condition Code Register, pointer comparisons.
0N/Aoperand flagsRegP() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "xcc_P" %}
0N/A format %{ "icc_P" %}
0N/A interface(REG_INTER);
0N/A// Condition Code Register, long comparisons.
0N/Aoperand flagsRegL() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "xcc_L" %}
0N/A interface(REG_INTER);
0N/A// Condition Code Register, floating comparisons, unordered same as "less".
0N/Aoperand flagsRegF() %{
0N/A constraint(ALLOC_IN_RC(float_flags));
0N/A interface(REG_INTER);
0N/Aoperand flagsRegF0() %{
0N/A constraint(ALLOC_IN_RC(float_flag0));
0N/A interface(REG_INTER);
0N/A// Condition Code Flag Register used by long compare
0N/Aoperand flagsReg_long_LTGE() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "icc_LTGE" %}
0N/A interface(REG_INTER);
0N/Aoperand flagsReg_long_EQNE() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "icc_EQNE" %}
0N/A interface(REG_INTER);
0N/Aoperand flagsReg_long_LEGT() %{
0N/A constraint(ALLOC_IN_RC(int_flags));
0N/A format %{ "icc_LEGT" %}
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(dflt_reg));
0N/A interface(REG_INTER);
0N/A constraint(ALLOC_IN_RC(sflt_reg));
0N/A interface(REG_INTER);
0N/Aoperand regD_low() %{
0N/A constraint(ALLOC_IN_RC(dflt_low_reg));
0N/A interface(REG_INTER);
0N/Aoperand inline_cache_regP(iRegP reg) %{
0N/A constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
0N/A interface(REG_INTER);
0N/Aoperand interpreter_method_oop_regP(iRegP reg) %{
0N/A constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
0N/A interface(REG_INTER);
0N/A//----------Complex Operands---------------------------------------------------
0N/A// Indirect Memory Reference
0N/Aoperand indirect(sp_ptr_RegP reg) %{
0N/A constraint(ALLOC_IN_RC(sp_ptr_reg));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
785N/A// Indirect with simm13 Offset
0N/Aoperand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
0N/A constraint(ALLOC_IN_RC(sp_ptr_reg));
0N/A match(AddP reg offset);
0N/A format %{ "[$reg + $offset]" %}
0N/A interface(MEMORY_INTER) %{
785N/A// Indirect with simm13 Offset minus 7
785N/Aoperand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
785N/A constraint(ALLOC_IN_RC(sp_ptr_reg));
785N/A match(AddP reg offset);
785N/A format %{ "[$reg + $offset]" %}
785N/A interface(MEMORY_INTER) %{
0N/A// Note: Intel has a swapped version also, like this:
0N/A//operand indOffsetX(iRegI reg, immP offset) %{
0N/A// constraint(ALLOC_IN_RC(int_reg));
0N/A// match(AddP offset reg);
0N/A// format %{ "[$reg + $offset]" %}
0N/A// interface(MEMORY_INTER) %{
0N/A//// However, it doesn't make sense for SPARC, since
0N/A// we have no particularly good way to embed oops in
0N/A// single instructions.
0N/A// Indirect with Register Index
0N/Aoperand indIndex(iRegP addr, iRegX index) %{
0N/A constraint(ALLOC_IN_RC(ptr_reg));
0N/A match(AddP addr index);
0N/A format %{ "[$addr + $index]" %}
0N/A interface(MEMORY_INTER) %{
0N/A//----------Special Memory Operands--------------------------------------------
0N/A// Stack Slot Operand - This operand is used for loading and storing temporary
0N/A// values on the stack where a match requires a value to
0N/A// flow through memory.
0N/Aoperand stackSlotI(sRegI reg) %{
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotP(sRegP reg) %{
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotF(sRegF reg) %{
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotD(sRegD reg) %{
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A disp($reg); // Stack Offset
0N/Aoperand stackSlotL(sRegL reg) %{
0N/A constraint(ALLOC_IN_RC(stack_slots));
0N/A format %{ "[$reg]" %}
0N/A interface(MEMORY_INTER) %{
0N/A disp($reg); // Stack Offset
0N/A// Operands for expressing Control Flow
0N/A// NOTE: Label is a predefined operand which should not be redefined in
0N/A// the AD file. It is generically handled within the ADLC.
0N/A//----------Conditional Branch Operands----------------------------------------
0N/A// Comparison Op - This is the operation of the comparison, and is limited to
0N/A// the following set of codes:
0N/A// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
0N/A// Other attributes of the comparison, such as unsignedness, are specified
0N/A// by the comparison instruction that sets a condition code flags register.
0N/A// That result is represented by a flags operand whose subtype is appropriate
0N/A// to the unsignedness (etc.) of the comparison.
0N/A// Later, the instruction which matches both the Comparison Op (a Bool) and
0N/A// the flags (produced by the Cmp) specifies the coding of the comparison op
0N/A// by matching a specific subtype of Bool operand below, such as cmpOpU.
0N/A interface(COND_INTER) %{
0N/A// Comparison Op, unsigned
0N/A interface(COND_INTER) %{
0N/A// Comparison Op, pointer (same as unsigned)
0N/A interface(COND_INTER) %{
0N/A// Comparison Op, branch-register encoding
0N/Aoperand cmpOp_reg() %{
0N/A interface(COND_INTER) %{
0N/A// Comparison Code, floating, unordered same as less
0N/A interface(COND_INTER) %{
0N/A// Used by long compare
0N/Aoperand cmpOp_commute() %{
0N/A interface(COND_INTER) %{
0N/A//----------OPERAND CLASSES----------------------------------------------------
0N/A// Operand Classes are groups of operands that are used to simplify
605N/A// instruction definitions by not requiring the AD writer to specify separate
0N/A// instructions for every form of operand when the instruction accepts
0N/A// multiple operand types with the same basic encoding and format. The classic
0N/A// case of this is memory operands.
0N/Aopclass memory( indirect, indOffset13, indIndex );
1396N/Aopclass indIndexMemory( indIndex );
0N/A//----------PIPELINE-----------------------------------------------------------
0N/A//----------ATTRIBUTES---------------------------------------------------------
0N/A fixed_size_instructions; // Fixed size instructions
0N/A branch_has_delay_slot; // Branch has delay slot following
0N/A max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
0N/A instruction_unit_size = 4; // An instruction is 4 bytes long
0N/A instruction_fetch_unit_size = 16; // The processor fetches one line
0N/A instruction_fetch_units = 1; // of 16 bytes
0N/A // List of nop instructions
0N/A nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
0N/A//----------RESOURCES----------------------------------------------------------
0N/A// Resources are the functional units available to the machine
0N/Aresources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
0N/A//----------PIPELINE DESCRIPTION-----------------------------------------------
0N/A// Pipeline Description specifies the stages in the machine's pipeline
0N/Apipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
0N/A//----------PIPELINE CLASSES---------------------------------------------------
0N/A// Pipeline Classes describe the stages in which input and output are
0N/A// referenced by the hardware pipeline.
0N/A// Integer ALU reg-reg operation
0N/Apipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A// Integer ALU reg-reg long operation
0N/Apipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
0N/A instruction_count(2);
0N/A// Integer ALU reg-reg long dependent operation
0N/Apipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer ALU reg-imm operaion
0N/Apipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
0N/A// Integer ALU reg-reg operation with condition code
0N/Apipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
0N/A// Integer ALU reg-imm operation with condition code
0N/Apipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
0N/A// Integer ALU zero-reg operation
0N/Apipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
0N/A// Integer ALU zero-reg operation with condition code only
0N/Apipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
0N/A// Integer ALU reg-reg operation with condition code only
0N/Apipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
0N/A// Integer ALU reg-imm operation with condition code only
0N/Apipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
0N/A// Integer ALU reg-reg-zero operation with condition code only
0N/Apipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
0N/A// Integer ALU reg-imm-zero operation with condition code only
0N/Apipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
0N/A// Integer ALU reg-reg operation with condition code, src1 modified
0N/Apipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
0N/A// Integer ALU reg-imm operation with condition code, src1 modified
0N/Apipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
0N/Apipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
0N/A// Integer ALU operation
0N/Apipe_class ialu_none(iRegI dst) %{
0N/A// Integer ALU reg operation
0N/Apipe_class ialu_reg(iRegI dst, iRegI src) %{
0N/A single_instruction; may_have_no_code;
0N/A// Integer ALU reg conditional operation
0N/A// This instruction has a 1 cycle stall, and cannot execute
0N/A// in the same cycle as the instruction setting the condition
0N/A// code. We kludge this by pretending to read the condition code
0N/A// 1 cycle earlier, and by marking the functional units as busy
0N/A// for 2 cycles with the result available 1 cycle later than
0N/A// is really the case.
0N/Apipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
0N/A cr : R(read); // This is really E, with a 1 cycle stall
0N/Apipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer ALU reg operation
0N/Apipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
0N/A single_instruction; may_have_no_code;
0N/Apipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
0N/A single_instruction; may_have_no_code;
0N/A// Two integer ALU reg operations
0N/Apipe_class ialu_reg_2(iRegL dst, iRegL src) %{
0N/A instruction_count(2);
0N/A// Two integer ALU reg operations
0N/Apipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
0N/A instruction_count(2); may_have_no_code;
0N/A// Integer ALU imm operation
0N/Apipe_class ialu_imm(iRegI dst, immI13 src) %{
0N/A// Integer ALU reg-reg with carry operation
0N/Apipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
0N/A// Integer ALU cc operation
0N/Apipe_class ialu_cc(iRegI dst, flagsReg cc) %{
0N/A// Integer ALU cc / second IALU operation
0N/Apipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer ALU cc / second IALU operation
0N/Apipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer ALU hi-lo-reg operation
0N/Apipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Float ALU hi-lo-reg operation (with temp)
0N/Apipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
0N/A instruction_count(1); multiple_bundles;
0N/Apipe_class loadConL( iRegL dst, immL src ) %{
0N/A instruction_count(2); multiple_bundles;
0N/Apipe_class loadConP( iRegP dst, immP src ) %{
0N/A instruction_count(0); multiple_bundles;
0N/Apipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
0N/A instruction_count(0); multiple_bundles;
0N/A// Long Constant small
0N/Apipe_class loadConLlo( iRegL dst, immL src ) %{
0N/A instruction_count(2);
0N/A// [PHH] This is wrong for 64-bit. See LdImmF/D.
0N/Apipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer ALU nop operation
0N/Apipe_class ialu_nop() %{
0N/A// Integer ALU nop operation
0N/Apipe_class ialu_nop_A0() %{
0N/A// Integer ALU nop operation
0N/Apipe_class ialu_nop_A1() %{
0N/A// Integer Multiply reg-reg operation
0N/Apipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A// Integer Multiply reg-imm operation
0N/Apipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
0N/Apipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/Apipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
0N/A// Integer Divide reg-reg
0N/Apipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Integer Divide reg-imm
0N/Apipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/Apipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/Apipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
0N/A// Floating Point Add Float
0N/Apipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A// Floating Point Add Double
0N/Apipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A// Floating Point Conditional Move based on integer flags
0N/Apipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
0N/A// Floating Point Conditional Move based on integer flags
0N/Apipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
0N/A// Floating Point Multiply Float
0N/Apipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A// Floating Point Multiply Double
0N/Apipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A// Floating Point Divide Float
0N/Apipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A// Floating Point Divide Double
0N/Apipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
0N/Apipe_class faddF_reg(regF dst, regF src) %{
0N/Apipe_class faddD_reg(regD dst, regD src) %{
0N/A// Floating Point Convert F->D
0N/Apipe_class fcvtF2D(regD dst, regF src) %{
0N/A// Floating Point Convert I->D
0N/Apipe_class fcvtI2D(regD dst, regF src) %{
0N/A// Floating Point Convert LHi->D
0N/Apipe_class fcvtLHi2D(regD dst, regD src) %{
0N/A// Floating Point Convert L->D
0N/Apipe_class fcvtL2D(regD dst, regF src) %{
0N/A// Floating Point Convert L->F
0N/Apipe_class fcvtL2F(regD dst, regF src) %{
0N/A// Floating Point Convert D->F
0N/Apipe_class fcvtD2F(regD dst, regF src) %{
0N/A// Floating Point Convert I->L
0N/Apipe_class fcvtI2L(regD dst, regF src) %{
0N/A// Floating Point Convert D->F
0N/Apipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Floating Point Convert D->L
0N/Apipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Floating Point Convert F->I
0N/Apipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Floating Point Convert F->L
0N/Apipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
0N/A instruction_count(1); multiple_bundles;
0N/A// Floating Point Convert I->F
0N/Apipe_class fcvtI2F(regF dst, regF src) %{
0N/A// Floating Point Compare
0N/Apipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
0N/A// Floating Point Compare
0N/Apipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
0N/Apipe_class fadd_nop() %{
0N/A// Integer Store to Memory
0N/Apipe_class istore_mem_reg(memory mem, iRegI src) %{
0N/A// Integer Store to Memory
0N/Apipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
0N/A// Integer Store Zero to Memory
0N/Apipe_class istore_mem_zero(memory mem, immI0 src) %{
0N/A// Special Stack Slot Store
0N/Apipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
0N/A// Special Stack Slot Store
0N/Apipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
0N/A instruction_count(2); multiple_bundles;
0N/Apipe_class fstoreF_mem_reg(memory mem, RegF src) %{
0N/Apipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
0N/Apipe_class fstoreD_mem_reg(memory mem, RegD src) %{
0N/A instruction_count(1);
0N/Apipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
0N/A// Special Stack Slot Float Store
0N/Apipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
0N/A// Special Stack Slot Double Store
0N/Apipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
0N/A// Integer Load (when sign bit propagation not needed)
0N/Apipe_class iload_mem(iRegI dst, memory mem) %{
0N/A// Integer Load from stack operand
0N/Apipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
0N/A// Integer Load (when sign bit propagation or masking is needed)
0N/Apipe_class iload_mask_mem(iRegI dst, memory mem) %{
0N/Apipe_class floadF_mem(regF dst, memory mem) %{
0N/Apipe_class floadD_mem(regD dst, memory mem) %{
0N/A instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
0N/Apipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
0N/Apipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
0N/Apipe_class mem_nop() %{
0N/Apipe_class sethi(iRegP dst, immI src) %{
0N/Apipe_class loadPollP(iRegP poll) %{
0N/Apipe_class br(Universe br, label labl) %{
0N/A single_instruction_with_delay_slot;
0N/Apipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
0N/A single_instruction_with_delay_slot;
0N/Apipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
0N/A single_instruction_with_delay_slot;
2676N/Apipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
2676N/A instruction_count(2); has_delay_slot;
2676N/Apipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
2676N/A instruction_count(2); has_delay_slot;
2676N/A// Compare and branch using cbcond
2676N/Apipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
2676N/A// Compare and branch using cbcond
2676N/Apipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
0N/Apipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
0N/A single_instruction_with_delay_slot;
0N/Apipe_class br_nop() %{
0N/Apipe_class simple_call(method meth) %{
0N/A instruction_count(2); multiple_bundles; force_serialization;
0N/Apipe_class compiled_call(method meth) %{
0N/A instruction_count(1); multiple_bundles; force_serialization;
0N/Apipe_class call(method meth) %{
0N/A instruction_count(0); multiple_bundles; force_serialization;
0N/Apipe_class tail_call(Universe ignore, label labl) %{
0N/A single_instruction; has_delay_slot;
0N/Apipe_class ret(Universe ignore) %{
0N/A single_instruction; has_delay_slot;
0N/Apipe_class ret_poll(g3RegP poll) %{
0N/A instruction_count(3); has_delay_slot;
0N/A// The real do-nothing guy
0N/Apipe_class empty( ) %{
0N/A instruction_count(0);
0N/Apipe_class long_memory_op() %{
0N/A instruction_count(0); multiple_bundles; force_serialization;
0N/Apipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
0N/A// Convert FPU flags into +1,0,-1
0N/Apipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
0N/A// Compare for p < q, and conditionally add y
0N/Apipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
0N/A// Perform a compare, then move conditionally in a branch delay slot.
0N/Apipe_class min_max( iRegI src2, iRegI srcdst ) %{
0N/A// Define the class for the Nop node
0N/A//----------INSTRUCTIONS-------------------------------------------------------
0N/A//------------Special Stack Slot instructions - no match rules-----------------
0N/Ainstruct stkI_to_regF(regF dst, stackSlotI src) %{
0N/A // No match rule to avoid chain rule match.
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDF $src,$dst\t! stkI to regF" %}
0N/A opcode(Assembler::ldf_op3);
415N/A ins_encode(simple_form3_mem_reg(src, dst));
0N/A ins_pipe(floadF_stk);
0N/Ainstruct stkL_to_regD(regD dst, stackSlotL src) %{
0N/A // No match rule to avoid chain rule match.
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $src,$dst\t! stkL to regD" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg(src, dst));
0N/A ins_pipe(floadD_stk);
0N/Ainstruct regF_to_stkI(stackSlotI dst, regF src) %{
0N/A // No match rule to avoid chain rule match.
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STF $src,$dst\t! regF to stkI" %}
0N/A opcode(Assembler::stf_op3);
415N/A ins_encode(simple_form3_mem_reg(dst, src));
0N/A ins_pipe(fstoreF_stk_reg);
0N/Ainstruct regD_to_stkL(stackSlotL dst, regD src) %{
0N/A // No match rule to avoid chain rule match.
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$dst\t! regD to stkL" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg(dst, src));
0N/A ins_pipe(fstoreD_stk_reg);
0N/Ainstruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST*2);
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
0N/A ins_pipe(lstoreI_stk_reg);
0N/Ainstruct regL_to_stkD(stackSlotD dst, iRegL src) %{
0N/A // No match rule to avoid chain rule match.
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$dst\t! regL to stkD" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_stk_reg);
0N/A//---------- Chain stack slots between similar types --------
0N/A// Load integer from stack slot
0N/Ainstruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $src,$dst\t!stk" %}
0N/A opcode(Assembler::lduw_op3);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/A// Store integer to stack slot
0N/Ainstruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$dst\t!stk" %}
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/A// Load long from stack slot
0N/Ainstruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDX $src,$dst\t! long" %}
0N/A opcode(Assembler::ldx_op3);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/A// Store long to stack slot
0N/Ainstruct regL_to_stkL(stackSlotL dst, iRegL src) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$dst\t! long" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/A// Load pointer from stack slot, 64-bit encoding
0N/Ainstruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDX $src,$dst\t!ptr" %}
0N/A opcode(Assembler::ldx_op3);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/A// Store pointer to stack slot
0N/Ainstruct regP_to_stkP(stackSlotP dst, iRegP src) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$dst\t!ptr" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/A// Load pointer from stack slot, 32-bit encoding
0N/Ainstruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $src,$dst\t!ptr" %}
0N/A opcode(Assembler::lduw_op3, Assembler::ldst_op);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/A// Store pointer to stack slot
0N/Ainstruct regP_to_stkP(stackSlotP dst, iRegP src) %{
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$dst\t!ptr" %}
0N/A opcode(Assembler::stw_op3, Assembler::ldst_op);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/A//------------Special Nop instructions for bundling - no match rules-----------
0N/A// Nop using the A0 functional unit
0N/A format %{ "NOP ! Alu Pipeline" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form2_nop() );
0N/A ins_pipe(ialu_nop_A0);
0N/A// Nop using the A1 functional unit
0N/Ainstruct Nop_A1( ) %{
0N/A format %{ "NOP ! Alu Pipeline" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form2_nop() );
0N/A ins_pipe(ialu_nop_A1);
0N/A// Nop using the memory functional unit
0N/Ainstruct Nop_MS( ) %{
0N/A format %{ "NOP ! Memory Pipeline" %}
0N/A ins_encode( emit_mem_nop );
0N/A// Nop using the floating add functional unit
0N/Ainstruct Nop_FA( ) %{
0N/A format %{ "NOP ! Floating Add Pipeline" %}
0N/A ins_encode( emit_fadd_nop );
0N/A// Nop using the branch functional unit
0N/Ainstruct Nop_BR( ) %{
0N/A format %{ "NOP ! Branch Pipeline" %}
0N/A ins_encode( emit_br_nop );
0N/A//----------Load
/Store/Move Instructions---------------------------------------
0N/A//----------Load Instructions--------------------------------------------------
0N/A// Load Byte (8bit signed)
0N/Ainstruct loadB(iRegI dst, memory mem) %{
0N/A match(Set dst (LoadB mem));
0N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDSB $mem,$dst\t! byte" %}
727N/A __ ldsb($mem$$Address, $dst$$Register);
624N/A ins_pipe(iload_mask_mem);
624N/A// Load Byte (8bit signed) into a Long Register
624N/Ainstruct loadB2L(iRegL dst, memory mem) %{
624N/A match(Set dst (ConvI2L (LoadB mem)));
624N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDSB $mem,$dst\t! byte -> long" %}
727N/A __ ldsb($mem$$Address, $dst$$Register);
0N/A ins_pipe(iload_mask_mem);
624N/A// Load Unsigned Byte (8bit UNsigned) into an int reg
624N/Ainstruct loadUB(iRegI dst, memory mem) %{
624N/A match(Set dst (LoadUB mem));
0N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDUB $mem,$dst\t! ubyte" %}
727N/A __ ldub($mem$$Address, $dst$$Register);
624N/A// Load Unsigned Byte (8bit UNsigned) into a Long Register
624N/Ainstruct loadUB2L(iRegL dst, memory mem) %{
624N/A match(Set dst (ConvI2L (LoadUB mem)));
624N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
727N/A __ ldub($mem$$Address, $dst$$Register);
824N/A// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
824N/Ainstruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
824N/A ins_cost(MEMORY_REF_COST + DEFAULT_COST);
824N/A format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
824N/A "AND $dst,$mask,$dst" %}
824N/A __ ldub($mem$$Address, $dst$$Register);
824N/A __ and3($dst$$Register, $mask$$constant, $dst$$Register);
624N/A// Load Short (16bit signed)
624N/Ainstruct loadS(iRegI dst, memory mem) %{
624N/A match(Set dst (LoadS mem));
624N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDSH $mem,$dst\t! short" %}
727N/A __ ldsh($mem$$Address, $dst$$Register);
624N/A ins_pipe(iload_mask_mem);
785N/A// Load Short (16 bit signed) to Byte (8 bit signed)
785N/Ainstruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
785N/A match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
785N/A ins_cost(MEMORY_REF_COST);
785N/A format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
785N/A __ ldsb($mem$$Address, $dst$$Register, 1);
785N/A ins_pipe(iload_mask_mem);
624N/A// Load Short (16bit signed) into a Long Register
624N/Ainstruct loadS2L(iRegL dst, memory mem) %{
624N/A match(Set dst (ConvI2L (LoadS mem)));
0N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDSH $mem,$dst\t! short -> long" %}
727N/A __ ldsh($mem$$Address, $dst$$Register);
624N/A ins_pipe(iload_mask_mem);
624N/Ainstruct loadUS(iRegI dst, memory mem) %{
624N/A match(Set dst (LoadUS mem));
624N/A ins_cost(MEMORY_REF_COST);
727N/A __ lduh($mem$$Address, $dst$$Register);
785N/Ainstruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
785N/A match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
785N/A ins_cost(MEMORY_REF_COST);
785N/A format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
785N/A __ ldsb($mem$$Address, $dst$$Register, 1);
785N/A ins_pipe(iload_mask_mem);
624N/Ainstruct loadUS2L(iRegL dst, memory mem) %{
624N/A match(Set dst (ConvI2L (LoadUS mem)));
0N/A ins_cost(MEMORY_REF_COST);
727N/A __ lduh($mem$$Address, $dst$$Register);
824N/A// Load Unsigned
Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
824N/Ainstruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
824N/A ins_cost(MEMORY_REF_COST);
824N/A __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
824N/A// Load Unsigned
Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
824N/Ainstruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
824N/A ins_cost(MEMORY_REF_COST + DEFAULT_COST);
824N/A "AND $dst,$mask,$dst" %}
824N/A Register Rdst = $dst$$Register;
824N/A __ lduh($mem$$Address, Rdst);
824N/A __ and3(Rdst, $mask$$constant, Rdst);
824N/A// Load Unsigned
Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
824N/Ainstruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
824N/A match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
824N/A effect(TEMP dst, TEMP tmp);
824N/A ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
951N/A size((3+1)*4); // set may use two instructions.
824N/A "AND $dst,$tmp,$dst" %}
824N/A Register Rdst = $dst$$Register;
824N/A Register Rtmp = $tmp$$Register;
824N/A __ lduh($mem$$Address, Rdst);
824N/A __ set($mask$$constant, Rtmp);
824N/A __ and3(Rdst, Rtmp, Rdst);
0N/Ainstruct loadI(iRegI dst, memory mem) %{
0N/A match(Set dst (LoadI mem));
0N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDUW $mem,$dst\t! int" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
785N/A// Load Integer to Byte (8 bit signed)
785N/Ainstruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
785N/A match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
785N/A ins_cost(MEMORY_REF_COST);
785N/A format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
785N/A __ ldsb($mem$$Address, $dst$$Register, 3);
785N/A ins_pipe(iload_mask_mem);
785N/A// Load Integer to Unsigned Byte (8 bit UNsigned)
785N/Ainstruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
785N/A match(Set dst (AndI (LoadI mem) mask));
785N/A ins_cost(MEMORY_REF_COST);
785N/A format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
785N/A __ ldub($mem$$Address, $dst$$Register, 3);
785N/A ins_pipe(iload_mask_mem);
785N/A// Load Integer to Short (16 bit signed)
785N/Ainstruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
785N/A match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
785N/A ins_cost(MEMORY_REF_COST);
785N/A format %{ "LDSH $mem+2,$dst\t! int -> short" %}
785N/A __ ldsh($mem$$Address, $dst$$Register, 2);
785N/A ins_pipe(iload_mask_mem);
785N/A// Load Integer to Unsigned Short (16 bit UNsigned)
785N/Ainstruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
785N/A match(Set dst (AndI (LoadI mem) mask));
785N/A ins_cost(MEMORY_REF_COST);
785N/A __ lduh($mem$$Address, $dst$$Register, 2);
785N/A ins_pipe(iload_mask_mem);
624N/A// Load Integer into a Long Register
624N/Ainstruct loadI2L(iRegL dst, memory mem) %{
624N/A match(Set dst (ConvI2L (LoadI mem)));
624N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDSW $mem,$dst\t! int -> long" %}
727N/A __ ldsw($mem$$Address, $dst$$Register);
824N/A ins_pipe(iload_mask_mem);
824N/A// Load Integer with mask 0xFF into a Long Register
824N/Ainstruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
824N/A ins_cost(MEMORY_REF_COST);
824N/A format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
824N/A __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
824N/A// Load Integer with mask 0xFFFF into a Long Register
824N/Ainstruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
824N/A ins_cost(MEMORY_REF_COST);
824N/A format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
824N/A __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
824N/A// Load Integer with a 13-bit mask into a Long Register
824N/Ainstruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
824N/A match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
824N/A ins_cost(MEMORY_REF_COST + DEFAULT_COST);
824N/A format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
824N/A "AND $dst,$mask,$dst" %}
824N/A Register Rdst = $dst$$Register;
824N/A __ lduw($mem$$Address, Rdst);
824N/A __ and3(Rdst, $mask$$constant, Rdst);
824N/A// Load Integer with a 32-bit mask into a Long Register
824N/Ainstruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
824N/A match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
824N/A effect(TEMP dst, TEMP tmp);
824N/A ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
951N/A size((3+1)*4); // set may use two instructions.
824N/A format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
824N/A "AND $dst,$tmp,$dst" %}
824N/A Register Rdst = $dst$$Register;
824N/A Register Rtmp = $tmp$$Register;
824N/A __ lduw($mem$$Address, Rdst);
824N/A __ set($mask$$constant, Rtmp);
824N/A __ and3(Rdst, Rtmp, Rdst);
624N/A// Load Unsigned Integer into a Long Register
624N/Ainstruct loadUI2L(iRegL dst, memory mem) %{
624N/A match(Set dst (LoadUI2L mem));
624N/A ins_cost(MEMORY_REF_COST);
624N/A format %{ "LDUW $mem,$dst\t! uint -> long" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
0N/A ins_pipe(iload_mem);
0N/A// Load Long - aligned
0N/Ainstruct loadL(iRegL dst, memory mem ) %{
0N/A match(Set dst (LoadL mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDX $mem,$dst\t! long" %}
727N/A __ ldx($mem$$Address, $dst$$Register);
0N/A ins_pipe(iload_mem);
0N/A// Load Long - UNaligned
0N/Ainstruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
0N/A match(Set dst (LoadL_unaligned mem));
0N/A ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
0N/A format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
0N/A "\tLDUW $mem ,$dst\n"
0N/A "\tSLLX #32, $dst, $dst\n"
0N/A "\tOR $dst, R_O7, $dst" %}
0N/A opcode(Assembler::lduw_op3);
415N/A ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
0N/A ins_pipe(iload_mem);
0N/A// Load Aligned Packed Byte into a Double Register
0N/Ainstruct loadA8B(regD dst, memory mem) %{
0N/A match(Set dst (Load8B mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $mem,$dst\t! packed8B" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadD_mem);
0N/A// Load Aligned Packed Char into a Double Register
0N/Ainstruct loadA4C(regD dst, memory mem) %{
0N/A match(Set dst (Load4C mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $mem,$dst\t! packed4C" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadD_mem);
0N/A// Load Aligned Packed Short into a Double Register
0N/Ainstruct loadA4S(regD dst, memory mem) %{
0N/A match(Set dst (Load4S mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $mem,$dst\t! packed4S" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadD_mem);
0N/A// Load Aligned Packed Int into a Double Register
0N/Ainstruct loadA2I(regD dst, memory mem) %{
0N/A match(Set dst (Load2I mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $mem,$dst\t! packed2I" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadD_mem);
0N/Ainstruct loadRange(iRegI dst, memory mem) %{
0N/A match(Set dst (LoadRange mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $mem,$dst\t! range" %}
0N/A opcode(Assembler::lduw_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(iload_mem);
0N/Ainstruct loadI_freg(regF dst, memory mem) %{
0N/A match(Set dst (LoadI mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A opcode(Assembler::ldf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadF_mem);
0N/Ainstruct loadP(iRegP dst, memory mem) %{
0N/A match(Set dst (LoadP mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $mem,$dst\t! ptr" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
0N/A format %{ "LDX $mem,$dst\t! ptr" %}
727N/A __ ldx($mem$$Address, $dst$$Register);
0N/A ins_pipe(iload_mem);
113N/A// Load Compressed Pointer
113N/Ainstruct loadN(iRegN dst, memory mem) %{
727N/A match(Set dst (LoadN mem));
727N/A ins_cost(MEMORY_REF_COST);
727N/A format %{ "LDUW $mem,$dst\t! compressed ptr" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
0N/A// Load Klass Pointer
0N/Ainstruct loadKlass(iRegP dst, memory mem) %{
0N/A match(Set dst (LoadKlass mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $mem,$dst\t! klass ptr" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
0N/A format %{ "LDX $mem,$dst\t! klass ptr" %}
727N/A __ ldx($mem$$Address, $dst$$Register);
0N/A ins_pipe(iload_mem);
164N/A// Load narrow Klass Pointer
164N/Ainstruct loadNKlass(iRegN dst, memory mem) %{
164N/A match(Set dst (LoadNKlass mem));
113N/A ins_cost(MEMORY_REF_COST);
113N/A format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
727N/A __ lduw($mem$$Address, $dst$$Register);
0N/Ainstruct loadD(regD dst, memory mem) %{
0N/A match(Set dst (LoadD mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $mem,$dst" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadD_mem);
0N/A// Load Double - UNaligned
0N/Ainstruct loadD_unaligned(regD_low dst, memory mem ) %{
0N/A match(Set dst (LoadD_unaligned mem));
0N/A ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
0N/A format %{ "LDF $mem ,$
dst.hi\t! misaligned double\n"
0N/A opcode(Assembler::ldf_op3);
0N/A ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
0N/A ins_pipe(iload_mem);
0N/Ainstruct loadF(regF dst, memory mem) %{
0N/A match(Set dst (LoadF mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDF $mem,$dst" %}
0N/A opcode(Assembler::ldf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(floadF_mem);
0N/Ainstruct loadConI( iRegI dst, immI src ) %{
0N/A ins_cost(DEFAULT_COST * 3/2);
0N/A format %{ "SET $src,$dst" %}
0N/A ins_encode( Set32(src, dst) );
0N/A ins_pipe(ialu_hi_lo_reg);
0N/Ainstruct loadConI13( iRegI dst, immI13 src ) %{
0N/A format %{ "MOV $src,$dst" %}
0N/A ins_encode( Set13( src, dst ) );
1915N/Ainstruct loadConP(iRegP dst, immP con) %{
1915N/A ins_cost(DEFAULT_COST * 3/2);
1915N/A format %{ "SET $con,$dst\t!ptr" %}
1915N/A // [RGV] This next line should be generated from ADLC
1915N/A if (_opnds[1]->constant_is_oop()) {
1915N/A intptr_t val = $con$$constant;
1915N/A __ set_oop_constant((jobject) val, $dst$$Register);
1915N/A } else { // non-oop pointers,
e.g. card mark base, heap top
1915N/A __ set($con$$constant, $dst$$Register);
1915N/Ainstruct loadConP_set(iRegP dst, immP_set con) %{
0N/A ins_cost(DEFAULT_COST * 3/2);
1915N/A format %{ "SET $con,$dst\t! ptr" %}
1915N/A // [RGV] This next line should be generated from ADLC
1915N/A if (_opnds[1]->constant_is_oop()) {
1915N/A intptr_t val = $con$$constant;
1915N/A __ set_oop_constant((jobject) val, $dst$$Register);
1915N/A } else { // non-oop pointers,
e.g. card mark base, heap top
1915N/A __ set($con$$constant, $dst$$Register);
1915N/Ainstruct loadConP_load(iRegP dst, immP_load con) %{
1915N/A format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
1964N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
1964N/A __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
1964N/Ainstruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
1964N/A ins_cost(DEFAULT_COST * 3/2);
1964N/A format %{ "SET $con,$dst\t! non-oop ptr" %}
1964N/A __ set($con$$constant, $dst$$Register);
0N/Ainstruct loadConP0(iRegP dst, immP0 src) %{
0N/A format %{ "CLR $dst\t!ptr" %}
0N/Ainstruct loadConP_poll(iRegP dst, immP_poll src) %{
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "SET $src,$dst\t!ptr" %}
727N/A AddressLiteral polling_page(os::get_polling_page());
727N/A __ sethi(polling_page, reg_to_register_object($dst$$reg));
0N/A ins_pipe(loadConP_poll);
164N/Ainstruct loadConN0(iRegN dst, immN0 src) %{
164N/A format %{ "CLR $dst\t! compressed NULL ptr" %}
113N/Ainstruct loadConN(iRegN dst, immN src) %{
164N/A ins_cost(DEFAULT_COST * 3/2);
164N/A format %{ "SET $src,$dst\t! compressed ptr" %}
113N/A Register dst = $dst$$Register;
164N/A __ set_narrow_oop((jobject)$src$$constant, dst);
164N/A ins_pipe(ialu_hi_lo_reg);
1915N/A// Materialize long value (predicated by immL_cheap).
1915N/Ainstruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
1915N/A ins_cost(DEFAULT_COST * 3);
1915N/A format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
1915N/A __ set64($con$$constant, $dst$$Register, $tmp$$Register);
1915N/A// Load long value from constant table (predicated by immL_expensive).
1915N/Ainstruct loadConL_ldx(iRegL dst, immL_expensive con) %{
1915N/A format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
1919N/A __ ldx($constanttablebase, con_offset, $dst$$Register);
0N/Ainstruct loadConL0( iRegL dst, immL0 src ) %{
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "CLR $dst\t! long" %}
0N/A ins_encode( Set13( src, dst ) );
0N/Ainstruct loadConL13( iRegL dst, immL13 src ) %{
0N/A ins_cost(DEFAULT_COST * 2);
0N/A format %{ "MOV $src,$dst\t! long" %}
0N/A ins_encode( Set13( src, dst ) );
1919N/Ainstruct loadConF(regF dst, immF con, o7RegI tmp) %{
1915N/A format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
0N/A ins_pipe(loadConFD);
1919N/Ainstruct loadConD(regD dst, immD con, o7RegI tmp) %{
1915N/A format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
732N/A // XXX This is a quick fix for 6833573.
1915N/A //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(loadConFD);
0N/A// Prefetch instructions.
0N/A// Must be safe to execute with invalid address (cannot fault).
0N/Ainstruct prefetchr( memory mem ) %{
0N/A match( PrefetchRead mem );
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
0N/A opcode(Assembler::prefetch_op3);
0N/A ins_encode( form3_mem_prefetch_read( mem ) );
0N/A ins_pipe(iload_mem);
0N/Ainstruct prefetchw( memory mem ) %{
0N/A match( PrefetchWrite mem );
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
0N/A opcode(Assembler::prefetch_op3);
0N/A ins_encode( form3_mem_prefetch_write( mem ) );
0N/A ins_pipe(iload_mem);
2679N/A// Prefetch instructions for allocation.
2679N/Ainstruct prefetchAlloc( memory mem ) %{
2679N/A predicate(AllocatePrefetchInstr == 0);
2679N/A match( PrefetchAllocation mem );
2679N/A format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
2679N/A opcode(Assembler::prefetch_op3);
2679N/A ins_encode( form3_mem_prefetch_write( mem ) );
2679N/A// Use BIS instruction to prefetch for allocation.
2679N/A// Could fault, need space at the end of TLAB.
2679N/Ainstruct prefetchAlloc_bis( iRegP dst ) %{
2679N/A predicate(AllocatePrefetchInstr == 1);
2679N/A match( PrefetchAllocation dst );
2679N/A format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
2679N/A __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
2679N/A// Next code is used for finding next cache line address to prefetch.
2679N/Ainstruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
2679N/A match(Set dst (CastX2P (AndI (CastP2X src) mask)));
2679N/A format %{ "AND $src,$mask,$dst\t! next cache line address" %}
2679N/A __ and3($src$$Register, $mask$$constant, $dst$$Register);
2679N/Ainstruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
2679N/A match(Set dst (CastX2P (AndL (CastP2X src) mask)));
2679N/A format %{ "AND $src,$mask,$dst\t! next cache line address" %}
2679N/A __ and3($src$$Register, $mask$$constant, $dst$$Register);
0N/A//----------Store Instructions-------------------------------------------------
0N/Ainstruct storeB(memory mem, iRegI src) %{
0N/A match(Set mem (StoreB mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STB $src,$mem\t! byte" %}
0N/A opcode(Assembler::stb_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/Ainstruct storeB0(memory mem, immI0 src) %{
0N/A match(Set mem (StoreB mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STB $src,$mem\t! byte" %}
0N/A opcode(Assembler::stb_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
0N/Ainstruct storeCM0(memory mem, immI0 src) %{
0N/A match(Set mem (StoreCM mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
0N/A opcode(Assembler::stb_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
0N/Ainstruct storeC(memory mem, iRegI src) %{
0N/A match(Set mem (StoreC mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STH $src,$mem\t! short" %}
0N/A opcode(Assembler::sth_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/Ainstruct storeC0(memory mem, immI0 src) %{
0N/A match(Set mem (StoreC mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STH $src,$mem\t! short" %}
0N/A opcode(Assembler::sth_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
0N/Ainstruct storeI(memory mem, iRegI src) %{
0N/A match(Set mem (StoreI mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$mem" %}
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/Ainstruct storeL(memory mem, iRegL src) %{
0N/A match(Set mem (StoreL mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$mem\t! long" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/Ainstruct storeI0(memory mem, immI0 src) %{
0N/A match(Set mem (StoreI mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$mem" %}
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
0N/Ainstruct storeL0(memory mem, immL0 src) %{
0N/A match(Set mem (StoreL mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$mem" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
0N/A// Store Integer from float register (used after fstoi)
0N/Ainstruct storeI_Freg(memory mem, regF src) %{
0N/A match(Set mem (StoreI mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A opcode(Assembler::stf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreF_mem_reg);
0N/Ainstruct storeP(memory dst, sp_ptr_RegP src) %{
0N/A match(Set dst (StoreP dst src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$dst\t! ptr" %}
0N/A opcode(Assembler::stw_op3, 0, REGP_OP);
0N/A format %{ "STX $src,$dst\t! ptr" %}
0N/A opcode(Assembler::stx_op3, 0, REGP_OP);
0N/A ins_encode( form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_spORreg);
0N/Ainstruct storeP0(memory dst, immP0 src) %{
0N/A match(Set dst (StoreP dst src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$dst\t! ptr" %}
0N/A opcode(Assembler::stw_op3, 0, REGP_OP);
0N/A format %{ "STX $src,$dst\t! ptr" %}
0N/A opcode(Assembler::stx_op3, 0, REGP_OP);
0N/A ins_encode( form3_mem_reg( dst, R_G0 ) );
0N/A ins_pipe(istore_mem_zero);
113N/A// Store Compressed Pointer
113N/Ainstruct storeN(memory dst, iRegN src) %{
113N/A match(Set dst (StoreN dst src));
113N/A ins_cost(MEMORY_REF_COST);
113N/A format %{ "STW $src,$dst\t! compressed ptr" %}
113N/A Register base = as_Register($dst$$base);
113N/A Register index = as_Register($dst$$index);
113N/A Register src = $src$$Register;
113N/A __ stw(src, base, index);
113N/A __ stw(src, base, $dst$$disp);
113N/A ins_pipe(istore_mem_spORreg);
113N/Ainstruct storeN0(memory dst, immN0 src) %{
113N/A match(Set dst (StoreN dst src));
113N/A ins_cost(MEMORY_REF_COST);
113N/A format %{ "STW $src,$dst\t! compressed ptr" %}
113N/A Register base = as_Register($dst$$base);
113N/A Register index = as_Register($dst$$index);
113N/A __ stw(0, base, index);
113N/A __ stw(0, base, $dst$$disp);
113N/A ins_pipe(istore_mem_zero);
0N/Ainstruct storeD( memory mem, regD src) %{
0N/A match(Set mem (StoreD mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$mem" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreD_mem_reg);
0N/Ainstruct storeD0( memory mem, immD0 src) %{
0N/A match(Set mem (StoreD mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $src,$mem" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(fstoreD_mem_zero);
0N/Ainstruct storeF( memory mem, regF src) %{
0N/A match(Set mem (StoreF mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STF $src,$mem" %}
0N/A opcode(Assembler::stf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreF_mem_reg);
0N/Ainstruct storeF0( memory mem, immF0 src) %{
0N/A match(Set mem (StoreF mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STW $src,$mem\t! storeF0" %}
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(fstoreF_mem_zero);
0N/A// Store Aligned Packed Bytes in Double register to memory
0N/Ainstruct storeA8B(memory mem, regD src) %{
0N/A match(Set mem (Store8B mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$mem\t! packed8B" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreD_mem_reg);
113N/A// Convert oop pointer into compressed form
113N/Ainstruct encodeHeapOop(iRegN dst, iRegP src) %{
221N/A predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113N/A match(Set dst (EncodeP src));
124N/A format %{ "encode_heap_oop $src, $dst" %}
113N/A __ encode_heap_oop($src$$Register, $dst$$Register);
124N/Ainstruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
221N/A predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124N/A match(Set dst (EncodeP src));
124N/A format %{ "encode_heap_oop_not_null $src, $dst" %}
124N/A __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
113N/Ainstruct decodeHeapOop(iRegP dst, iRegN src) %{
182N/A predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
182N/A n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
113N/A match(Set dst (DecodeN src));
113N/A format %{ "decode_heap_oop $src, $dst" %}
113N/A __ decode_heap_oop($src$$Register, $dst$$Register);
124N/Ainstruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
182N/A predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
182N/A n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
124N/A match(Set dst (DecodeN src));
124N/A format %{ "decode_heap_oop_not_null $src, $dst" %}
124N/A __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
0N/A// Store Zero into Aligned Packed Bytes
0N/Ainstruct storeA8B0(memory mem, immI0 zero) %{
0N/A match(Set mem (Store8B mem zero));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $zero,$mem\t! packed8B" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(fstoreD_mem_zero);
0N/Ainstruct storeA4C(memory mem, regD src) %{
0N/A match(Set mem (Store4C mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$mem\t! packed4C" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreD_mem_reg);
0N/Ainstruct storeA4C0(memory mem, immI0 zero) %{
0N/A match(Set mem (Store4C mem (Replicate4C zero)));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $zero,$mem\t! packed4C" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(fstoreD_mem_zero);
0N/A// Store Aligned Packed Ints in Double register to memory
0N/Ainstruct storeA2I(memory mem, regD src) %{
0N/A match(Set mem (Store2I mem src));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$mem\t! packed2I" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, src ) );
0N/A ins_pipe(fstoreD_mem_reg);
0N/A// Store Zero into Aligned Packed Ints
0N/Ainstruct storeA2I0(memory mem, immI0 zero) %{
0N/A match(Set mem (Store2I mem zero));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STX $zero,$mem\t! packed2I" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0N/A ins_pipe(fstoreD_mem_zero);
0N/A//----------MemBar Instructions-----------------------------------------------
0N/A// Memory barrier flavors
0N/Ainstruct membar_acquire() %{
0N/A match(MemBarAcquire);
0N/A ins_cost(4*MEMORY_REF_COST);
0N/A format %{ "MEMBAR-acquire" %}
0N/A ins_encode( enc_membar_acquire );
0N/A ins_pipe(long_memory_op);
0N/Ainstruct membar_acquire_lock() %{
0N/A format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
0N/Ainstruct membar_release() %{
0N/A match(MemBarRelease);
0N/A ins_cost(4*MEMORY_REF_COST);
0N/A format %{ "MEMBAR-release" %}
0N/A ins_encode( enc_membar_release );
0N/A ins_pipe(long_memory_op);
0N/Ainstruct membar_release_lock() %{
0N/A format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
0N/Ainstruct membar_volatile() %{
0N/A match(MemBarVolatile);
0N/A ins_cost(4*MEMORY_REF_COST);
0N/A format %{ "MEMBAR-volatile" %}
0N/A ins_encode( enc_membar_volatile );
0N/A ins_pipe(long_memory_op);
0N/Ainstruct unnecessary_membar_volatile() %{
0N/A match(MemBarVolatile);
0N/A predicate(Matcher::post_store_load_barrier(n));
0N/A format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
3043N/Ainstruct membar_storestore() %{
3043N/A format %{ "!MEMBAR-storestore (empty encoding)" %}
0N/A//----------Register Move Instructions-----------------------------------------
0N/Ainstruct roundDouble_nop(regD dst) %{
0N/A match(Set dst (RoundDouble dst));
0N/A // SPARC results are already "rounded" (
i.e., normal-format IEEE)
0N/Ainstruct roundFloat_nop(regF dst) %{
0N/A match(Set dst (RoundFloat dst));
0N/A // SPARC results are already "rounded" (
i.e., normal-format IEEE)
0N/A// Cast Index to Pointer for unsafe natives
0N/Ainstruct castX2P(iRegX src, iRegP dst) %{
0N/A match(Set dst (CastX2P src));
0N/A format %{ "MOV $src,$dst\t! IntX->Ptr" %}
0N/A ins_encode( form3_g0_rs2_rd_move( src, dst ) );
0N/A// Cast Pointer to Index for unsafe natives
0N/Ainstruct castP2X(iRegP src, iRegX dst) %{
0N/A match(Set dst (CastP2X src));
0N/A format %{ "MOV $src,$dst\t! Ptr->IntX" %}
0N/A ins_encode( form3_g0_rs2_rd_move( src, dst ) );
0N/Ainstruct stfSSD(stackSlotD stkSlot, regD src) %{
0N/A // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
0N/A match(Set stkSlot src); // chain rule
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STDF $src,$stkSlot\t!stk" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg(stkSlot, src));
0N/A ins_pipe(fstoreD_stk_reg);
0N/Ainstruct ldfSSD(regD dst, stackSlotD stkSlot) %{
0N/A // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
0N/A match(Set dst stkSlot); // chain rule
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $stkSlot,$dst\t!stk" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg(stkSlot, dst));
0N/A ins_pipe(floadD_stk);
0N/Ainstruct stfSSF(stackSlotF stkSlot, regF src) %{
0N/A // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
0N/A match(Set stkSlot src); // chain rule
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STF $src,$stkSlot\t!stk" %}
0N/A opcode(Assembler::stf_op3);
415N/A ins_encode(simple_form3_mem_reg(stkSlot, src));
0N/A ins_pipe(fstoreF_stk_reg);
0N/A//----------Conditional Move---------------------------------------------------
0N/Ainstruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
0N/A match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
0N/Ainstruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
0N/A match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
0N/Ainstruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
0N/A match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
0N/Ainstruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
0N/A match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
1160N/Ainstruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
0N/A match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1160N/Ainstruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
0N/A match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
0N/Ainstruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
0N/A match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
0N/Ainstruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
0N/A match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
164N/A// Conditional move for RegN. Only cmov(reg,reg).
164N/Ainstruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
164N/A match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
164N/A format %{ "MOV$cmp $pcc,$src,$dst" %}
164N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
164N/A// This instruction also works with CmpN so we don't need cmovNN_reg.
164N/Ainstruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
164N/A match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
164N/A format %{ "MOV$cmp $icc,$src,$dst" %}
164N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1160N/A// This instruction also works with CmpN so we don't need cmovNN_reg.
1160N/Ainstruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
1160N/A match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "MOV$cmp $icc,$src,$dst" %}
1160N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
164N/Ainstruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
164N/A match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
164N/A format %{ "MOV$cmp $fcc,$src,$dst" %}
164N/A ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
0N/Ainstruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
0N/A match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
0N/Ainstruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
0N/A match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
164N/A// This instruction also works with CmpN so we don't need cmovPN_reg.
0N/Ainstruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
0N/A match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1160N/Ainstruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
1160N/A match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
1160N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
0N/Ainstruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
0N/A match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
1160N/Ainstruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
1160N/A match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
1160N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
0N/Ainstruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
0N/A match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
0N/Ainstruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
0N/A match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
0N/Ainstruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
0N/A match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "FMOVD$cmp $pcc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
0N/A ins_pipe(int_conditional_float_move);
0N/Ainstruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
0N/A match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
0N/A format %{ "FMOVS$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
0N/A ins_pipe(int_conditional_float_move);
1160N/Ainstruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
1160N/A match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "FMOVS$cmp $icc,$src,$dst" %}
1160N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
1160N/A ins_pipe(int_conditional_float_move);
0N/Ainstruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
0N/A match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "FMOVF$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
0N/A ins_pipe(int_conditional_double_move);
0N/Ainstruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
0N/A match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "FMOVD$cmp $pcc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
0N/A ins_pipe(int_conditional_double_move);
0N/Ainstruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
0N/A match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
0N/A format %{ "FMOVD$cmp $icc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
0N/A ins_pipe(int_conditional_double_move);
1160N/Ainstruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
1160N/A match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "FMOVD$cmp $icc,$src,$dst" %}
1160N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
1160N/A ins_pipe(int_conditional_double_move);
0N/Ainstruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
0N/A match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "FMOVD$cmp $fcc,$src,$dst" %}
0N/A ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
0N/A ins_pipe(int_conditional_double_move);
0N/Ainstruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
0N/A match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
0N/Ainstruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
0N/A match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
0N/Ainstruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
0N/A match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
0N/A format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1160N/Ainstruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
1160N/A match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
1160N/A format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
1160N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
0N/Ainstruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
0N/A match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
0N/A//----------OS and Locking Instructions----------------------------------------
0N/A// This name is KNOWN by the ADLC and cannot be changed.
0N/A// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
0N/Ainstruct tlsLoadP(g2RegP dst) %{
0N/A match(Set dst (ThreadLocal));
0N/A format %{ "# TLS is in G2" %}
0N/A ins_encode( /*empty encoding*/ );
0N/A ins_pipe(ialu_none);
0N/Ainstruct checkCastPP( iRegP dst ) %{
0N/A match(Set dst (CheckCastPP dst));
0N/A format %{ "# checkcastPP of $dst" %}
0N/A ins_encode( /*empty encoding*/ );
0N/Ainstruct castPP( iRegP dst ) %{
0N/A match(Set dst (CastPP dst));
0N/A format %{ "# castPP of $dst" %}
0N/A ins_encode( /*empty encoding*/ );
0N/Ainstruct castII( iRegI dst ) %{
0N/A match(Set dst (CastII dst));
0N/A format %{ "# castII of $dst" %}
0N/A ins_encode( /*empty encoding*/ );
0N/A//----------Arithmetic Instructions--------------------------------------------
0N/A// Addition Instructions
0N/Ainstruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (AddI src1 src2));
0N/A format %{ "ADD $src1,$src2,$dst" %}
0N/A __ add($src1$$Register, $src2$$Register, $dst$$Register);
0N/A ins_pipe(ialu_reg_reg);
0N/A// Immediate Addition
0N/Ainstruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (AddI src1 src2));
0N/A format %{ "ADD $src1,$src2,$dst" %}
0N/A opcode(Assembler::add_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Pointer Register Addition
0N/Ainstruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
0N/A match(Set dst (AddP src1 src2));
0N/A format %{ "ADD $src1,$src2,$dst" %}
0N/A opcode(Assembler::add_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Pointer Immediate Addition
0N/Ainstruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
0N/A match(Set dst (AddP src1 src2));
0N/A format %{ "ADD $src1,$src2,$dst" %}
0N/A opcode(Assembler::add_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (AddL src1 src2));
0N/A format %{ "ADD $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::add_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
0N/A match(Set dst (AddL src1 con));
0N/A format %{ "ADD $src1,$con,$dst" %}
0N/A opcode(Assembler::add_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A//----------Conditional_store--------------------------------------------------
0N/A// Conditional-store of the updated heap-top.
0N/A// Used during allocation of the shared heap.
0N/A// Sets flags (EQ) on success. Implemented with a CASA on Sparc.
0N/A// LoadP-locked. Same as a regular pointer load when used with a compare-swap
0N/Ainstruct loadPLocked(iRegP dst, memory mem) %{
0N/A match(Set dst (LoadPLocked mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $mem,$dst\t! ptr" %}
0N/A opcode(Assembler::lduw_op3, 0, REGP_OP);
0N/A format %{ "LDX $mem,$dst\t! ptr" %}
0N/A opcode(Assembler::ldx_op3, 0, REGP_OP);
0N/A ins_encode( form3_mem_reg( mem, dst ) );
0N/A ins_pipe(iload_mem);
0N/A// LoadL-locked. Same as a regular long load when used with a compare-swap
0N/Ainstruct loadLLocked(iRegL dst, memory mem) %{
0N/A match(Set dst (LoadLLocked mem));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDX $mem,$dst\t! long" %}
0N/A opcode(Assembler::ldx_op3);
415N/A ins_encode(simple_form3_mem_reg( mem, dst ) );
0N/A ins_pipe(iload_mem);
0N/Ainstruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
0N/A match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
0N/A effect( KILL newval );
0N/A format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
0N/A "CMP R_G3,$oldval\t\t! See if we made progress" %}
0N/A ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
0N/A ins_pipe( long_memory_op );
420N/A// Conditional-store of an int value.
420N/Ainstruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
420N/A match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
420N/A format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
420N/A "CMP $oldval,$newval\t\t! See if we made progress" %}
420N/A ins_encode( enc_cas(mem_ptr,oldval,newval) );
0N/A ins_pipe( long_memory_op );
420N/A// Conditional-store of a long value.
420N/Ainstruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
420N/A match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
420N/A format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
420N/A "CMP $oldval,$newval\t\t! See if we made progress" %}
420N/A ins_encode( enc_cas(mem_ptr,oldval,newval) );
0N/A ins_pipe( long_memory_op );
0N/A// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
0N/Ainstruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
0N/A match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
0N/A effect( USE mem_ptr, KILL ccr, KILL tmp1);
0N/A "MOV $newval,O7\n\t"
0N/A "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
0N/A "CMP $oldval,O7\t\t! See if we made progress\n\t"
0N/A "MOVne xcc,R_G0,$res"
0N/A ins_encode( enc_casx(mem_ptr, oldval, newval),
0N/A enc_lflags_ne_to_boolean(res) );
0N/A ins_pipe( long_memory_op );
0N/Ainstruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
0N/A match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
0N/A effect( USE mem_ptr, KILL ccr, KILL tmp1);
0N/A "MOV $newval,O7\n\t"
0N/A "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
0N/A "CMP $oldval,O7\t\t! See if we made progress\n\t"
0N/A "MOVne icc,R_G0,$res"
0N/A ins_encode( enc_casi(mem_ptr, oldval, newval),
0N/A enc_iflags_ne_to_boolean(res) );
0N/A ins_pipe( long_memory_op );
0N/Ainstruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
0N/A match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
0N/A effect( USE mem_ptr, KILL ccr, KILL tmp1);
0N/A "MOV $newval,O7\n\t"
113N/A "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
0N/A "CMP $oldval,O7\t\t! See if we made progress\n\t"
0N/A "MOVne xcc,R_G0,$res"
0N/A ins_encode( enc_casx(mem_ptr, oldval, newval),
0N/A enc_lflags_ne_to_boolean(res) );
113N/A ins_encode( enc_casi(mem_ptr, oldval, newval),
113N/A enc_iflags_ne_to_boolean(res) );
113N/A ins_pipe( long_memory_op );
181N/Ainstruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
113N/A match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
181N/A effect( USE mem_ptr, KILL ccr, KILL tmp1);
0N/A "MOV $newval,O7\n\t"
0N/A "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
0N/A "CMP $oldval,O7\t\t! See if we made progress\n\t"
0N/A "MOVne icc,R_G0,$res"
181N/A ins_encode( enc_casi(mem_ptr, oldval, newval),
181N/A enc_iflags_ne_to_boolean(res) );
0N/A ins_pipe( long_memory_op );
0N/A//---------------------
0N/A// Subtraction Instructions
0N/A// Register Subtraction
0N/Ainstruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (SubI src1 src2));
0N/A format %{ "SUB $src1,$src2,$dst" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Immediate Subtraction
0N/Ainstruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (SubI src1 src2));
0N/A format %{ "SUB $src1,$src2,$dst" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
0N/A match(Set dst (SubI zero src2));
0N/A format %{ "NEG $src2,$dst" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
0N/A ins_pipe(ialu_zero_reg);
0N/Ainstruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (SubL src1 src2));
0N/A format %{ "SUB $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Immediate Subtraction
0N/Ainstruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
0N/A match(Set dst (SubL src1 con));
0N/A format %{ "SUB $src1,$con,$dst\t! long" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
0N/A match(Set dst (SubL zero src2));
0N/A format %{ "NEG $src2,$dst\t! long" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
0N/A ins_pipe(ialu_zero_reg);
0N/A// Multiplication Instructions
0N/A// Integer Multiplication
0N/A// Register Multiplication
0N/Ainstruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (MulI src1 src2));
0N/A format %{ "MULX $src1,$src2,$dst" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(imul_reg_reg);
0N/A// Immediate Multiplication
0N/Ainstruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (MulI src1 src2));
0N/A format %{ "MULX $src1,$src2,$dst" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(imul_reg_imm);
0N/Ainstruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (MulL src1 src2));
0N/A ins_cost(DEFAULT_COST * 5);
0N/A format %{ "MULX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(mulL_reg_reg);
0N/A// Immediate Multiplication
0N/Ainstruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
0N/A match(Set dst (MulL src1 src2));
0N/A ins_cost(DEFAULT_COST * 5);
0N/A format %{ "MULX $src1,$src2,$dst" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(mulL_reg_imm);
0N/Ainstruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
0N/A match(Set dst (DivI src1 src2));
0N/A ins_cost((2+71)*DEFAULT_COST);
0N/A format %{ "SRA $src2,0,$src2\n\t"
0N/A "SRA $src1,0,$src1\n\t"
0N/A "SDIVX $src1,$src2,$dst" %}
0N/A ins_encode( idiv_reg( src1, src2, dst ) );
0N/A ins_pipe(sdiv_reg_reg);
0N/A// Immediate Division
0N/Ainstruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
0N/A match(Set dst (DivI src1 src2));
0N/A ins_cost((2+71)*DEFAULT_COST);
0N/A format %{ "SRA $src1,0,$src1\n\t"
0N/A "SDIVX $src1,$src2,$dst" %}
0N/A ins_encode( idiv_imm( src1, src2, dst ) );
0N/A ins_pipe(sdiv_reg_imm);
0N/A//----------Div-By-10-Expansion------------------------------------------------
0N/A// Extract hi bits of a 32x32->64 bit multiply.
0N/A// Expand rule only, not matched
0N/Ainstruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
0N/A effect( DEF dst, USE src1, USE src2 );
0N/A format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
0N/A "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
0N/A ins_encode( enc_mul_hi(dst,src1,src2));
0N/A ins_pipe(sdiv_reg_reg);
605N/A// Magic constant, reciprocal of 10
0N/Ainstruct loadConI_x66666667(iRegIsafe dst) %{
0N/A format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
0N/A ins_encode( Set32(0x66666667, dst) );
0N/A ins_pipe(ialu_hi_lo_reg);
605N/A// Register Shift Right Arithmetic Long by 32-63
0N/Ainstruct sra_31( iRegI dst, iRegI src ) %{
0N/A effect( DEF dst, USE src );
0N/A format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
0N/A ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Arithmetic Shift Right by 8-bit immediate
0N/Ainstruct sra_reg_2( iRegI dst, iRegI src ) %{
0N/A effect( DEF dst, USE src );
0N/A format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
0N/A opcode(Assembler::sra_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Integer DIV with 10
0N/Ainstruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
0N/A match(Set dst (DivI src div));
0N/A ins_cost((6+6)*DEFAULT_COST);
0N/A iRegIsafe tmp1; // Killed temps;
0N/A iRegIsafe tmp2; // Killed temps;
0N/A iRegI tmp3; // Killed temps;
0N/A iRegI tmp4; // Killed temps;
0N/A loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
0N/A mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
0N/A sra_31( tmp3, src ); // SRA src,31 -> tmp3
0N/A sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
0N/A subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
0N/A// Register Long Division
0N/Ainstruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (DivL src1 src2));
0N/A ins_cost(DEFAULT_COST*71);
0N/A format %{ "SDIVX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sdivx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(divL_reg_reg);
0N/A// Register Long Division
0N/Ainstruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
0N/A match(Set dst (DivL src1 src2));
0N/A ins_cost(DEFAULT_COST*71);
0N/A format %{ "SDIVX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sdivx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(divL_reg_imm);
0N/A// Register Remainder
0N/Ainstruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
0N/A match(Set dst (ModI src1 src2));
0N/A effect( KILL ccr, KILL temp);
0N/A format %{ "SREM $src1,$src2,$dst" %}
0N/A ins_encode( irem_reg(src1, src2, dst, temp) );
0N/A ins_pipe(sdiv_reg_reg);
0N/A// Immediate Remainder
0N/Ainstruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
0N/A match(Set dst (ModI src1 src2));
0N/A effect( KILL ccr, KILL temp);
0N/A format %{ "SREM $src1,$src2,$dst" %}
0N/A ins_encode( irem_imm(src1, src2, dst, temp) );
0N/A ins_pipe(sdiv_reg_imm);
0N/A// Register Long Remainder
0N/Ainstruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "SDIVX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sdivx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(divL_reg_reg);
0N/A// Register Long Division
0N/Ainstruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "SDIVX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sdivx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(divL_reg_imm);
0N/Ainstruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "MULX $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(mulL_reg_reg);
0N/A// Immediate Multiplication
0N/Ainstruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "MULX $src1,$src2,$dst" %}
0N/A opcode(Assembler::mulx_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(mulL_reg_imm);
0N/Ainstruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "SUB $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "SUB $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::sub_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Long Remainder
0N/Ainstruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (ModL src1 src2));
0N/A ins_cost(DEFAULT_COST*(71 + 6 + 1));
0N/A divL_reg_reg_1(tmp1, src1, src2);
0N/A mulL_reg_reg_1(tmp2, tmp1, src2);
0N/A subL_reg_reg_1(dst, src1, tmp2);
0N/A// Register Long Remainder
0N/Ainstruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
0N/A match(Set dst (ModL src1 src2));
0N/A ins_cost(DEFAULT_COST*(71 + 6 + 1));
0N/A divL_reg_imm13_1(tmp1, src1, src2);
0N/A mulL_reg_imm13_1(tmp2, tmp1, src2);
0N/A subL_reg_reg_2 (dst, src1, tmp2);
0N/A// Integer Shift Instructions
0N/A// Register Shift Left
0N/Ainstruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (LShiftI src1 src2));
0N/A format %{ "SLL $src1,$src2,$dst" %}
0N/A opcode(Assembler::sll_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Shift Left Immediate
0N/Ainstruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
0N/A match(Set dst (LShiftI src1 src2));
0N/A format %{ "SLL $src1,$src2,$dst" %}
0N/A opcode(Assembler::sll_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Shift Left
0N/Ainstruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
0N/A match(Set dst (LShiftL src1 src2));
0N/A format %{ "SLLX $src1,$src2,$dst" %}
0N/A opcode(Assembler::sllx_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Shift Left Immediate
0N/Ainstruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
0N/A match(Set dst (LShiftL src1 src2));
0N/A format %{ "SLLX $src1,$src2,$dst" %}
0N/A opcode(Assembler::sllx_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Arithmetic Shift Right
0N/Ainstruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (RShiftI src1 src2));
0N/A format %{ "SRA $src1,$src2,$dst" %}
0N/A opcode(Assembler::sra_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Arithmetic Shift Right Immediate
0N/Ainstruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
0N/A match(Set dst (RShiftI src1 src2));
0N/A format %{ "SRA $src1,$src2,$dst" %}
0N/A opcode(Assembler::sra_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Shift Right Arithmatic Long
0N/Ainstruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
0N/A match(Set dst (RShiftL src1 src2));
0N/A format %{ "SRAX $src1,$src2,$dst" %}
0N/A opcode(Assembler::srax_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Shift Left Immediate
0N/Ainstruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
0N/A match(Set dst (RShiftL src1 src2));
0N/A format %{ "SRAX $src1,$src2,$dst" %}
0N/A opcode(Assembler::srax_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Shift Right
0N/Ainstruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (URShiftI src1 src2));
0N/A format %{ "SRL $src1,$src2,$dst" %}
0N/A opcode(Assembler::srl_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Shift Right Immediate
0N/Ainstruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
0N/A match(Set dst (URShiftI src1 src2));
0N/A format %{ "SRL $src1,$src2,$dst" %}
0N/A opcode(Assembler::srl_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Shift Right
0N/Ainstruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
0N/A match(Set dst (URShiftL src1 src2));
0N/A format %{ "SRLX $src1,$src2,$dst" %}
0N/A opcode(Assembler::srlx_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/A// Register Shift Right Immediate
0N/Ainstruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
0N/A match(Set dst (URShiftL src1 src2));
0N/A format %{ "SRLX $src1,$src2,$dst" %}
0N/A opcode(Assembler::srlx_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Register Shift Right Immediate with a CastP2X
0N/Ainstruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
0N/A match(Set dst (URShiftL (CastP2X src1) src2));
0N/A format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
0N/A opcode(Assembler::srlx_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
0N/A match(Set dst (URShiftI (CastP2X src1) src2));
0N/A format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
0N/A opcode(Assembler::srl_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A//----------Floating Point Arithmetic Instructions-----------------------------
0N/A// Add float single precision
0N/Ainstruct addF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A match(Set dst (AddF src1 src2));
0N/A format %{ "FADDS $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
0N/A ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
0N/A ins_pipe(faddF_reg_reg);
0N/A// Add float double precision
0N/Ainstruct addD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A match(Set dst (AddD src1 src2));
0N/A format %{ "FADDD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(faddD_reg_reg);
0N/A// Sub float single precision
0N/Ainstruct subF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A match(Set dst (SubF src1 src2));
0N/A format %{ "FSUBS $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
0N/A ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
0N/A ins_pipe(faddF_reg_reg);
0N/A// Sub float double precision
0N/Ainstruct subD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A match(Set dst (SubD src1 src2));
0N/A format %{ "FSUBD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(faddD_reg_reg);
0N/A// Mul float single precision
0N/Ainstruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A match(Set dst (MulF src1 src2));
0N/A format %{ "FMULS $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
0N/A ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
0N/A ins_pipe(fmulF_reg_reg);
0N/A// Mul float double precision
0N/Ainstruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A match(Set dst (MulD src1 src2));
0N/A format %{ "FMULD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(fmulD_reg_reg);
0N/A// Div float single precision
0N/Ainstruct divF_reg_reg(regF dst, regF src1, regF src2) %{
0N/A match(Set dst (DivF src1 src2));
0N/A format %{ "FDIVS $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
0N/A ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
0N/A ins_pipe(fdivF_reg_reg);
0N/A// Div float double precision
0N/Ainstruct divD_reg_reg(regD dst, regD src1, regD src2) %{
0N/A match(Set dst (DivD src1 src2));
0N/A format %{ "FDIVD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(fdivD_reg_reg);
0N/A// Absolute float double precision
0N/Ainstruct absD_reg(regD dst, regD src) %{
0N/A match(Set dst (AbsD src));
0N/A format %{ "FABSd $src,$dst" %}
0N/A ins_encode(fabsd(dst, src));
0N/A ins_pipe(faddD_reg);
0N/A// Absolute float single precision
0N/Ainstruct absF_reg(regF dst, regF src) %{
0N/A match(Set dst (AbsF src));
0N/A format %{ "FABSs $src,$dst" %}
0N/A ins_encode(fabss(dst, src));
0N/A ins_pipe(faddF_reg);
0N/Ainstruct negF_reg(regF dst, regF src) %{
0N/A match(Set dst (NegF src));
0N/A format %{ "FNEGs $src,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
0N/A ins_encode(form3_opf_rs2F_rdF(src, dst));
0N/A ins_pipe(faddF_reg);
0N/Ainstruct negD_reg(regD dst, regD src) %{
0N/A match(Set dst (NegD src));
0N/A format %{ "FNEGd $src,$dst" %}
0N/A ins_encode(fnegd(dst, src));
0N/A ins_pipe(faddD_reg);
0N/A// Sqrt float double precision
0N/Ainstruct sqrtF_reg_reg(regF dst, regF src) %{
0N/A match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
0N/A format %{ "FSQRTS $src,$dst" %}
0N/A ins_encode(fsqrts(dst, src));
0N/A ins_pipe(fdivF_reg_reg);
0N/A// Sqrt float double precision
0N/Ainstruct sqrtD_reg_reg(regD dst, regD src) %{
0N/A match(Set dst (SqrtD src));
0N/A format %{ "FSQRTD $src,$dst" %}
0N/A ins_encode(fsqrtd(dst, src));
0N/A ins_pipe(fdivD_reg_reg);
0N/A//----------Logical Instructions-----------------------------------------------
0N/Ainstruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (AndI src1 src2));
0N/A format %{ "AND $src1,$src2,$dst" %}
0N/A opcode(Assembler::and_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (AndI src1 src2));
0N/A format %{ "AND $src1,$src2,$dst" %}
0N/A opcode(Assembler::and_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (AndL src1 src2));
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "AND $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::and_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
0N/A match(Set dst (AndL src1 con));
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "AND $src1,$con,$dst\t! long" %}
0N/A opcode(Assembler::and_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (OrI src1 src2));
0N/A format %{ "OR $src1,$src2,$dst" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (OrI src1 src2));
0N/A format %{ "OR $src1,$src2,$dst" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (OrL src1 src2));
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "OR $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
0N/A match(Set dst (OrL src1 con));
0N/A ins_cost(DEFAULT_COST*2);
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "OR $src1,$con,$dst\t! long" %}
0N/A opcode(Assembler::or_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
0N/A ins_pipe(ialu_reg_imm);
420N/A// Use sp_ptr_RegP to match G2 (TLS register) without spilling.
420N/Ainstruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
420N/A match(Set dst (OrI src1 (CastP2X src2)));
420N/A format %{ "OR $src1,$src2,$dst" %}
420N/A opcode(Assembler::or_op3, Assembler::arith_op);
420N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
420N/A ins_pipe(ialu_reg_reg);
420N/Ainstruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
420N/A match(Set dst (OrL src1 (CastP2X src2)));
420N/A ins_cost(DEFAULT_COST);
420N/A format %{ "OR $src1,$src2,$dst\t! long" %}
420N/A opcode(Assembler::or_op3, Assembler::arith_op);
420N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
420N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
0N/A match(Set dst (XorI src1 src2));
0N/A format %{ "XOR $src1,$src2,$dst" %}
0N/A opcode(Assembler::xor_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
0N/A match(Set dst (XorI src1 src2));
0N/A format %{ "XOR $src1,$src2,$dst" %}
0N/A opcode(Assembler::xor_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/Ainstruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
0N/A match(Set dst (XorL src1 src2));
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "XOR $src1,$src2,$dst\t! long" %}
0N/A opcode(Assembler::xor_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
0N/A ins_pipe(ialu_reg_reg);
0N/Ainstruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
0N/A match(Set dst (XorL src1 con));
0N/A ins_cost(DEFAULT_COST);
0N/A format %{ "XOR $src1,$con,$dst\t! long" %}
0N/A opcode(Assembler::xor_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A//----------Convert to Boolean-------------------------------------------------
0N/A// Nice hack for 32-bit tests but doesn't work for
0N/Ainstruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
0N/A match(Set dst (Conv2B src));
0N/A ins_cost(DEFAULT_COST*2);
0N/A format %{ "CMP R_G0,$src\n\t"
0N/A "ADDX R_G0,0,$dst" %}
0N/A ins_encode( enc_to_bool( src, dst ) );
0N/A ins_pipe(ialu_reg_ialu);
0N/Ainstruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
0N/A match(Set dst (Conv2B src));
0N/A ins_cost(DEFAULT_COST*2);
0N/A format %{ "CMP R_G0,$src\n\t"
0N/A "ADDX R_G0,0,$dst" %}
0N/A ins_encode( enc_to_bool( src, dst ) );
0N/A ins_pipe(ialu_reg_ialu);
0N/Ainstruct convP2B( iRegI dst, iRegP src ) %{
0N/A match(Set dst (Conv2B src));
0N/A ins_cost(DEFAULT_COST*2);
0N/A format %{ "MOV $src,$dst\n\t"
0N/A "MOVRNZ $src,1,$dst" %}
0N/A ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
0N/A ins_pipe(ialu_clr_and_mover);
2126N/Ainstruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
2126N/A match(Set dst (CmpLTMask src zero));
2126N/A format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
2126N/A __ sra($src$$Register, 31, $dst$$Register);
0N/Ainstruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
0N/A match(Set dst (CmpLTMask p q));
0N/A ins_cost(DEFAULT_COST*4);
0N/A format %{ "CMP $p,$q\n\t"
0N/A ins_encode( enc_ltmask(p,q,dst) );
0N/A ins_pipe(ialu_reg_reg_ialu);
0N/Ainstruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
0N/A match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
0N/A effect(KILL ccr, TEMP tmp);
0N/A ins_cost(DEFAULT_COST*3);
0N/A format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
0N/A "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
2126N/A "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
0N/A ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
0N/A ins_pipe( cadd_cmpltmask );
2629N/A//-----------------------------------------------------------------
2629N/A// Direct raw moves between float and general registers using VIS3.
2629N/Ainstruct MoveF2I_reg_reg(iRegI dst, regF src) %{
2629N/A match(Set dst (MoveF2I src));
2629N/A format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
2629N/A __ movstouw($src$$FloatRegister, $dst$$Register);
2629N/Ainstruct MoveI2F_reg_reg(regF dst, iRegI src) %{
2629N/A match(Set dst (MoveI2F src));
2629N/A format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
2629N/A __ movwtos($src$$Register, $dst$$FloatRegister);
0N/A ins_pipe(ialu_reg_reg);
2629N/Ainstruct MoveD2L_reg_reg(iRegL dst, regD src) %{
2629N/A match(Set dst (MoveD2L src));
2629N/A format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
2629N/A __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
0N/A ins_pipe(ialu_reg_reg);
2629N/Ainstruct MoveL2D_reg_reg(regD dst, iRegL src) %{
2629N/A match(Set dst (MoveL2D src));
2629N/A format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
2629N/A __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(ialu_reg_reg);
2629N/A// Raw moves between float and general registers using stack.
0N/Ainstruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
0N/A match(Set dst (MoveF2I src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDUW $src,$dst\t! MoveF2I" %}
0N/A opcode(Assembler::lduw_op3);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/Ainstruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
0N/A match(Set dst (MoveI2F src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDF $src,$dst\t! MoveI2F" %}
0N/A opcode(Assembler::ldf_op3);
415N/A ins_encode(simple_form3_mem_reg(src, dst));
0N/A ins_pipe(floadF_stk);
0N/Ainstruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
0N/A match(Set dst (MoveD2L src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDX $src,$dst\t! MoveD2L" %}
0N/A opcode(Assembler::ldx_op3);
415N/A ins_encode(simple_form3_mem_reg( src, dst ) );
0N/A ins_pipe(iload_mem);
0N/Ainstruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "LDDF $src,$dst\t! MoveL2D" %}
0N/A opcode(Assembler::lddf_op3);
415N/A ins_encode(simple_form3_mem_reg(src, dst));
0N/A ins_pipe(floadD_stk);
0N/Ainstruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
0N/A match(Set dst (MoveF2I src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
2629N/A format %{ "STF $src,$dst\t! MoveF2I" %}
0N/A opcode(Assembler::stf_op3);
415N/A ins_encode(simple_form3_mem_reg(dst, src));
0N/A ins_pipe(fstoreF_stk_reg);
0N/Ainstruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
0N/A match(Set dst (MoveI2F src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
2629N/A format %{ "STW $src,$dst\t! MoveI2F" %}
0N/A opcode(Assembler::stw_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
0N/Ainstruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
0N/A match(Set dst (MoveD2L src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
2629N/A format %{ "STDF $src,$dst\t! MoveD2L" %}
0N/A opcode(Assembler::stdf_op3);
415N/A ins_encode(simple_form3_mem_reg(dst, src));
0N/A ins_pipe(fstoreD_stk_reg);
0N/Ainstruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
0N/A match(Set dst (MoveL2D src));
0N/A effect(DEF dst, USE src);
0N/A ins_cost(MEMORY_REF_COST);
2629N/A format %{ "STX $src,$dst\t! MoveL2D" %}
0N/A opcode(Assembler::stx_op3);
415N/A ins_encode(simple_form3_mem_reg( dst, src ) );
0N/A ins_pipe(istore_mem_reg);
2629N/A//----------Arithmetic Conversion Instructions---------------------------------
2629N/A// The conversions operations are all Alpha sorted. Please keep it that way!
2629N/Ainstruct convD2F_reg(regF dst, regD src) %{
2629N/A match(Set dst (ConvD2F src));
2629N/A format %{ "FDTOS $src,$dst" %}
2629N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
2629N/A ins_encode(form3_opf_rs2D_rdF(src, dst));
2629N/A// Convert a double to an int in a float register.
2629N/A// If the double is a NAN, stuff a zero in instead.
2629N/Ainstruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
2629N/A effect(DEF dst, USE src, KILL fcc0);
2629N/A format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
2629N/A "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
2629N/A "FDTOI $src,$dst\t! convert in delay slot\n\t"
2629N/A "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
2629N/A ins_encode(form_d2i_helper(src,dst));
2629N/Ainstruct convD2I_stk(stackSlotI dst, regD src) %{
2629N/A match(Set dst (ConvD2I src));
2629N/A ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
2629N/Ainstruct convD2I_reg(iRegI dst, regD src) %{
2629N/A match(Set dst (ConvD2I src));
2629N/A ins_cost(DEFAULT_COST*2 + BRANCH_COST);
2629N/A// Convert a double to a long in a double register.
2629N/A// If the double is a NAN, stuff a zero in instead.
2629N/Ainstruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
2629N/A effect(DEF dst, USE src, KILL fcc0);
2629N/A format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
2629N/A "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
2629N/A "FDTOX $src,$dst\t! convert in delay slot\n\t"
2629N/A "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
2629N/A ins_encode(form_d2l_helper(src,dst));
2629N/Ainstruct convD2L_stk(stackSlotL dst, regD src) %{
2629N/A match(Set dst (ConvD2L src));
2629N/A ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
2629N/Ainstruct convD2L_reg(iRegL dst, regD src) %{
2629N/A match(Set dst (ConvD2L src));
2629N/A ins_cost(DEFAULT_COST*2 + BRANCH_COST);
2629N/Ainstruct convF2D_reg(regD dst, regF src) %{
2629N/A match(Set dst (ConvF2D src));
2629N/A format %{ "FSTOD $src,$dst" %}
2629N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
2629N/A ins_encode(form3_opf_rs2F_rdD(src, dst));
2629N/A// Convert a float to an int in a float register.
2629N/A// If the float is a NAN, stuff a zero in instead.
2629N/Ainstruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
2629N/A effect(DEF dst, USE src, KILL fcc0);
2629N/A format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
2629N/A "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
2629N/A "FSTOI $src,$dst\t! convert in delay slot\n\t"
2629N/A "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
2629N/A ins_encode(form_f2i_helper(src,dst));
2629N/Ainstruct convF2I_stk(stackSlotI dst, regF src) %{
2629N/A match(Set dst (ConvF2I src));
2629N/A ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
2629N/Ainstruct convF2I_reg(iRegI dst, regF src) %{
2629N/A match(Set dst (ConvF2I src));
2629N/A ins_cost(DEFAULT_COST*2 + BRANCH_COST);
2629N/A// Convert a float to a long in a float register.
2629N/A// If the float is a NAN, stuff a zero in instead.
2629N/Ainstruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
2629N/A effect(DEF dst, USE src, KILL fcc0);
2629N/A format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
2629N/A "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
2629N/A "FSTOX $src,$dst\t! convert in delay slot\n\t"
2629N/A "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
2629N/A ins_encode(form_f2l_helper(src,dst));
2629N/Ainstruct convF2L_stk(stackSlotL dst, regF src) %{
2629N/A match(Set dst (ConvF2L src));
2629N/A ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
2629N/Ainstruct convF2L_reg(iRegL dst, regF src) %{
2629N/A match(Set dst (ConvF2L src));
2629N/A ins_cost(DEFAULT_COST*2 + BRANCH_COST);
2629N/Ainstruct convI2D_helper(regD dst, regF tmp) %{
2629N/A format %{ "FITOD $tmp,$dst" %}
2629N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
2629N/A ins_encode(form3_opf_rs2F_rdD(tmp, dst));
2629N/Ainstruct convI2D_stk(stackSlotI src, regD dst) %{
2629N/A match(Set dst (ConvI2D src));
2629N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
2629N/Ainstruct convI2D_reg(regD_low dst, iRegI src) %{
2629N/A match(Set dst (ConvI2D src));
2629N/Ainstruct convI2D_mem(regD_low dst, memory mem) %{
2629N/A match(Set dst (ConvI2D (LoadI mem)));
2629N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
2629N/A format %{ "LDF $mem,$dst\n\t"
2629N/A opcode(Assembler::ldf_op3, Assembler::fitod_opf);
2629N/A ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
2629N/Ainstruct convI2F_helper(regF dst, regF tmp) %{
2629N/A format %{ "FITOS $tmp,$dst" %}
2629N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
2629N/A ins_encode(form3_opf_rs2F_rdF(tmp, dst));
2629N/Ainstruct convI2F_stk(regF dst, stackSlotI src) %{
2629N/A match(Set dst (ConvI2F src));
2629N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
2629N/Ainstruct convI2F_reg(regF dst, iRegI src) %{
2629N/A match(Set dst (ConvI2F src));
2629N/Ainstruct convI2F_mem( regF dst, memory mem ) %{
2629N/A match(Set dst (ConvI2F (LoadI mem)));
2629N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
2629N/A format %{ "LDF $mem,$dst\n\t"
2629N/A opcode(Assembler::ldf_op3, Assembler::fitos_opf);
2629N/A ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
2629N/Ainstruct convI2L_reg(iRegL dst, iRegI src) %{
2629N/A match(Set dst (ConvI2L src));
2629N/A format %{ "SRA $src,0,$dst\t! int->long" %}
2629N/A opcode(Assembler::sra_op3, Assembler::arith_op);
2629N/A ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
2629N/A// Zero-extend convert int to long
2629N/Ainstruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
2629N/A match(Set dst (AndL (ConvI2L src) mask) );
2629N/A format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
2629N/A opcode(Assembler::srl_op3, Assembler::arith_op);
2629N/A ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
2629N/Ainstruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
2629N/A match(Set dst (AndL src mask) );
2629N/A format %{ "SRL $src,0,$dst\t! zero-extend long" %}
2629N/A opcode(Assembler::srl_op3, Assembler::arith_op);
2629N/A ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
0N/A// Long to Double conversion using V8 opcodes.
0N/A// Still useful because cheetah traps and becomes
0N/A// amazingly slow for some common numbers.
0N/A// Magic constant, 0x43300000
0N/Ainstruct loadConI_x43300000(iRegI dst) %{
0N/A format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
0N/A ins_encode(SetHi22(0x43300000, dst));
0N/A ins_pipe(ialu_none);
0N/A// Magic constant, 0x41f00000
0N/Ainstruct loadConI_x41f00000(iRegI dst) %{
0N/A format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
0N/A ins_encode(SetHi22(0x41f00000, dst));
0N/A ins_pipe(ialu_none);
0N/A// Construct a double from two float halves
0N/Ainstruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
0N/A ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
0N/A ins_pipe(faddD_reg_reg);
0N/A// Convert integer in high half of a double register (in the lower half of
0N/A// the double register file) to double
0N/Ainstruct convI2D_regDHi_regD(regD dst, regD_low src) %{
0N/A effect(DEF dst, USE src);
0N/A format %{ "FITOD $src,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
0N/A ins_encode(form3_opf_rs2D_rdD(src, dst));
0N/A ins_pipe(fcvtLHi2D);
0N/A// Add float double precision
0N/Ainstruct addD_regD_regD(regD dst, regD src1, regD src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "FADDD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(faddD_reg_reg);
0N/A// Sub float double precision
0N/Ainstruct subD_regD_regD(regD dst, regD src1, regD src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "FSUBD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(faddD_reg_reg);
0N/A// Mul float double precision
0N/Ainstruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
0N/A effect(DEF dst, USE src1, USE src2);
0N/A format %{ "FMULD $src1,$src2,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
0N/A ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
0N/A ins_pipe(fmulD_reg_reg);
0N/Ainstruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
0N/A match(Set dst (ConvL2D src));
0N/A ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
0N/A stackSlotL lx43300000;
0N/A stackSlotL lx41f00000;
0N/A regD_low dx43300000;
0N/A stkL_to_regD(tmpsrc, src);
0N/A loadConI_x43300000(ix43300000);
0N/A loadConI_x41f00000(ix41f00000);
0N/A regI_to_stkLHi(lx43300000, ix43300000);
0N/A regI_to_stkLHi(lx41f00000, ix41f00000);
0N/A stkL_to_regD(dx43300000, lx43300000);
0N/A stkL_to_regD(dx41f00000, lx41f00000);
0N/A convI2D_regDHi_regD(tmp1, tmpsrc);
0N/A regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
0N/A subD_regD_regD(tmp3, tmp2, dx43300000);
0N/A mulD_regD_regD(tmp4, tmp1, dx41f00000);
0N/A addD_regD_regD(dst, tmp3, tmp4);
0N/A// Long to Double conversion using fast fxtof
0N/Ainstruct convL2D_helper(regD dst, regD tmp) %{
0N/A effect(DEF dst, USE tmp);
0N/A format %{ "FXTOD $tmp,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
0N/A ins_encode(form3_opf_rs2D_rdD(tmp, dst));
2629N/Ainstruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
0N/A predicate(VM_Version::has_fast_fxtof());
0N/A match(Set dst (ConvL2D src));
0N/A ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
0N/A stkL_to_regD(tmp, src);
0N/A convL2D_helper(dst, tmp);
2629N/Ainstruct convL2D_reg(regD dst, iRegL src) %{
2629N/A match(Set dst (ConvL2D src));
0N/A// Long to Float conversion using fast fxtof
0N/Ainstruct convL2F_helper(regF dst, regD tmp) %{
0N/A effect(DEF dst, USE tmp);
0N/A format %{ "FXTOS $tmp,$dst" %}
0N/A opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
0N/A ins_encode(form3_opf_rs2D_rdF(tmp, dst));
2629N/Ainstruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
0N/A match(Set dst (ConvL2F src));
0N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
0N/A stkL_to_regD(tmp, src);
0N/A convL2F_helper(dst, tmp);
2629N/Ainstruct convL2F_reg(regF dst, iRegL src) %{
2629N/A match(Set dst (ConvL2F src));
0N/Ainstruct convL2I_reg(iRegI dst, iRegL src) %{
0N/A match(Set dst (ConvL2I src));
0N/A ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
0N/A ins_pipe(ialu_move_reg_I_to_L);
0N/A format %{ "SRA $src,R_G0,$dst\t! long->int" %}
0N/A ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
0N/A// Register Shift Right Immediate
0N/Ainstruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
0N/A match(Set dst (ConvL2I (RShiftL src cnt)));
0N/A format %{ "SRAX $src,$cnt,$dst" %}
0N/A opcode(Assembler::srax_op3, Assembler::arith_op);
0N/A ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
0N/A ins_pipe(ialu_reg_imm);
0N/A// Replicate scalar to packed byte values in Double register
0N/Ainstruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
0N/A effect(DEF dst, USE src);
0N/A format %{ "SLLX $src,56,$dst\n\t"
0N/A "SRLX $dst, 8,O7\n\t"
0N/A "OR $dst,O7,$dst\n\t"
0N/A "SRLX $dst,16,O7\n\t"
0N/A "OR $dst,O7,$dst\n\t"
0N/A "SRLX $dst,32,O7\n\t"
0N/A "OR $dst,O7,$dst\t! replicate8B" %}
0N/A ins_encode( enc_repl8b(src, dst));
0N/A// Replicate scalar to packed byte values in Double register
0N/Ainstruct Repl8B_reg(stackSlotD dst, iRegI src) %{
0N/A match(Set dst (Replicate8B src));
0N/A Repl8B_reg_helper(tmp, src);
0N/A regL_to_stkD(dst, tmp);
0N/A// Replicate scalar constant to packed byte values in Double register
1919N/Ainstruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
1915N/A match(Set dst (Replicate8B con));
1915N/A format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
1915N/A // XXX This is a quick fix for 6833573.
1915N/A //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(loadConFD);
0N/A// Replicate scalar to packed char values into stack slot
0N/Ainstruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
0N/A effect(DEF dst, USE src);
0N/A format %{ "SLLX $src,48,$dst\n\t"
0N/A "SRLX $dst,16,O7\n\t"
0N/A "OR $dst,O7,$dst\n\t"
0N/A "SRLX $dst,32,O7\n\t"
0N/A "OR $dst,O7,$dst\t! replicate4C" %}
0N/A ins_encode( enc_repl4s(src, dst) );
0N/A// Replicate scalar to packed char values into stack slot
0N/Ainstruct Repl4C_reg(stackSlotD dst, iRegI src) %{
0N/A match(Set dst (Replicate4C src));
0N/A Repl4C_reg_helper(tmp, src);
0N/A regL_to_stkD(dst, tmp);
0N/A// Replicate scalar constant to packed char values in Double register
1919N/Ainstruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
1915N/A match(Set dst (Replicate4C con));
1915N/A format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
1915N/A // XXX This is a quick fix for 6833573.
1915N/A //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(loadConFD);
0N/A// Replicate scalar to packed short values into stack slot
0N/Ainstruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
0N/A effect(DEF dst, USE src);
0N/A format %{ "SLLX $src,48,$dst\n\t"
0N/A "SRLX $dst,16,O7\n\t"
0N/A "OR $dst,O7,$dst\n\t"
0N/A "SRLX $dst,32,O7\n\t"
0N/A "OR $dst,O7,$dst\t! replicate4S" %}
0N/A ins_encode( enc_repl4s(src, dst) );
0N/A// Replicate scalar to packed short values into stack slot
0N/Ainstruct Repl4S_reg(stackSlotD dst, iRegI src) %{
0N/A match(Set dst (Replicate4S src));
0N/A Repl4S_reg_helper(tmp, src);
0N/A regL_to_stkD(dst, tmp);
0N/A// Replicate scalar constant to packed short values in Double register
1919N/Ainstruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
1915N/A match(Set dst (Replicate4S con));
1915N/A format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
1915N/A // XXX This is a quick fix for 6833573.
1915N/A //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(loadConFD);
0N/A// Replicate scalar to packed int values in Double register
0N/Ainstruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
0N/A effect(DEF dst, USE src);
0N/A format %{ "SLLX $src,32,$dst\n\t"
0N/A "SRLX $dst,32,O7\n\t"
0N/A "OR $dst,O7,$dst\t! replicate2I" %}
0N/A ins_encode( enc_repl2i(src, dst));
0N/A// Replicate scalar to packed int values in Double register
0N/Ainstruct Repl2I_reg(stackSlotD dst, iRegI src) %{
0N/A match(Set dst (Replicate2I src));
0N/A Repl2I_reg_helper(tmp, src);
0N/A regL_to_stkD(dst, tmp);
0N/A// Replicate scalar zero constant to packed int values in Double register
1919N/Ainstruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
1915N/A match(Set dst (Replicate2I con));
1915N/A format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
1915N/A // XXX This is a quick fix for 6833573.
1915N/A //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
1919N/A __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
0N/A ins_pipe(loadConFD);
0N/A//----------Control Flow Instructions------------------------------------------
0N/A// Compare Instructions
0N/Ainstruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
0N/A match(Set icc (CmpI op1 op2));
0N/A effect( DEF icc, USE op1, USE op2 );
0N/A format %{ "CMP $op1,$op2" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
0N/A match(Set icc (CmpU op1 op2));
0N/A format %{ "CMP $op1,$op2\t! unsigned" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
0N/A match(Set icc (CmpI op1 op2));
0N/A effect( DEF icc, USE op1 );
0N/A format %{ "CMP $op1,$op2" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_imm);
0N/Ainstruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
0N/A match(Set icc (CmpI (AndI op1 op2) zero));
0N/A format %{ "BTST $op2,$op1" %}
0N/A opcode(Assembler::andcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg_zero);
0N/Ainstruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
0N/A match(Set icc (CmpI (AndI op1 op2) zero));
0N/A format %{ "BTST $op2,$op1" %}
0N/A opcode(Assembler::andcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_imm_zero);
0N/Ainstruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
0N/A match(Set xcc (CmpL op1 op2));
0N/A effect( DEF xcc, USE op1, USE op2 );
0N/A format %{ "CMP $op1,$op2\t\t! long" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
0N/A match(Set xcc (CmpL op1 con));
0N/A effect( DEF xcc, USE op1, USE con );
0N/A format %{ "CMP $op1,$con\t\t! long" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
0N/A match(Set xcc (CmpL (AndL op1 op2) zero));
0N/A effect( DEF xcc, USE op1, USE op2 );
0N/A format %{ "BTST $op1,$op2\t\t! long" %}
0N/A opcode(Assembler::andcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/A// useful for checking the alignment of a pointer:
0N/Ainstruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
0N/A match(Set xcc (CmpL (AndL op1 con) zero));
0N/A effect( DEF xcc, USE op1, USE con );
0N/A format %{ "BTST $op1,$con\t\t! long" %}
0N/A opcode(Assembler::andcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
0N/A match(Set icc (CmpU op1 op2));
0N/A format %{ "CMP $op1,$op2\t! unsigned" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_imm);
0N/Ainstruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
0N/A match(Set pcc (CmpP op1 op2));
0N/A format %{ "CMP $op1,$op2\t! ptr" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_reg);
0N/Ainstruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
0N/A match(Set pcc (CmpP op1 op2));
0N/A format %{ "CMP $op1,$op2\t! ptr" %}
0N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
0N/A ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
0N/A ins_pipe(ialu_cconly_reg_imm);
164N/Ainstruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
164N/A match(Set icc (CmpN op1 op2));
164N/A format %{ "CMP $op1,$op2\t! compressed ptr" %}
164N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
164N/A ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
164N/A ins_pipe(ialu_cconly_reg_reg);
164N/Ainstruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
164N/A match(Set icc (CmpN op1 op2));
164N/A format %{ "CMP $op1,$op2\t! compressed ptr" %}
164N/A opcode(Assembler::subcc_op3, Assembler::arith_op);
164N/A ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
164N/A ins_pipe(ialu_cconly_reg_imm);
0N/A//----------Max and Min--------------------------------------------------------
0N/A// Conditional move for min
0N/Ainstruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
0N/A effect( USE_DEF op2, USE op1, USE icc );
0N/A format %{ "MOVlt icc,$op1,$op2\t! min" %}
0N/A opcode(Assembler::less);
0N/A ins_encode( enc_cmov_reg_minmax(op2,op1) );
0N/A ins_pipe(ialu_reg_flags);
0N/A// Min Register with Register.
0N/Ainstruct minI_eReg(iRegI op1, iRegI op2) %{
0N/A match(Set op2 (MinI op1 op2));
0N/A ins_cost(DEFAULT_COST*2);
0N/A compI_iReg(icc,op1,op2);
0N/A cmovI_reg_lt(op2,op1,icc);
0N/A// Conditional move for max
0N/Ainstruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
0N/A effect( USE_DEF op2, USE op1, USE icc );
0N/A format %{ "MOVgt icc,$op1,$op2\t! max" %}
0N/A opcode(Assembler::greater);
0N/A ins_encode( enc_cmov_reg_minmax(op2,op1) );
0N/A ins_pipe(ialu_reg_flags);
0N/A// Max Register with Register
0N/Ainstruct maxI_eReg(iRegI op1, iRegI op2) %{
0N/A match(Set op2 (MaxI op1 op2));
0N/A ins_cost(DEFAULT_COST*2);
0N/A compI_iReg(icc,op1,op2);
0N/A cmovI_reg_gt(op2,op1,icc);
0N/A//----------Float Compares----------------------------------------------------
0N/A// Compare floating, generate condition code
0N/Ainstruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
0N/A match(Set fcc (CmpF src1 src2));
0N/A format %{ "FCMPs $fcc,$src1,$src2" %}
0N/A opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
0N/A ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
0N/A ins_pipe(faddF_fcc_reg_reg_zero);
0N/Ainstruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
0N/A match(Set fcc (CmpD src1 src2));
0N/A format %{ "FCMPd $fcc,$src1,$src2" %}
0N/A opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
0N/A ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
0N/A ins_pipe(faddD_fcc_reg_reg_zero);
0N/A// Compare floating, generate -1,0,1
0N/Ainstruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
0N/A match(Set dst (CmpF3 src1 src2));
0N/A ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
0N/A format %{ "fcmpl $dst,$src1,$src2" %}
0N/A ins_encode( floating_cmp( dst, src1, src2 ) );
0N/A ins_pipe( floating_cmp );
0N/Ainstruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
0N/A match(Set dst (CmpD3 src1 src2));
0N/A ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
0N/A format %{ "dcmpl $dst,$src1,$src2" %}
0N/A // Primary = double (not float)
0N/A ins_encode( floating_cmp( dst, src1, src2 ) );
0N/A ins_pipe( floating_cmp );
0N/A//----------Branches---------------------------------------------------------
0N/A// (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
0N/Ainstruct jumpXtnd(iRegX switch_val, o7RegI table) %{
0N/A match(Jump switch_val);
1915N/A format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
1915N/A "LD [O7 + $switch_val], O7\n\t"
1915N/A // Calculate table address into a register.
2957N/A // If we are calculating the size of this instruction don't trust
2957N/A // zero offsets because they might change when
2957N/A // MachConstantBaseNode decides to optimize the constant table
2957N/A if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
1915N/A table_reg = $constanttablebase;
1919N/A RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
1919N/A __ add($constanttablebase, con_offset, table_reg);
1915N/A // Jump to base address + switch value
1915N/A __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
0N/A ins_pipe(ialu_reg_reg);
0N/A// Direct Branch. Use V8 version with longer range.
0N/Ainstruct branch(label labl) %{
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BA $labl" %}
2676N/A// Direct Branch, short with no delay slot
2676N/Ainstruct branch_short(label labl) %{
2676N/A format %{ "BA $labl\t! short branch" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
0N/A// Conditional Direct Branch
0N/Ainstruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BP$cmp $icc,$labl" %}
0N/A // Prim = bits 24-22, Secnd = bits 31-30
0N/A ins_encode( enc_bp( labl, cmp, icc ) );
0N/Ainstruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
0N/A format %{ "BP$cmp $icc,$labl" %}
0N/A // Prim = bits 24-22, Secnd = bits 31-30
0N/A ins_encode( enc_bp( labl, cmp, icc ) );
0N/Ainstruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BP$cmp $pcc,$labl" %}
2664N/A Assembler::Predict predict_taken =
2664N/A __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
0N/Ainstruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "FBP$cmp $fcc,$labl" %}
2664N/A Assembler::Predict predict_taken =
2664N/A __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
0N/Ainstruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
0N/A match(CountedLoopEnd cmp icc);
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BP$cmp $icc,$labl\t! Loop end" %}
0N/A // Prim = bits 24-22, Secnd = bits 31-30
0N/A ins_encode( enc_bp( labl, cmp, icc ) );
0N/Ainstruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
0N/A match(CountedLoopEnd cmp icc);
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BP$cmp $icc,$labl\t! Loop end" %}
0N/A // Prim = bits 24-22, Secnd = bits 31-30
0N/A ins_encode( enc_bp( labl, cmp, icc ) );
2676N/A// Compare and branch instructions
2676N/Ainstruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! int\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! int\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$constant);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
2676N/A match(If cmp (CmpU op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! unsigned\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
2676N/A match(If cmp (CmpU op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! unsigned\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$constant);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
2676N/A match(If cmp (CmpL op1 op2));
2676N/A effect(USE labl, KILL xcc);
2676N/A format %{ "CMP $op1,$op2\t! long\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
2676N/Ainstruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
2676N/A match(If cmp (CmpL op1 op2));
2676N/A effect(USE labl, KILL xcc);
2676N/A format %{ "CMP $op1,$op2\t! long\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$constant);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
2676N/A// Compare Pointers and branch
2676N/Ainstruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
2676N/A match(If cmp (CmpP op1 op2));
2676N/A effect(USE labl, KILL pcc);
2676N/A format %{ "CMP $op1,$op2\t! ptr\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
2676N/Ainstruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
2676N/A match(If cmp (CmpP op1 null));
2676N/A effect(USE labl, KILL pcc);
2676N/A format %{ "CMP $op1,0\t! ptr\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, G0);
2676N/A // bpr() is not used here since it has shorter distance.
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
2676N/Ainstruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpN op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpN op1 null));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,0\t! compressed ptr\n\t"
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, G0);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
2676N/A match(CountedLoopEnd cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! int\n\t"
2676N/A "BP$cmp $labl\t! Loop end" %}
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$Register);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/Ainstruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
2676N/A match(CountedLoopEnd cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CMP $op1,$op2\t! int\n\t"
2676N/A "BP$cmp $labl\t! Loop end" %}
2676N/A Assembler::Predict predict_taken =
2676N/A __ cmp($op1$$Register, $op2$$constant);
2676N/A __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2676N/A// Short compare and branch instructions
2676N/Ainstruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
2676N/Ainstruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
2676N/A match(If cmp (CmpU op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
2676N/A match(If cmp (CmpU op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
2676N/Ainstruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
2676N/A match(If cmp (CmpL op1 op2));
2676N/A effect(USE labl, KILL xcc);
2676N/A format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
2676N/A match(If cmp (CmpL op1 op2));
2676N/A effect(USE labl, KILL xcc);
2676N/A format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
2676N/A// Compare Pointers and branch
2676N/Ainstruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
2676N/A match(If cmp (CmpP op1 op2));
2676N/A effect(USE labl, KILL pcc);
2676N/A format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
2676N/A match(If cmp (CmpP op1 null));
2676N/A effect(USE labl, KILL pcc);
2676N/A format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
2676N/A format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
2676N/Ainstruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpN op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
2676N/A match(If cmp (CmpN op1 null));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
2676N/Ainstruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
2676N/A match(CountedLoopEnd cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
2676N/Ainstruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
2676N/A match(CountedLoopEnd cmp (CmpI op1 op2));
2676N/A effect(USE labl, KILL icc);
2676N/A format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
2676N/A assert(__ use_cbcond(*L), "back to back cbcond");
2676N/A __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
2676N/A// Branch-on-register tests all 64 bits. We assume that values
2676N/A// in 64-bit registers always remains zero or sign extended
2676N/A// unless our code munges the high bits. Interrupts can chop
2676N/A// the high order bits to zero or sign at any time.
2676N/Ainstruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
2676N/A match(If cmp (CmpI op1 zero));
2676N/A predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
2676N/A format %{ "BR$cmp $op1,$labl" %}
2676N/A ins_encode( enc_bpr( labl, cmp, op1 ) );
2676N/Ainstruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
2676N/A match(If cmp (CmpP op1 null));
2676N/A predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
2676N/A format %{ "BR$cmp $op1,$labl" %}
2676N/A ins_encode( enc_bpr( labl, cmp, op1 ) );
2676N/Ainstruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
2676N/A match(If cmp (CmpL op1 zero));
2676N/A predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
2676N/A format %{ "BR$cmp $op1,$labl" %}
2676N/A ins_encode( enc_bpr( labl, cmp, op1 ) );
0N/A// ============================================================================
0N/A// Currently we hold longs in 2 registers. Comparing such values efficiently
0N/A// is tricky. The flavor of compare used depends on whether we are testing
0N/A// for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
0N/A// The GE test is the negated LT test. The LE test can be had by commuting
0N/A// the operands (yielding a GE test) and then negating; negate again for the
0N/A// GT test. The EQ test is done by ORcc'ing the high and low halves, and the
0N/A// NE test is negated from that.
0N/A// Due to a shortcoming in the ADLC, it mixes up expressions like:
0N/A// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
0N/A// difference between 'Y' and '0L'. The tree-matches for the CmpI sections
0N/A// are collapsed internally in the ADLC's dfa-gen code. The match for
0N/A// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
0N/A// foo match ends up with the wrong leaf. One fix is to not match both
0N/A// reg-reg and reg-zero forms of long-compare. This is unfortunate because
0N/A// both forms beat the trinary form of long-compare and both are very useful
0N/A// on Intel which has so few registers.
0N/Ainstruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
0N/A ins_cost(BRANCH_COST);
0N/A format %{ "BP$cmp $xcc,$labl" %}
2664N/A Assembler::Predict predict_taken =
2664N/A __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
0N/A// Manifest a CmpL3 result in an integer register. Very painful.
0N/A// This is the test to avoid.
0N/Ainstruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
0N/A match(Set dst (CmpL3 src1 src2) );
0N/A ins_cost(6*DEFAULT_COST);
0N/A format %{ "CMP $src1,$src2\t\t! long\n"
0N/A "\tMOV -1,$dst\t! delay slot\n"
0N/A "\tMOV 1,$dst\t! delay slot\n"
0N/A ins_encode( cmpl_flag(src1,src2,dst) );
0N/Ainstruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
0N/A match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
0N/A match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
0N/A match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
0N/A match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
164N/Ainstruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
164N/A match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
164N/A format %{ "MOV$cmp $xcc,$src,$dst" %}
164N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
0N/A match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
0N/A match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "MOV$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
0N/Ainstruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
0N/A match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "FMOVS$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
0N/A ins_pipe(int_conditional_float_move);
0N/Ainstruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
0N/A match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
0N/A format %{ "FMOVD$cmp $xcc,$src,$dst" %}
0N/A ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
0N/A ins_pipe(int_conditional_float_move);
0N/A// ============================================================================
0N/A// Safepoint Instruction
0N/Ainstruct safePoint_poll(iRegP poll) %{
0N/A match(SafePoint poll);
0N/A format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
0N/A format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
0N/A __ relocate(relocInfo::poll_type);
0N/A __ ld_ptr($poll$$Register, 0, G0);
0N/A ins_pipe(loadPollP);
0N/A// ============================================================================
0N/A// Call Java Static Instruction
0N/Ainstruct CallStaticJavaDirect( method meth ) %{
0N/A match(CallStaticJava);
1487N/A predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
0N/A ins_cost(CALL_COST);
0N/A format %{ "CALL,static ; NOP ==> " %}
0N/A ins_encode( Java_Static_Call( meth ), call_epilog );
0N/A ins_pipe(simple_call);
1487N/A// Call Java Static Instruction (method handle version)
1487N/Ainstruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
1487N/A predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
1487N/A effect(USE meth, KILL l7_mh_SP_save);
1487N/A ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
0N/A// Call Java Dynamic Instruction
0N/Ainstruct CallDynamicJavaDirect( method meth ) %{
0N/A match(CallDynamicJava);
0N/A ins_cost(CALL_COST);
0N/A format %{ "SET (empty),R_G5\n\t"
0N/A "CALL,dynamic ; NOP ==> " %}
0N/A ins_encode( Java_Dynamic_Call( meth ), call_epilog );
0N/A// Call Runtime Instruction
0N/Ainstruct CallRuntimeDirect(method meth, l7RegP l7) %{
0N/A effect(USE meth, KILL l7);
0N/A ins_cost(CALL_COST);
0N/A format %{ "CALL,runtime" %}
0N/A ins_encode( Java_To_Runtime( meth ),
0N/A call_epilog, adjust_long_from_native_call );
0N/A ins_pipe(simple_call);
0N/A// Call runtime without safepoint - same as CallRuntime
0N/Ainstruct CallLeafDirect(method meth, l7RegP l7) %{
0N/A effect(USE meth, KILL l7);
0N/A ins_cost(CALL_COST);
0N/A format %{ "CALL,runtime leaf" %}
0N/A ins_encode( Java_To_Runtime( meth ),
0N/A adjust_long_from_native_call );
0N/A ins_pipe(simple_call);
0N/A// Call runtime without safepoint - same as CallLeaf
0N/Ainstruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
0N/A match(CallLeafNoFP);
0N/A effect(USE meth, KILL l7);
0N/A ins_cost(CALL_COST);
0N/A format %{ "CALL,runtime leaf nofp" %}
0N/A ins_encode( Java_To_Runtime( meth ),
0N/A adjust_long_from_native_call );
0N/A ins_pipe(simple_call);
0N/A// Tail Call; Jump from runtime stub to Java code.
0N/A// Also known as an 'interprocedural jump'.
0N/A// Target of jump will eventually return to caller.
0N/A// TailJump below removes the return address.
0N/Ainstruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
0N/A match(TailCall jump_target method_oop );
0N/A ins_cost(CALL_COST);
0N/A format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
0N/A ins_encode(form_jmpl(jump_target));
0N/A ins_pipe(tail_call);
0N/A// Return Instruction
0N/A // The epilogue node did the ret already.
0N/A format %{ "! return" %}
0N/A// Tail Jump; remove the return address; jump to target.
0N/A// TailCall above leaves the return address around.
0N/A// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
0N/A// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
0N/A// "restore" before this instruction (in Epilogue), we need to materialize it
0N/Ainstruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
0N/A match( TailJump jump_target ex_oop );
0N/A ins_cost(CALL_COST);
0N/A format %{ "! discard R_O7\n\t"
0N/A "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
0N/A ins_encode(form_jmpl_set_exception_pc(jump_target));
0N/A // opcode(Assembler::jmpl_op3, Assembler::arith_op);
0N/A // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
0N/A // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
0N/A ins_pipe(tail_call);
0N/A// Create exception oop: created by stack-crawling runtime code.
0N/A// Created exception is now available to this handler, and is setup
0N/A// just prior to jumping to this handler. No code emitted.
0N/Ainstruct CreateException( o0RegP ex_oop )
0N/A match(Set ex_oop (CreateEx));
0N/A // use the following format syntax
0N/A format %{ "! exception oop is in R_O0; no code emitted" %}
0N/A// Rethrow exception:
0N/A// The exception oop will come in the first argument position.
0N/A// Then JUMP (not call) to the rethrow stub code.
0N/Ainstruct RethrowException()
0N/A ins_cost(CALL_COST);
0N/A // use the following format syntax
0N/A format %{ "Jmp rethrow_stub" %}
0N/A ins_encode(enc_rethrow);
0N/A ins_pipe(tail_call);
0N/Ainstruct ShouldNotReachHere( )
0N/A ins_cost(CALL_COST);
0N/A // Use the following format syntax
0N/A format %{ "ILLTRAP ; ShouldNotReachHere" %}
0N/A ins_encode( form2_illtrap() );
0N/A ins_pipe(tail_call);
0N/A// ============================================================================
0N/A// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
0N/A// array for an instance of the superklass. Set a hidden internal cache on a
0N/A// hit (cache is checked with exposed code in gen_subtype_check()). Return
0N/A// not zero for a miss or zero for a hit. The encoding ALSO sets flags.
0N/Ainstruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
0N/A match(Set index (PartialSubtypeCheck sub super));
0N/A effect( KILL pcc, KILL o7 );
0N/A ins_cost(DEFAULT_COST*10);
0N/A format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
0N/A ins_encode( enc_PartialSubtypeCheck() );
0N/A ins_pipe(partial_subtype_check_pipe);
0N/Ainstruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
0N/A match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
0N/A effect( KILL idx, KILL o7 );
0N/A ins_cost(DEFAULT_COST*10);
0N/A format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
0N/A ins_encode( enc_PartialSubtypeCheck() );
0N/A ins_pipe(partial_subtype_check_pipe);
0N/A// ============================================================================
0N/A// inlined locking and unlocking
0N/Ainstruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
0N/A match(Set pcc (FastLock object box));
0N/A effect(KILL scratch, TEMP scratch2);
0N/A format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
0N/A ins_encode( Fast_Lock(object, box, scratch, scratch2) );
0N/A ins_pipe(long_memory_op);
0N/Ainstruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
0N/A match(Set pcc (FastUnlock object box));
0N/A effect(KILL scratch, TEMP scratch2);
0N/A format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
0N/A ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
0N/A ins_pipe(long_memory_op);
2726N/A// The encodings are generic.
0N/Ainstruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
2726N/A predicate(!use_block_zeroing(n->in(2)) );
0N/A match(Set dummy (ClearArray cnt base));
0N/A effect(TEMP temp, KILL ccr);
0N/A format %{ "MOV $cnt,$temp\n"
0N/A "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
0N/A " BRge loop\t\t! Clearing loop\n"
0N/A " STX G0,[$base+$temp]\t! delay slot" %}
2726N/A // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2726N/A Register nof_bytes_arg = $cnt$$Register;
2726N/A Register nof_bytes_tmp = $temp$$Register;
2726N/A Register base_pointer_arg = $base$$Register;
2726N/A __ mov(nof_bytes_arg, nof_bytes_tmp);
2726N/A // Loop and clear, walking backwards through the array.
2726N/A // nof_bytes_tmp (if >0) is always the number of bytes to zero
2726N/A __ deccc(nof_bytes_tmp, 8);
2726N/A __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2726N/A __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2726N/A // %%%% this mini-loop must not cross a cache boundary!
2726N/Ainstruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
2726N/A predicate(use_block_zeroing(n->in(2)));
2726N/A match(Set dummy (ClearArray cnt base));
2726N/A effect(USE_KILL cnt, USE_KILL base, KILL ccr);
2726N/A format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
2726N/A assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
2726N/A Register to = $base$$Register;
2726N/A Register count = $cnt$$Register;
2726N/A __ nop(); // Separate short branches
2726N/A // Use BIS for zeroing (temp is not used).
2726N/A __ bis_zeroing(to, count, G0, Ldone);
2726N/Ainstruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
2726N/A predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
2726N/A match(Set dummy (ClearArray cnt base));
2726N/A effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
2726N/A format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
2726N/A assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
2726N/A Register to = $base$$Register;
2726N/A Register count = $cnt$$Register;
2726N/A Register temp = $tmp$$Register;
2726N/A __ nop(); // Separate short branches
2726N/A __ bis_zeroing(to, count, temp, Ldone);
0N/A ins_pipe(long_memory_op);
986N/Ainstruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
986N/A o7RegI tmp, flagsReg ccr) %{
986N/A match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
986N/A effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
986N/A format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
986N/A ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
0N/A ins_pipe(long_memory_op);
986N/Ainstruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
986N/A o7RegI tmp, flagsReg ccr) %{
986N/A match(Set result (StrEquals (Binary str1 str2) cnt));
986N/A effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
986N/A format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
986N/A ins_encode( enc_String_Equals(str1, str2, cnt, result) );
681N/A ins_pipe(long_memory_op);
986N/Ainstruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
986N/A o7RegI tmp2, flagsReg ccr) %{
681N/A match(Set result (AryEq ary1 ary2));
681N/A effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
986N/A format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
986N/A ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
681N/A ins_pipe(long_memory_op);
775N/A//---------- Zeros Count Instructions ------------------------------------------
775N/Ainstruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
775N/A predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
775N/A match(Set dst (CountLeadingZerosI src));
775N/A effect(TEMP dst, TEMP tmp, KILL cr);
775N/A // return (WORDBITS - popc(x));
1041N/A format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
1041N/A "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "SUB $tmp,$dst,$dst" %}
775N/A Register Rdst = $dst$$Register;
775N/A Register Rsrc = $src$$Register;
775N/A Register Rtmp = $tmp$$Register;
775N/A __ or3(Rdst, Rtmp, Rdst);
775N/A __ or3(Rdst, Rtmp, Rdst);
775N/A __ or3(Rdst, Rtmp, Rdst);
775N/A __ or3(Rdst, Rtmp, Rdst);
775N/A __ mov(BitsPerInt, Rtmp);
775N/A __ sub(Rtmp, Rdst, Rdst);
1835N/Ainstruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
775N/A predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
775N/A match(Set dst (CountLeadingZerosL src));
775N/A effect(TEMP dst, TEMP tmp, KILL cr);
775N/A // return (WORDBITS - popc(x));
1041N/A format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
775N/A "OR $src,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "SRLX $dst,16,$tmp\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "SRLX $dst,32,$tmp\n\t"
775N/A "OR $dst,$tmp,$dst\n\t"
775N/A "SUB $tmp,$dst,$dst" %}
775N/A Register Rdst = $dst$$Register;
775N/A Register Rsrc = $src$$Register;
775N/A Register Rtmp = $tmp$$Register;
775N/A __ mov(BitsPerLong, Rtmp);
775N/A __ sub(Rtmp, Rdst, Rdst);
775N/Ainstruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
775N/A predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
775N/A match(Set dst (CountTrailingZerosI src));
775N/A effect(TEMP dst, KILL cr);
775N/A // return popc(~x & (x - 1));
775N/A format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
775N/A "ANDN $dst,$src,$dst\n\t"
775N/A "SRL $dst,R_G0,$dst\n\t"
775N/A Register Rdst = $dst$$Register;
775N/A Register Rsrc = $src$$Register;
775N/A __ andn(Rdst, Rsrc, Rdst);
775N/A __ srl(Rdst, G0, Rdst);
2839N/Ainstruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
775N/A predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
775N/A match(Set dst (CountTrailingZerosL src));
775N/A effect(TEMP dst, KILL cr);
775N/A // return popc(~x & (x - 1));
775N/A format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
775N/A "ANDN $dst,$src,$dst\n\t"
775N/A Register Rdst = $dst$$Register;
775N/A Register Rsrc = $src$$Register;
775N/A __ andn(Rdst, Rsrc, Rdst);
643N/A//---------- Population Count Instructions -------------------------------------
643N/Ainstruct popCountI(iRegI dst, iRegI src) %{
643N/A predicate(UsePopCountInstruction);
643N/A match(Set dst (PopCountI src));
643N/A format %{ "POPC $src, $dst" %}
643N/A __ popc($src$$Register, $dst$$Register);
643N/Ainstruct popCountL(iRegI dst, iRegL src) %{
643N/A predicate(UsePopCountInstruction);
643N/A match(Set dst (PopCountL src));
643N/A format %{ "POPC $src, $dst" %}
643N/A __ popc($src$$Register, $dst$$Register);
0N/A// ============================================================================
0N/A//------------Bytes reverse--------------------------------------------------
0N/Ainstruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
0N/A match(Set dst (ReverseBytesI src));
1396N/A // Op cost is artificially doubled to make sure that load or store
1396N/A // instructions are preferred over this one which requires a spill
1396N/A ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
1396N/A format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
1396N/A __ set($src$$disp + STACK_BIAS, O7);
1396N/A __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
1396N/Ainstruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
1396N/A match(Set dst (ReverseBytesL src));
0N/A // Op cost is artificially doubled to make sure that load or store
0N/A // instructions are preferred over this one which requires a spill
0N/A // onto a stack slot.
0N/A ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
1396N/A format %{ "LDXA $src, $dst\t!asi=primary_little" %}
1396N/A __ set($src$$disp + STACK_BIAS, O7);
1396N/A __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
0N/A ins_pipe( iload_mem );
1396N/Ainstruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
1396N/A match(Set dst (ReverseBytesUS src));
1396N/A // Op cost is artificially doubled to make sure that load or store
1396N/A // instructions are preferred over this one which requires a spill
1396N/A ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
1396N/A format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
1396N/A // the value was spilled as an int so bias the load
1396N/A __ set($src$$disp + STACK_BIAS + 2, O7);
1396N/A __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
1396N/Ainstruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
1396N/A match(Set dst (ReverseBytesS src));
0N/A // Op cost is artificially doubled to make sure that load or store
0N/A // instructions are preferred over this one which requires a spill
0N/A // onto a stack slot.
0N/A ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
1396N/A format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
1396N/A // the value was spilled as an int so bias the load
1396N/A __ set($src$$disp + STACK_BIAS + 2, O7);
1396N/A __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
0N/A ins_pipe( iload_mem );
0N/A// Load Integer reversed byte order
1396N/Ainstruct loadI_reversed(iRegI dst, indIndexMemory src) %{
0N/A match(Set dst (ReverseBytesI (LoadI src)));
0N/A ins_cost(DEFAULT_COST + MEMORY_REF_COST);
0N/A format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
1396N/A __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
0N/A ins_pipe(iload_mem);
0N/A// Load Long - aligned and reversed
1396N/Ainstruct loadL_reversed(iRegL dst, indIndexMemory src) %{
0N/A match(Set dst (ReverseBytesL (LoadL src)));
0N/A format %{ "LDXA $src, $dst\t!asi=primary_little" %}
1396N/A __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
1396N/A// Load unsigned short / char reversed byte order
1396N/Ainstruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
1396N/A match(Set dst (ReverseBytesUS (LoadUS src)));
1396N/A format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
1396N/A __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
1396N/A// Load short reversed byte order
1396N/Ainstruct loadS_reversed(iRegI dst, indIndexMemory src) %{
1396N/A match(Set dst (ReverseBytesS (LoadS src)));
1396N/A format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
1396N/A __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
0N/A ins_pipe(iload_mem);
0N/A// Store Integer reversed byte order
1396N/Ainstruct storeI_reversed(indIndexMemory dst, iRegI src) %{
0N/A match(Set dst (StoreI dst (ReverseBytesI src)));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STWA $src, $dst\t!asi=primary_little" %}
1396N/A __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
0N/A ins_pipe(istore_mem_reg);
0N/A// Store Long reversed byte order
1396N/Ainstruct storeL_reversed(indIndexMemory dst, iRegL src) %{
0N/A match(Set dst (StoreL dst (ReverseBytesL src)));
0N/A ins_cost(MEMORY_REF_COST);
0N/A format %{ "STXA $src, $dst\t!asi=primary_little" %}
1396N/A __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
1396N/Ainstruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
1396N/A match(Set dst (StoreC dst (ReverseBytesUS src)));
1396N/A format %{ "STHA $src, $dst\t!asi=primary_little" %}
1396N/A __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
1396N/A// Store short reversed byte order
1396N/Ainstruct storeS_reversed(indIndexMemory dst, iRegI src) %{
1396N/A match(Set dst (StoreC dst (ReverseBytesS src)));
1396N/A format %{ "STHA $src, $dst\t!asi=primary_little" %}
1396N/A __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
0N/A ins_pipe(istore_mem_reg);
0N/A//----------PEEPHOLE RULES-----------------------------------------------------
0N/A// These must follow all instruction definitions as they use the names
0N/A// defined in the instructions definitions.
605N/A// peepmatch ( root_instr_name [preceding_instruction]* );
0N/A// // instruction numbers are zero-based using left to right order in peepmatch
0N/A// // in the replacement instruction's match rule
0N/A// ---------VM FLAGS---------------------------------------------------------
0N/A// All peephole optimizations can be turned off using -XX:-OptoPeephole
0N/A// Each peephole rule is given an identifying number starting with zero and
0N/A// increasing by one in the order seen by the parser. An individual peephole
0N/A// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
0N/A// on the command-line.
0N/A// ---------CURRENT LIMITATIONS----------------------------------------------
0N/A// Only match adjacent instructions in same basic block
0N/A// Only equality constraints
0N/A// Only one replacement instruction
0N/A// ---------EXAMPLE----------------------------------------------------------
0N/A// // pertinent parts of existing instructions in architecture description
0N/A// instruct movI(eRegI dst, eRegI src) %{
0N/A// match(Set dst (CopyI src));
0N/A// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
0N/A// match(Set dst (AddI dst src));
0N/A// // Change (inc mov) to lea
0N/A// // increment preceeded by register-register move
0N/A// peepmatch ( incI_eReg movI );
0N/A// // require that the destination register of the increment
0N/A// // match the destination register of the move
0N/A// // construct a replacement instruction that sets
0N/A// // the destination to ( move's source register + one )
0N/A// // Change load of spilled value to only a spill
0N/A// instruct storeI(memory mem, eRegI src) %{
0N/A// match(Set mem (StoreI mem src));
0N/A// instruct loadI(eRegI dst, memory mem) %{
0N/A// match(Set dst (LoadI mem));
0N/A// peepmatch ( loadI storeI );
0N/A//----------SMARTSPILL RULES---------------------------------------------------
0N/A// These must follow all instruction definitions as they use the names
0N/A// defined in the instructions definitions.
0N/A// SPARC will probably not have any of these rules due to RISC instruction set.
0N/A//----------PIPELINE-----------------------------------------------------------
0N/A// Rules which define the behavior of the target architectures pipeline.